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| author | Andrew Cagney <cagney@redhat.com> | 1997-11-05 08:17:26 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 1997-11-05 08:17:26 +0000 |
| commit | 63be8febf762353b62e794963fdc65f1280a7498 (patch) | |
| tree | 3d79e72b7f56c6597f4285efcc55562938d902ef /sim/mips/mips.igen | |
| parent | 22de994d0e830082802fdd9033af16fb34f58dde (diff) | |
| download | gdb-63be8febf762353b62e794963fdc65f1280a7498.zip gdb-63be8febf762353b62e794963fdc65f1280a7498.tar.gz gdb-63be8febf762353b62e794963fdc65f1280a7498.tar.bz2 | |
Rewrite the MIPS simulator's memory model so that it uses the generic
common/sim-core.
Add support for 3, 5, 6, 7 byte transfers to sim core.
Diffstat (limited to 'sim/mips/mips.igen')
| -rw-r--r-- | sim/mips/mips.igen | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen index 185d99e..646b78a 100644 --- a/sim/mips/mips.igen +++ b/sim/mips/mips.igen @@ -1466,7 +1466,7 @@ int byte; paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse)); byte = ((vaddr & mask) ^ bigend); - if (!!ByteSwapMem) + if (!BigEndianMem) paddr &= ~mask; LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL); GPR[destreg] = ((memval << ((7 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((7 - byte) * 8)) - 1))); @@ -1510,7 +1510,7 @@ int byte; paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse)); byte = ((vaddr & mask) ^ bigend); - if (!ByteSwapMem) + if (BigEndianMem) paddr &= ~mask; LoadMemory(&memval,&memval1,uncached,(7 - byte),paddr,vaddr,isDATA,isREAL); { @@ -1864,7 +1864,7 @@ int byte; paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse)); byte = ((vaddr & mask) ^ bigend); - if (!!ByteSwapMem) + if (!BigEndianMem) paddr &= ~mask; LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL); if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) { @@ -1914,7 +1914,7 @@ int byte; paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse)); byte = ((vaddr & mask) ^ bigend); - if (!ByteSwapMem) + if (BigEndianMem) paddr &= ~mask; LoadMemory(&memval,&memval1,uncached,(3 - byte),paddr,vaddr,isDATA,isREAL); if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) { @@ -2497,7 +2497,7 @@ int byte; paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse)); byte = ((vaddr & mask) ^ bigend); - if (!!ByteSwapMem) + if (!BigEndianMem) paddr &= ~mask; memval = (op2 >> (8 * (7 - byte))); StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL); @@ -2541,7 +2541,7 @@ int byte; paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse)); byte = ((vaddr & mask) ^ bigend); - if (!ByteSwapMem) + if (!BigEndianMem) paddr &= ~mask; memval = ((unsigned64) op2 << (byte * 8)); StoreMemory(uncached,(AccessLength_DOUBLEWORD - byte),memval,memval1,paddr,vaddr,isREAL); @@ -2996,7 +2996,7 @@ int byte; paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse)); byte = ((vaddr & mask) ^ bigend); - if (!!ByteSwapMem) + if (!BigEndianMem) paddr &= ~mask; memval = (op2 >> (8 * (3 - byte))); if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) { @@ -3045,7 +3045,7 @@ int byte; paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse)); byte = ((vaddr & mask) ^ bigend); - if (!ByteSwapMem) + if (!BigEndianMem) paddr &= ~mask; memval = ((unsigned64) op2 << (byte * 8)); if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) { |