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| author | Chris Demetriou <cgd@google.com> | 2003-01-05 07:56:59 +0000 |
|---|---|---|
| committer | Chris Demetriou <cgd@google.com> | 2003-01-05 07:56:59 +0000 |
| commit | 4c54fc26ed171989615301442435fa4dd3af9755 (patch) | |
| tree | b70c489e9be4ac83454d7e158266c54c8ac48781 /sim/mips/mips.igen | |
| parent | e6c674b8963707976fcd50ef01026fcb1a693b7d (diff) | |
| download | gdb-4c54fc26ed171989615301442435fa4dd3af9755.zip gdb-4c54fc26ed171989615301442435fa4dd3af9755.tar.gz gdb-4c54fc26ed171989615301442435fa4dd3af9755.tar.bz2 | |
2003-01-04 Richard Sandiford <rsandifo@redhat.com>
Andrew Cagney <ac131313@redhat.com>
Gavin Romig-Koch <gavin@redhat.com>
Graydon Hoare <graydon@redhat.com>
Aldy Hernandez <aldyh@redhat.com>
Dave Brolley <brolley@redhat.com>
Chris Demetriou <cgd@broadcom.com>
* configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
(sim_mach_default): New variable.
(mips64vr-*-*, mips64vrel-*-*): New configurations.
Add a new simulator generator, MULTI.
* configure: Regenerate.
* Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
(multi-run.o): New dependency.
(SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
(tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
(tmp-multi): Combine them.
(BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
(clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
(distclean-extra): New rule.
* sim-main.h: Include bfd.h.
(MIPS_MACH): New macro.
* mips.igen (vr4120, vr5400, vr5500): New models.
(clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
* vr.igen: Replace with new version.
Diffstat (limited to 'sim/mips/mips.igen')
| -rw-r--r-- | sim/mips/mips.igen | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen index 3d4eeb0..fece487 100644 --- a/sim/mips/mips.igen +++ b/sim/mips/mips.igen @@ -55,7 +55,10 @@ // (or which pre-date or use different encodings than the standard // instructions) are (for the most part) in separate .igen files. :model:::vr4100:mips4100: // vr.igen +:model:::vr4120:mips4120: :model:::vr5000:mips5000: +:model:::vr5400:mips5400: +:model:::vr5500:mips5500: :model:::r3900:mips3900: // tx.igen // MIPS Application Specific Extensions (ASEs) @@ -978,6 +981,7 @@ "clo r<RD>, r<RS>" *mips32: *mips64: +*vr5500: { unsigned32 temp = GPR[RS]; unsigned32 i, mask; @@ -1002,6 +1006,7 @@ "clz r<RD>, r<RS>" *mips32: *mips64: +*vr5500: { unsigned32 temp = GPR[RS]; unsigned32 i, mask; @@ -1111,6 +1116,7 @@ 011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO "dclo r<RD>, r<RS>" *mips64: +*vr5500: { unsigned64 temp = GPR[RS]; unsigned32 i; @@ -1134,6 +1140,7 @@ 011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ "dclz r<RD>, r<RS>" *mips64: +*vr5500: { unsigned64 temp = GPR[RS]; unsigned32 i; @@ -2157,6 +2164,7 @@ "madd r<RS>, r<RT>" *mips32: *mips64: +*vr5500: { signed64 temp; check_mult_hilo (SD_, HIHISTORY, LOHISTORY); @@ -2176,6 +2184,7 @@ "maddu r<RS>, r<RT>" *mips32: *mips64: +*vr5500: { unsigned64 temp; check_mult_hilo (SD_, HIHISTORY, LOHISTORY); @@ -2280,6 +2289,7 @@ "msub r<RS>, r<RT>" *mips32: *mips64: +*vr5500: { signed64 temp; check_mult_hilo (SD_, HIHISTORY, LOHISTORY); @@ -2299,6 +2309,7 @@ "msubu r<RS>, r<RT>" *mips32: *mips64: +*vr5500: { unsigned64 temp; check_mult_hilo (SD_, HIHISTORY, LOHISTORY); @@ -2356,6 +2367,7 @@ "mul r<RD>, r<RS>, r<RT>" *mips32: *mips64: +*vr5500: { signed64 prod; if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) |