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| author | Andrew Cagney <cagney@redhat.com> | 1998-04-15 14:04:01 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 1998-04-15 14:04:01 +0000 |
| commit | 74025eeea7d79d807ac403e680876a32b6ea87e3 (patch) | |
| tree | 1dcb9078a9acb1f347fec3cde088b3c7f0784aa1 /sim/mips/mips.igen | |
| parent | ea5d84f5dcbd24e82a7c57cda0de5a3fe3a8e292 (diff) | |
| download | gdb-74025eeea7d79d807ac403e680876a32b6ea87e3.zip gdb-74025eeea7d79d807ac403e680876a32b6ea87e3.tar.gz gdb-74025eeea7d79d807ac403e680876a32b6ea87e3.tar.bz2 | |
Re-fix 32 bit DSRAV instruction.
Fix mips16 BRANCH, unsigned ADD/SUB and SRAV instructions.
Diffstat (limited to 'sim/mips/mips.igen')
| -rw-r--r-- | sim/mips/mips.igen | 21 |
1 files changed, 15 insertions, 6 deletions
diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen index b893e8a..7b4102c 100644 --- a/sim/mips/mips.igen +++ b/sim/mips/mips.igen @@ -1287,7 +1287,7 @@ } -:function:::void:do_srav:int rs, int rt, int rd +:function:::void:do_dsrav:int rs, int rt, int rd { int s = MASKED64 (GPR[rs], 5, 0); TRACE_ALU_INPUT2 (GPR[rt], s); @@ -1313,12 +1313,12 @@ *tx19: // end-sanitize-tx19 { - do_srav (SD_, RS, RT, RD); + do_dsrav (SD_, RS, RT, RD); } 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL -"dsrav r<RD>, r<RT>, <SHIFT>" +"dsrl r<RD>, r<RT>, <SHIFT>" *mipsIII: *mipsIV: *vr5000: @@ -2857,6 +2857,16 @@ } + +:function:::void:do_srav:int rs, int rt, int rd +{ + int s = MASKED (GPR[rs], 4, 0); + signed32 temp = (signed32) GPR[rt] >> s; + TRACE_ALU_INPUT2 (GPR[rt], s); + GPR[rd] = EXTEND32 (temp); + TRACE_ALU_RESULT (GPR[rd]); +} + 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV "srav r<RD>, r<RT>, r<RS>" *mipsI,mipsII,mipsIII,mipsIV: @@ -2875,12 +2885,11 @@ *tx19: // end-sanitize-tx19 { - int s = MASKED (GPR[RS], 4, 0); - signed32 temp = (signed32) GPR[RT] >> s; - GPR[RD] = EXTEND32 (temp); + do_srav (SD_, RS, RT, RD); } + :function:::void:do_srl:int rt, int rd, int shift { unsigned32 temp = (unsigned32) GPR[rt] >> shift; |