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| author | Gavin Romig-Koch <gavin@redhat.com> | 1998-12-12 22:43:54 +0000 |
|---|---|---|
| committer | Gavin Romig-Koch <gavin@redhat.com> | 1998-12-12 22:43:54 +0000 |
| commit | 82aeada70ce252df2878d506625819870cfd1d8b (patch) | |
| tree | 261e2c2c9c44aee8f6a22634a752bdf413fa7743 /sim/mips/mips.igen | |
| parent | b3f1799e8136ff32f31089b7d1bb56194693663c (diff) | |
| download | gdb-82aeada70ce252df2878d506625819870cfd1d8b.zip gdb-82aeada70ce252df2878d506625819870cfd1d8b.tar.gz gdb-82aeada70ce252df2878d506625819870cfd1d8b.tar.bz2 | |
* configure.in (mips64vr4xxx): Enable TARGET_ENABLE_FR.
Set mips_fpu, and mips_fpu_bitsize.
Set sim_gen, and sim_igen_machine.
* configure: Rebuild.
* mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
* sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
Diffstat (limited to 'sim/mips/mips.igen')
| -rw-r--r-- | sim/mips/mips.igen | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen index 21e822e..8c07108 100644 --- a/sim/mips/mips.igen +++ b/sim/mips/mips.igen @@ -4178,7 +4178,7 @@ // BC1T // BC1TL -010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1 +010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a "bc1%s<TF>%s<ND> <OFFSET>" *mipsI,mipsII,mipsIII: *vr4100: @@ -4206,7 +4206,7 @@ } } -010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1 +010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b "bc1%s<TF>%s<ND> <OFFSET>":CC == 0 "bc1%s<TF>%s<ND> <CC>, <OFFSET>" *mipsIV: |