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| author | Andrew Cagney <cagney@redhat.com> | 1998-11-12 06:42:34 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 1998-11-12 06:42:34 +0000 |
| commit | d1cbd70abba43c47cbbbf759e225bd946538325a (patch) | |
| tree | 8f6c98c595892a4a3ed48c0e3c7b5ba29506b06a /sim/mips/interp.c | |
| parent | 93db5513ee4fd5bfd3e556638cc1331d8d0a9533 (diff) | |
| download | gdb-d1cbd70abba43c47cbbbf759e225bd946538325a.zip gdb-d1cbd70abba43c47cbbbf759e225bd946538325a.tar.gz gdb-d1cbd70abba43c47cbbbf759e225bd946538325a.tar.bz2 | |
Add configury for mips-lsi-elf target (32 bit MIPS16).
Fix numerous problems with PENDING_* code.
In old gencode simulator, don't double tick each cycle.
Add BREAK instruction to MIPS16 gencode simulator.
Diffstat (limited to 'sim/mips/interp.c')
| -rw-r--r-- | sim/mips/interp.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/sim/mips/interp.c b/sim/mips/interp.c index ba3d6e5..f2db125 100644 --- a/sim/mips/interp.c +++ b/sim/mips/interp.c @@ -4277,9 +4277,6 @@ sim_engine_run (sd, next_cpu_nr, nr_cpus, siggnal) CANCELDELAYSLOT(); } - if (MIPSISA < 4) - PENDING_TICK(); - #if !defined(FASTSIM) if (sim_events_tickn (sd, pipeline_count)) { |