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| author | Frank Ch. Eigler <fche@redhat.com> | 1998-06-01 16:29:43 +0000 |
|---|---|---|
| committer | Frank Ch. Eigler <fche@redhat.com> | 1998-06-01 16:29:43 +0000 |
| commit | 29b5afe9afd7c259f878bdd9c558afc66edecc7d (patch) | |
| tree | a8b32f17d01772fbf47645c963c39f3f0be86737 /sim/mips/interp.c | |
| parent | fb0ea2b9e1136c295c6357159e8fd809ab5766ba (diff) | |
| download | gdb-29b5afe9afd7c259f878bdd9c558afc66edecc7d.zip gdb-29b5afe9afd7c259f878bdd9c558afc66edecc7d.tar.gz gdb-29b5afe9afd7c259f878bdd9c558afc66edecc7d.tar.bz2 | |
* Small TX39-only patch for ECC.
Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
* interp.c (decode_coproc): For TX39, add stub COP0 register #3,
to allay warnings.
Diffstat (limited to 'sim/mips/interp.c')
| -rw-r--r-- | sim/mips/interp.c | 19 |
1 files changed, 14 insertions, 5 deletions
diff --git a/sim/mips/interp.c b/sim/mips/interp.c index c09bf5a..3bf532a 100644 --- a/sim/mips/interp.c +++ b/sim/mips/interp.c @@ -489,8 +489,10 @@ sim_open (kind, cb, abfd, argv) } /* start-sanitize-tx3904 */ - else if(! strcmp(board, BOARD_JMR3904) || - (! strcmp(board, BOARD_JMR3904_DEBUG))) +#if (WITH_HW) + if (board != NULL + && (strcmp(board, BOARD_JMR3904) == 0 || + strcmp(board, BOARD_JMR3904_DEBUG) == 0)) { /* match VIRTUAL memory layout of JMR-TX3904 board */ @@ -547,6 +549,7 @@ sim_open (kind, cb, abfd, argv) device_init(sd); } +#endif /* end-sanitize-tx3904 */ @@ -1758,7 +1761,7 @@ signal_exception (SIM_DESC sd, address_word cia, int exception,...) { - int vector; + /* int vector; */ #ifdef DEBUG sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia)); @@ -1915,12 +1918,12 @@ signal_exception (SIM_DESC sd, else EPC = cia; /* FIXME: TLB et.al. */ - vector = 0x180; + /* vector = 0x180; */ } else { CAUSE = (exception << 2); - vector = 0x180; + /* vector = 0x180; */ } SR |= status_EXL; /* Store exception code into current exception id variable (used @@ -3350,6 +3353,12 @@ decode_coproc (SIM_DESC sd, /* 10 = EntryHi R4000 VR4100 VR4300 */ /* 11 = Compare R4000 VR4100 VR4300 */ /* 12 = SR R4000 VR4100 VR4300 */ +#ifdef SUBTARGET_R3900 + case 3: + /* ignore */ + break; + /* 3 = Config R3900 */ +#endif /* SUBTARGET_R3900 */ case 12: if (code == 0x00) GPR[rt] = SR; |