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| author | Chris Demetriou <cgd@google.com> | 2002-06-04 22:38:41 +0000 |
|---|---|---|
| committer | Chris Demetriou <cgd@google.com> | 2002-06-04 22:38:41 +0000 |
| commit | ee7254b0cc380b91b93231b21fe5b40247180627 (patch) | |
| tree | 737e8cdaf91250806816c1592a4e1748aa0e08e2 /sim/mips/interp.c | |
| parent | d3eb724f8198916e9fdd3805811f467167149f62 (diff) | |
| download | gdb-ee7254b0cc380b91b93231b21fe5b40247180627.zip gdb-ee7254b0cc380b91b93231b21fe5b40247180627.tar.gz gdb-ee7254b0cc380b91b93231b21fe5b40247180627.tar.bz2 | |
2002-06-04 Chris Demetriou <cgd@broadcom.com>
* sim-main.h (FGRIDX): Remove, replace all uses with...
(FGR_BASE): New macro.
(FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
(_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
(NR_FGR, FGR): Likewise.
* interp.c: Replace all uses of FGRIDX with FGR_BASE.
* mips.igen: Likewise.
Diffstat (limited to 'sim/mips/interp.c')
| -rw-r--r-- | sim/mips/interp.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/sim/mips/interp.c b/sim/mips/interp.c index 35016e3..8cc6318 100644 --- a/sim/mips/interp.c +++ b/sim/mips/interp.c @@ -575,7 +575,7 @@ sim_open (kind, cb, abfd, argv) { if (rn < 32) cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE; - else if ((rn >= FGRIDX) && (rn < (FGRIDX + NR_FGR))) + else if ((rn >= FGR_BASE) && (rn < (FGR_BASE + NR_FGR))) cpu->register_widths[rn] = WITH_TARGET_FLOATING_POINT_BITSIZE; else if ((rn >= 33) && (rn <= 37)) cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE; @@ -849,26 +849,26 @@ sim_store_register (sd,rn,memory,length) - if (rn >= FGRIDX && rn < FGRIDX + NR_FGR) + if (rn >= FGR_BASE && rn < FGR_BASE + NR_FGR) { - cpu->fpr_state[rn - FGRIDX] = fmt_uninterpreted; + cpu->fpr_state[rn - FGR_BASE] = fmt_uninterpreted; if (cpu->register_widths[rn] == 32) { if (length == 8) { - cpu->fgr[rn - FGRIDX] = + cpu->fgr[rn - FGR_BASE] = (unsigned32) T2H_8 (*(unsigned64*)memory); return 8; } else { - cpu->fgr[rn - FGRIDX] = T2H_4 (*(unsigned32*)memory); + cpu->fgr[rn - FGR_BASE] = T2H_4 (*(unsigned32*)memory); return 4; } } else { - cpu->fgr[rn - FGRIDX] = T2H_8 (*(unsigned64*)memory); + cpu->fgr[rn - FGR_BASE] = T2H_8 (*(unsigned64*)memory); return 8; } } @@ -921,25 +921,25 @@ sim_fetch_register (sd,rn,memory,length) /* Any floating point register */ - if (rn >= FGRIDX && rn < FGRIDX + NR_FGR) + if (rn >= FGR_BASE && rn < FGR_BASE + NR_FGR) { if (cpu->register_widths[rn] == 32) { if (length == 8) { *(unsigned64*)memory = - H2T_8 ((unsigned32) (cpu->fgr[rn - FGRIDX])); + H2T_8 ((unsigned32) (cpu->fgr[rn - FGR_BASE])); return 8; } else { - *(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGRIDX]); + *(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGR_BASE]); return 4; } } else { - *(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGRIDX]); + *(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGR_BASE]); return 8; } } |