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| author | Andrew Cagney <cagney@redhat.com> | 1998-04-21 01:17:58 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 1998-04-21 01:17:58 +0000 |
| commit | 421cbaae983d05c663270534b65e4fe9dc415dae (patch) | |
| tree | 42d92712f3f57b0b165aeeabc7d82d4d061ac6ff /sim/mips/interp.c | |
| parent | 98f5dae13b105229af113f761ffe8b4dbf3f428d (diff) | |
| download | gdb-421cbaae983d05c663270534b65e4fe9dc415dae.zip gdb-421cbaae983d05c663270534b65e4fe9dc415dae.tar.gz gdb-421cbaae983d05c663270534b65e4fe9dc415dae.tar.bz2 | |
For new IGEN simulators, rewrite checks validating correct use of the
HI/LO registers. For old gencode simulator, delete all checks.
Diffstat (limited to 'sim/mips/interp.c')
| -rw-r--r-- | sim/mips/interp.c | 22 |
1 files changed, 4 insertions, 18 deletions
diff --git a/sim/mips/interp.c b/sim/mips/interp.c index 8f45da9..612b73b 100644 --- a/sim/mips/interp.c +++ b/sim/mips/interp.c @@ -3300,8 +3300,8 @@ decode_coproc (SIM_DESC sd, read_vu_vec_reg(&(vu0_device.regs), id, 1, A4_16(& xyzw, 2)); read_vu_vec_reg(&(vu0_device.regs), id, 2, A4_16(& xyzw, 1)); read_vu_vec_reg(&(vu0_device.regs), id, 3, A4_16(& xyzw, 0)); - xyzw = T2H_16(xyzw); - memcpy(& GPR[rt], & xyzw, sizeof(xyzw)); + GPR[rt] = T2H_8(* A8_16(& xyzw, 1)); + GPR1[rt] = T2H_8(* A8_16(& xyzw, 0)); } else /* CFC2 */ { @@ -3334,8 +3334,8 @@ decode_coproc (SIM_DESC sd, /* perform VU register address */ if(i_25_21 == 0x05) /* QMTC2 */ { - unsigned_16 xyzw; - memcpy(& xyzw, & GPR[rt], sizeof(xyzw)); + unsigned_16 xyzw = U16_8(GPR1[rt], GPR[rt]); + xyzw = H2T_16(xyzw); /* one word at a time, argh! */ write_vu_vec_reg(&(vu0_device.regs), id, 0, A4_16(& xyzw, 3)); @@ -3624,20 +3624,6 @@ sim_engine_run (sd, next_cpu_nr, nr_cpus, siggnal) #error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU" #endif -#if defined(WARN_LOHI) - /* Decrement the HI/LO validity ticks */ - if (HIACCESS > 0) - HIACCESS--; - if (LOACCESS > 0) - LOACCESS--; - /* start-sanitize-r5900 */ - if (HI1ACCESS > 0) - HI1ACCESS--; - if (LO1ACCESS > 0) - LO1ACCESS--; - /* end-sanitize-r5900 */ -#endif /* WARN_LOHI */ - /* For certain MIPS architectures, GPR[0] is hardwired to zero. We should check for it being changed. It is better doing it here, than within the simulator, since it will help keep the simulator |