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| author | Stan Shebs <shebs@codesourcery.com> | 1999-04-26 18:34:20 +0000 |
|---|---|---|
| committer | Stan Shebs <shebs@codesourcery.com> | 1999-04-26 18:34:20 +0000 |
| commit | 7a292a7adf506b866905b06b3024c0fd411c4583 (patch) | |
| tree | 5b208bb48269b8a82d5c3a5f19c87b45a62a22f4 /sim/mips/interp.c | |
| parent | 1996fae84682e8ddd146215dd2959ad1ec924c09 (diff) | |
| download | gdb-7a292a7adf506b866905b06b3024c0fd411c4583.zip gdb-7a292a7adf506b866905b06b3024c0fd411c4583.tar.gz gdb-7a292a7adf506b866905b06b3024c0fd411c4583.tar.bz2 | |
import gdb-19990422 snapshot
Diffstat (limited to 'sim/mips/interp.c')
| -rw-r--r-- | sim/mips/interp.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/sim/mips/interp.c b/sim/mips/interp.c index 75bc54b..a2ed20f 100644 --- a/sim/mips/interp.c +++ b/sim/mips/interp.c @@ -750,6 +750,7 @@ sim_store_register (sd,rn,memory,length) if (rn >= FGRIDX && rn < FGRIDX + NR_FGR) { + cpu->fpr_state[rn - FGRIDX] = fmt_uninterpreted; if (cpu->register_widths[rn] == 32) { cpu->fgr[rn - FGRIDX] = T2H_4 (*(unsigned32*)memory); |