* Updates to tx3904 peripheral simulations for ECC.

Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
	* dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
 	register upon non-zero interrupt event level, clear upon zero
 	event value.
	* dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
	by passing zero event value.
	(*_io_{read,write}_buffer): Endianness fixes.
	* dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
	(deliver_*_tick): Reduce sim event interval to 75% of count interval.
	* interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
	serial I/O and timer module at base address 0xFFFF0000.

1 files changed, 15 insertions, 16 deletions

diff --git a/sim/mips/dv-tx3904tmr.c b/sim/mips/dv-tx3904tmr.c
index b101421..b27e9b0 100644
--- a/sim/mips/dv-tx3904tmr.c
+++ b/sim/mips/dv-tx3904tmr.c
@@ -324,7 +324,7 @@ tx3904tmr_io_read_buffer (struct hw *me,
     {
       address_word address = base + byte;
       int reg_number = (address - controller->base_address) / 4;
-      int reg_offset = (address - controller->base_address) % 4;
+      int reg_offset = 3 - (address - controller->base_address) % 4;
       unsigned_4 register_value; /* in target byte order */
 
       /* fill in entire register_value word */
@@ -367,7 +367,7 @@ tx3904tmr_io_write_buffer (struct hw *me,
       address_word address = base + byte;
       unsigned_1 write_byte = ((char*) source)[byte];
       int reg_number = (address - controller->base_address) / 4;
-      int reg_offset = (address - controller->base_address) % 4;
+      int reg_offset = 3 - (address - controller->base_address) % 4;
       unsigned_4* register_ptr;
       unsigned_4 register_value;
 
@@ -384,9 +384,8 @@ tx3904tmr_io_write_buffer (struct hw *me,
 	      if(GET_TCR_TCE(controller) == 0 &&
 		 GET_TCR_CRE(controller) == 1)
 		controller->trr = 0;
-
 	    }
-	  HW_TRACE ((me, "tcr: %08lx", (long) controller->tcr));
+	  /* HW_TRACE ((me, "tcr: %08lx", (long) controller->tcr)); */
 	  break;
 
 	case ITMR_REG:
@@ -398,7 +397,7 @@ tx3904tmr_io_write_buffer (struct hw *me,
 	    {
 	      SET_ITMR_TZCE(controller, write_byte & 0x01);
 	    }
-	  HW_TRACE ((me, "itmr: %08lx", (long) controller->itmr));
+	  /* HW_TRACE ((me, "itmr: %08lx", (long) controller->itmr)); */
 	  break;
 
 	case CCDR_REG:
@@ -406,7 +405,7 @@ tx3904tmr_io_write_buffer (struct hw *me,
 	    {
 	      controller->ccdr = write_byte & 0x07;
 	    }
-	  HW_TRACE ((me, "ccdr: %08lx", (long) controller->ccdr));
+	  /* HW_TRACE ((me, "ccdr: %08lx", (long) controller->ccdr)); */
 	  break;
 
 	case PMGR_REG:
@@ -419,7 +418,7 @@ tx3904tmr_io_write_buffer (struct hw *me,
 	    {
 	      SET_PMGR_FFI(controller, write_byte & 0x01);
 	    }
-	  HW_TRACE ((me, "pmgr: %08lx", (long) controller->pmgr));
+	  /* HW_TRACE ((me, "pmgr: %08lx", (long) controller->pmgr)); */
 	  break;
 
 	case WTMR_REG:
@@ -432,7 +431,7 @@ tx3904tmr_io_write_buffer (struct hw *me,
 	      SET_WTMR_WDIS(controller, write_byte & 0x80);
 	      SET_WTMR_TWC(controller, write_byte & 0x01);
 	    }
-	  HW_TRACE ((me, "wtmr: %08lx", (long) controller->wtmr));
+	  /* HW_TRACE ((me, "wtmr: %08lx", (long) controller->wtmr)); */
 	  break;
 
 	case TISR_REG:
@@ -450,23 +449,23 @@ tx3904tmr_io_write_buffer (struct hw *me,
 	      /* clear interrupt status register */
 	      controller->tisr = 0;
 	    }
-	  HW_TRACE ((me, "tisr: %08lx", (long) controller->tisr));
+	  /* HW_TRACE ((me, "tisr: %08lx", (long) controller->tisr)); */
 	  break;
 
 	case CPRA_REG:
 	  if(reg_offset < 3) /* first, second, or third byte */
 	    {
-	      MBLIT32(controller->cpra, (reg_offset*8), (reg_offset*8+7), write_byte);
+	      MBLIT32(controller->cpra, (reg_offset*8)+7, (reg_offset*8), write_byte);
 	    }
-	  HW_TRACE ((me, "cpra: %08lx", (long) controller->cpra));
+	  /* HW_TRACE ((me, "cpra: %08lx", (long) controller->cpra)); */
 	  break;
 
 	case CPRB_REG:
 	  if(reg_offset < 3) /* first, second, or third byte */
 	    {
-	      MBLIT32(controller->cprb, (reg_offset*8), (reg_offset*8+7), write_byte);
+	      MBLIT32(controller->cprb, (reg_offset*8)+7, (reg_offset*8), write_byte);
 	    }
-	  HW_TRACE ((me, "cprb: %08lx", (long) controller->cprb));
+	  /* HW_TRACE ((me, "cprb: %08lx", (long) controller->cprb)); */
 	  break;
 
 	default: 
@@ -667,9 +666,9 @@ deliver_tx3904tmr_tick (struct hw *me,
     } /* end quotient loop */
 
   /* Reschedule a timer event in near future, so we can increment the
-     counter again.  Set the event about 50% of divisor time away, so
-     we will experience roughly two events per counter increment. */
-  hw_event_queue_schedule(me, divisor/2, deliver_tx3904tmr_tick, NULL);
+     counter again.  Set the event about 75% of divisor time away, so
+     we will experience roughly 1.3 events per counter increment. */
+  hw_event_queue_schedule(me, divisor*3/4, deliver_tx3904tmr_tick, NULL);
 }