* Updates to tx3904 peripheral simulations for ECC.

Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
	* dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
 	register upon non-zero interrupt event level, clear upon zero
 	event value.
	* dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
	by passing zero event value.
	(*_io_{read,write}_buffer): Endianness fixes.
	* dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
	(deliver_*_tick): Reduce sim event interval to 75% of count interval.
	* interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
	serial I/O and timer module at base address 0xFFFF0000.

1 files changed, 26 insertions, 18 deletions

diff --git a/sim/mips/dv-tx3904cpu.c b/sim/mips/dv-tx3904cpu.c
index d043253..a040d4c 100644
--- a/sim/mips/dv-tx3904cpu.c
+++ b/sim/mips/dv-tx3904cpu.c
@@ -1,4 +1,4 @@
-/*  This file is part of the program GDB, the GU debugger.
+/*  This file is part of the program GDB, the GNU debugger.
     
     Copyright (C) 1998 Free Software Foundation, Inc.
     Contributed by Cygnus Solutions.
@@ -163,24 +163,28 @@ deliver_tx3904cpu_interrupt (struct hw *me,
 		 controller->pending_level,
 		 (long) CIA_GET (cpu), (long) SR));
 
-      /* Don't overwrite the CAUSE field since we have no good place to clear
-	 it again.  The specs allow it to be zero by the time the interrupt
-	 handler is invoked. */
-      /* CAUSE &= ~ (cause_IP_mask << cause_IP_shift);
-	 CAUSE |= (controller->pending_level & cause_IP_mask) << cause_IP_shift; */
+      /* Clear CAUSE register.  It may stay this way if the interrupt
+	 was cleared with a negative pending_level. */
+      CAUSE &= ~ (cause_IP_mask << cause_IP_shift);
 
-      /* check for enabled / unmasked interrupts */
-      if((SR & status_IEc) &&
-	 (controller->pending_level & ((SR >> status_IM_shift) & status_IM_mask)))
+      if(controller->pending_level > 0) /* interrupt set */
 	{
-	  controller->pending_level = 0;
-	  SignalExceptionInterrupt();
-	}
-      else
-	{
-	  /* reschedule soon */
-	  hw_event_queue_schedule (me, 1, deliver_tx3904cpu_interrupt, NULL);
-	}
+	  /* set hardware-interrupt subfields of CAUSE register */
+	  CAUSE |= (controller->pending_level & cause_IP_mask) << cause_IP_shift;
+
+	  /* check for enabled / unmasked interrupts */
+	  if((SR & status_IEc) &&
+	     (controller->pending_level & ((SR >> status_IM_shift) & status_IM_mask)))
+	    {
+	      controller->pending_level = 0;
+	      SignalExceptionInterrupt();
+	    }
+	  else
+	    {
+	      /* reschedule soon */
+	      hw_event_queue_schedule (me, 1, deliver_tx3904cpu_interrupt, NULL);
+	    }
+	} /* interrupt set */
     }
 #undef CPU cpu
 #undef SD current_state
@@ -209,7 +213,11 @@ tx3904cpu_port_event (struct hw *me,
       break;
       
     case LEVEL_PORT:
-      controller->pending_level |= level; /* accumulate bits until they are cleared */
+      /* level == 0 means that the interrupt was cleared */
+      if(level == 0)
+	controller->pending_level = -1; /* signal end of interrupt */
+      else
+	controller->pending_level = level;
       HW_TRACE ((me, "port-in level=%d", level));
       break;