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| author | Mike Frysinger <vapier@gentoo.org> | 2015-04-16 02:11:12 -0400 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2015-04-17 02:44:30 -0400 |
| commit | 034685f9ce92cf6dfb6656745365b6a5904a8e84 (patch) | |
| tree | c4b591263048d0a9d89af68c9abd8e69786ed2f7 /sim/mips/dv-tx3904cpu.c | |
| parent | 27b97b40bca216097d16d53fa9408a70cd281479 (diff) | |
| download | gdb-034685f9ce92cf6dfb6656745365b6a5904a8e84.zip gdb-034685f9ce92cf6dfb6656745365b6a5904a8e84.tar.gz gdb-034685f9ce92cf6dfb6656745365b6a5904a8e84.tar.bz2 | |
sim: replace CIA_{GET,SET} with CPU_PC_{GET,SET}
The CIA_{GET,SET} macros serve the same function as CPU_PC_{GET,SET}
except the latter adds a layer of indirection via the sim state. This
lets models set up different functions at runtime and doesn't reach so
directly into the arch-specific cpu state.
It also doesn't make sense to have two sets of macros that do exactly
the same thing, so lets standardize on the one that gets us more.
Diffstat (limited to 'sim/mips/dv-tx3904cpu.c')
| -rw-r--r-- | sim/mips/dv-tx3904cpu.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/sim/mips/dv-tx3904cpu.c b/sim/mips/dv-tx3904cpu.c index 56b3386..cf9399a 100644 --- a/sim/mips/dv-tx3904cpu.c +++ b/sim/mips/dv-tx3904cpu.c @@ -141,7 +141,7 @@ deliver_tx3904cpu_interrupt (struct hw *me, struct tx3904cpu *controller = hw_data (me); SIM_DESC sd = hw_system (me); sim_cpu *cpu = STATE_CPU (sd, 0); /* NB: fix CPU 0. */ - address_word cia = CIA_GET (cpu); + address_word cia = CPU_PC_GET (cpu); #define CPU cpu #define SD current_state @@ -149,20 +149,20 @@ deliver_tx3904cpu_interrupt (struct hw *me, if (controller->pending_reset) { controller->pending_reset = 0; - HW_TRACE ((me, "reset pc=0x%08lx", (long) CIA_GET (cpu))); + HW_TRACE ((me, "reset pc=0x%08lx", (long) CPU_PC_GET (cpu))); SignalExceptionNMIReset(); } else if (controller->pending_nmi) { controller->pending_nmi = 0; - HW_TRACE ((me, "nmi pc=0x%08lx", (long) CIA_GET (cpu))); + HW_TRACE ((me, "nmi pc=0x%08lx", (long) CPU_PC_GET (cpu))); SignalExceptionNMIReset(); } else if (controller->pending_level) { HW_TRACE ((me, "interrupt level=%d pc=0x%08lx sr=0x%08lx", controller->pending_level, - (long) CIA_GET (cpu), (long) SR)); + (long) CPU_PC_GET (cpu), (long) SR)); /* Clear CAUSE register. It may stay this way if the interrupt was cleared with a negative pending_level. */ |