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authorChris Demetriou <cgd@google.com>2002-06-07 22:55:49 +0000
committerChris Demetriou <cgd@google.com>2002-06-07 22:55:49 +0000
commit52714ff9eea8dbf085c0f7bc1191d4eafc2936a2 (patch)
tree44a16a24538404b36fdb12708e291a43b5790fb3 /sim/mips/cp1.h
parent85b5171940bef9c7bd14141d94805df4c8a8eb59 (diff)
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2002-06-07 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com> * cp1.c: Fix more comment spelling and formatting. (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value. (denorm_mode): New function. (fpu_unary, fpu_binary): Round results after operation, collect status from rounding operations, and update the FCSR. (convert): Collect status from integer conversions and rounding operations, and update the FCSR. Adjust NaN values that result from conversions. Convert to use sim_io_eprintf rather than fprintf, and remove some debugging code. * cp1.h (fenr_FS): New define.
Diffstat (limited to 'sim/mips/cp1.h')
-rw-r--r--sim/mips/cp1.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/sim/mips/cp1.h b/sim/mips/cp1.h
index 90919e3..24901d8 100644
--- a/sim/mips/cp1.h
+++ b/sim/mips/cp1.h
@@ -40,6 +40,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#define fcsr_RM_mask (0x00000003)
#define fcsr_RM_shift (0)
+#define fenr_FS (0x00000004)
/* Macros to update and retrieve the FCSR condition-code bits. This
is complicated by the fact that there is a hole in the index range