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| author | Steve Ellcey <sje@cup.hp.com> | 2012-09-24 18:03:18 +0000 |
|---|---|---|
| committer | Steve Ellcey <sje@cup.hp.com> | 2012-09-24 18:03:18 +0000 |
| commit | cc2202431b7cabda9042d264b920f9156bfc2f60 (patch) | |
| tree | e8c880db8ec38c88a86ce09aba8c988177317da3 /sim/mips/configure | |
| parent | b4aa388a2099d88f1d521a79bdfabb0501a03f1a (diff) | |
| download | gdb-cc2202431b7cabda9042d264b920f9156bfc2f60.zip gdb-cc2202431b7cabda9042d264b920f9156bfc2f60.tar.gz gdb-cc2202431b7cabda9042d264b920f9156bfc2f60.tar.bz2 | |
2012-09-24 Steve Ellcey <sellcey@mips.com>
* mips/basic.exp: Add mips*-mti-elf* target.
* configure.ac: Add mips*-mti-elf* target.
* configure: Regenerate.
Diffstat (limited to 'sim/mips/configure')
| -rwxr-xr-x | sim/mips/configure | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/sim/mips/configure b/sim/mips/configure index b0b6a63..d4db996 100755 --- a/sim/mips/configure +++ b/sim/mips/configure @@ -5312,6 +5312,7 @@ case "${target}" in mips64vr*-*-*) SIM_SUBTARGET="-DTARGET_ENABLE_FR=1" ;; mips*tx39*) SIM_SUBTARGET="-DSUBTARGET_R3900=1";; mips*-sde-elf*) SIM_SUBTARGET="-DTARGET_ENABLE_FR=1";; + mips*-mti-elf*) SIM_SUBTARGET="-DTARGET_ENABLE_FR=1";; mipsisa32*-*-*) SIM_SUBTARGET="-DTARGET_ENABLE_FR=1";; mipsisa64*-*-*) SIM_SUBTARGET="-DTARGET_ENABLE_FR=1";; *) SIM_SUBTARGET="";; @@ -5389,6 +5390,7 @@ fi mips_addr_bitsize= case "${target}" in mips*-sde-elf*) mips_bitsize=64 ; mips_msb=63 ;; + mips*-mti-elf*) mips_bitsize=64 ; mips_msb=63 ;; mips64*-*-*) mips_bitsize=64 ; mips_msb=63 ;; mips16*-*-*) mips_bitsize=64 ; mips_msb=63 ;; mipsisa32*-*-*) mips_bitsize=32 ; mips_msb=31 ;; @@ -5466,6 +5468,7 @@ mips_fpu_bitsize= case "${target}" in mips*tx39*) mips_fpu=HARD_FLOATING_POINT ; mips_fpu_bitsize=32 ;; mips*-sde-elf*) mips_fpu=HARD_FLOATING_POINT ; mips_fpu_bitsize=64 ;; + mips*-mti-elf*) mips_fpu=HARD_FLOATING_POINT ; mips_fpu_bitsize=64 ;; mips64*-*-*) mips_fpu=HARD_FLOATING_POINT ;; mips16*-*-*) mips_fpu=HARD_FLOATING_POINT ;; mipsisa32*-*-*) mips_fpu=HARD_FLOATING_POINT ; mips_fpu_bitsize=64 ;; @@ -5571,7 +5574,8 @@ case "${target}" in vr5500:mipsIV,vr5500:32,64,f:mips5500" sim_multi_default=mips5000 ;; - mips*-sde-elf*) sim_gen=M16 + mips*-sde-elf* | mips*-mti-elf*) + sim_gen=M16 sim_igen_machine="-M mips64r2,mips3d,mips16,mips16e,mdmx,dsp,dsp2,smartmips" sim_m16_machine="-M mips16,mips16e,mips64r2" sim_igen_filter="32,64,f" |