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authorGavin Romig-Koch <gavin@redhat.com>1998-12-12 22:43:54 +0000
committerGavin Romig-Koch <gavin@redhat.com>1998-12-12 22:43:54 +0000
commit82aeada70ce252df2878d506625819870cfd1d8b (patch)
tree261e2c2c9c44aee8f6a22634a752bdf413fa7743 /sim/mips/configure.in
parentb3f1799e8136ff32f31089b7d1bb56194693663c (diff)
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* configure.in (mips64vr4xxx): Enable TARGET_ENABLE_FR.
Set mips_fpu, and mips_fpu_bitsize. Set sim_gen, and sim_igen_machine. * configure: Rebuild. * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts. * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
Diffstat (limited to 'sim/mips/configure.in')
-rw-r--r--sim/mips/configure.in11
1 files changed, 11 insertions, 0 deletions
diff --git a/sim/mips/configure.in b/sim/mips/configure.in
index e12f922..2cb577f 100644
--- a/sim/mips/configure.in
+++ b/sim/mips/configure.in
@@ -18,6 +18,9 @@ SIM_AC_OPTION_WARNINGS
# in question.
#
case "${target}" in
+# start-sanitize-vr4xxx
+ mips64vr4xxx-*-*) SIM_SUBTARGET="-DTARGET_ENABLE_FR=1" ;;
+# end-sanitize-vr4xxx
# start-sanitize-tx19
mips*tx19*) SIM_SUBTARGET="-DSUBTARGET_R3900=1";;
# end-sanitize-tx19
@@ -85,6 +88,9 @@ case "${target}" in
mips*tx39*) mips_fpu=HARD_FLOATING_POINT
mips_fpu_bitsize=32
;;
+# start-sanitize-vr4xxx
+ mips64vr4xxx-*-*) mips_fpu=HARD_FLOATING_POINT ; mips_fpu_bitsize=64 ;;
+# end-sanitize-vr4xxx
# start-sanitize-r5900
mips64r59*-*-*) mips_fpu=HARD_FLOATING_POINT ; mips_fpu_bitsize=32 ;;
# end-sanitize-r5900
@@ -161,6 +167,11 @@ case "${target}" in
sim_igen_machine="-M vr5000,vr5400 -G gen-multi-sim=vr5000"
;;
# end-sanitize-cygnus
+# start-sanitize-vr4xxx
+ mips64vr4xxx-*-*) sim_gen=IGEN
+ sim_igen_machine="-M mipsIV,vr4100 -G gen-multi-sim=mipsIV"
+ ;;
+# end-sanitize-vr4xxx
mips64vr41*) sim_gen=M16
sim_igen_machine="-M vr4100"
sim_m16_machine="-M vr4100"