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authorAndrew Cagney <cagney@redhat.com>1997-11-14 08:27:38 +0000
committerAndrew Cagney <cagney@redhat.com>1997-11-14 08:27:38 +0000
commitf23e93dab0704098167aa45ef45243cc8df2fa42 (patch)
treed3f32386d00539be4d76e78d4292258fb35eb616 /sim/mips/configure.in
parent15ddb4c9adfa250e06f79d6d465ccdb2f50be49b (diff)
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* mips.igen: Tag vr5000 instructions.
(ANDI): Was missing mipsIV model, fix assembler syntax. (do_c_cond_fmt): New function. (C.cond.fmt): Handle mips I-III which do not support CC field separatly. (bc1): Handle mips IV which do not have a delaed FCC separatly. (SDR): Mask paddr when BigEndianMem, not the converse as specified in IV3.2 spec. (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle vr5000 which saves LO in a GPR separatly. * configure.in (enable-sim-igen): For vr5000, select vr5000 specific instructions. * configure: Re-generate.
Diffstat (limited to 'sim/mips/configure.in')
-rw-r--r--sim/mips/configure.in4
1 files changed, 4 insertions, 0 deletions
diff --git a/sim/mips/configure.in b/sim/mips/configure.in
index 2df6fcc..1949aed 100644
--- a/sim/mips/configure.in
+++ b/sim/mips/configure.in
@@ -121,8 +121,12 @@ case "${target}" in
mips64vr54*-*-*) sim_default_gen=IGEN
sim_use_gen=IGEN
sim_igen_machine="vr5400"
+ #sim_igen_machine="vr5000,vr5400 -G gen-muli-sim"
;;
# end-sanitize-vr5400
+ mips64vr5*-*-*) sim_default_gen=IGEN
+ sim_igen_machine="vr5000"
+ ;;
mips16*-*-*) sim_default_gen=M16
;;
mips32*-*-*) sim_default_gen=IGEN