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| author | Chao-ying Fu <fu@mips.com> | 2005-12-14 23:07:56 +0000 |
|---|---|---|
| committer | Chao-ying Fu <fu@mips.com> | 2005-12-14 23:07:56 +0000 |
| commit | 40a5538e9498da85e4df900c7f4e19bcf6f98760 (patch) | |
| tree | 31d390e51bb74f9599afb9178984dda056ac9967 /sim/mips/configure.ac | |
| parent | dcf6ef0cc3332e75ceadd8f08bf88ddee09178f7 (diff) | |
| download | gdb-40a5538e9498da85e4df900c7f4e19bcf6f98760.zip gdb-40a5538e9498da85e4df900c7f4e19bcf6f98760.tar.gz gdb-40a5538e9498da85e4df900c7f4e19bcf6f98760.tar.bz2 | |
* Makefile.in (SIM_OBJS): Add dsp.o.
(dsp.o): New dependency.
(IGEN_INCLUDE): Add dsp.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
mipsisa64*-*-*): Add dsp to sim_igen_machine.
* configure: Regenerate.
* mips.igen: Add dsp model and include dsp.igen.
(MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
because these instructions are extended in DSP ASE.
* sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
adding 6 DSP accumulator registers and 1 DSP control register.
(AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
DSPCR_CCOND_SMASK): New define.
(DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
* dsp.c, dsp.igen: New files for MIPS DSP ASE.
Diffstat (limited to 'sim/mips/configure.ac')
| -rw-r--r-- | sim/mips/configure.ac | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/sim/mips/configure.ac b/sim/mips/configure.ac index 3128f9f..f81abbb 100644 --- a/sim/mips/configure.ac +++ b/sim/mips/configure.ac @@ -146,19 +146,19 @@ case "${target}" in sim_m16_filter="16" ;; mipsisa32r2*-*-*) sim_gen=M16 - sim_igen_machine="-M mips32r2,mips16,mips16e" + sim_igen_machine="-M mips32r2,mips16,mips16e,dsp" sim_m16_machine="-M mips16,mips16e,mips32r2" sim_igen_filter="32,f" sim_mach_default="mipsisa32r2" ;; mipsisa32*-*-*) sim_gen=M16 - sim_igen_machine="-M mips32,mips16,mips16e" + sim_igen_machine="-M mips32,mips16,mips16e,dsp" sim_m16_machine="-M mips16,mips16e,mips32" sim_igen_filter="32,f" sim_mach_default="mipsisa32" ;; mipsisa64r2*-*-*) sim_gen=M16 - sim_igen_machine="-M mips64r2,mips3d,mips16,mips16e" + sim_igen_machine="-M mips64r2,mips3d,mips16,mips16e,dsp" sim_m16_machine="-M mips16,mips16e,mips64r2" sim_igen_filter="32,64,f" sim_mach_default="mipsisa64r2" @@ -169,7 +169,7 @@ case "${target}" in sim_mach_default="mips_sb1" ;; mipsisa64*-*-*) sim_gen=M16 - sim_igen_machine="-M mips64,mips3d,mips16,mips16e" + sim_igen_machine="-M mips64,mips3d,mips16,mips16e,dsp" sim_m16_machine="-M mips16,mips16e,mips64" sim_igen_filter="32,64,f" sim_mach_default="mipsisa64" |