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| author | Andrew Cagney <cagney@redhat.com> | 1997-11-06 09:16:16 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 1997-11-06 09:16:16 +0000 |
| commit | 7ce8b9178c183326040745390bd88aa5ac9faf5a (patch) | |
| tree | f446e986548273b66fbf002328c7c21477a5f8bb /sim/mips/Makefile.in | |
| parent | 864519b9fdc3e1a14cbff8af20d7055f617233cd (diff) | |
| download | gdb-7ce8b9178c183326040745390bd88aa5ac9faf5a.zip gdb-7ce8b9178c183326040745390bd88aa5ac9faf5a.tar.gz gdb-7ce8b9178c183326040745390bd88aa5ac9faf5a.tar.bz2 | |
IGEN likes to cache the current instruction address (CIA). Change the
MIPS simulator so that correctly writes the value of CIA back int PC
(the global previously used) when the simulation halts.
Fix implementation of DELAY_SLOT and NULLIFY_NEXT_INSTRUCTION macros.
Diffstat (limited to 'sim/mips/Makefile.in')
| -rw-r--r-- | sim/mips/Makefile.in | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/sim/mips/Makefile.in b/sim/mips/Makefile.in index c8e42c0..608486a 100644 --- a/sim/mips/Makefile.in +++ b/sim/mips/Makefile.in @@ -180,6 +180,12 @@ tmp-igen: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE) $(srcdir)/../../move-if-change tmp-irun.c irun.c touch tmp-igen +semantics.o: sim-main.h $(SIM_EXTRA_DEPS) +engine.o: sim-main.h $(SIM_EXTRA_DEPS) +support.o: sim-main.h $(SIM_EXTRA_DEPS) +idecode.o: sim-main.h $(SIM_EXTRA_DEPS) +itable.o: sim-main.h $(SIM_EXTRA_DEPS) + SIM_M16_ALL = tmp-igen $(SIM_M16_ALL) |