[PATCH] Add micromips support to the MIPS simulator

2015-09-25  Andrew Bennett  <andrew.bennett@imgtec.com>
 	      Ali Lown  <ali.lown@imgtec.com>

	sim/common/
	* sim-bits.h (EXTEND6): New macro.
	(EXTEND12): New macro.
	(EXTEND25): New macro.

	sim/mips/
	* Makefile.in (tmp-micromips): New rule.
	(tmp-mach-multi): Add support for micromips.
	* configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
	that works for both mips64 and micromips64.
	(mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
	micromips32.
	Add build support for micromips.
	* dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
	do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
	do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
	do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
	do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
	do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
	do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
	do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
	Refactored instruction code to use these functions.
	* dsp2.igen: Refactored instruction code to use the new functions.
	* interp.c (decode_coproc): Refactored to work with any instruction
	encoding.
	(isa_mode): New variable
	(RSVD_INSTRUCTION): Changed to 0x00000039.
	* m16.igen (BREAK16): Refactored instruction to use do_break16.
	(JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
	* micromips.dc: New file.
	* micromips.igen: New file.
	* micromips16.dc: New file.
	* micromipsdsp.igen: New file.
	* micromipsrun.c: New file.
	* mips.igen (do_swc1): Changed to work with any instruction encoding.
	(do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
	do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo
	do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu
	do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu
	do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub
	do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo
	do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc, do_scd
	do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu, do_tgeu, do_tlt
	do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt, do_add_fmt
	do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1, do_cvt_d_fmt
	do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl, do_cvt_s_pu
	do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt, do_luxc1_32
	do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b, do_mov_fmt, do_movtf
	do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt, do_mtc1b, do_mul_fmt
	do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps, do_plu_ps, do_pul_ps
	do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt, do_prefx, do_sdc1
	do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt, do_swc1, do_swxc1
	do_trunc_fmt): New functions, refactored from existing instructions.
	Refactored instruction code to use these functions.
	(RSVD): Changed to use new reserved instruction.
	(loadstore_ea, not_word_value, unpredictable, check_mt_hilo, check_mf_hilo,
	check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32, do_sdc1, do_suxc1_32,
	check_fmt_p, check_fpu, do_load_double, do_store_double):  Added micromips32
	and micromips64 models.
	Added include for micromips.igen and micromipsdsp.igen
	Add micromips32 and micromips64 models.
	(DecodeCoproc): Updated to use new macro definition.
	* mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
	do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
	do_seb, do_seh do_rdhwr, do_wsbh): New functions.
	Refactored instruction code to use these functions.
	* sim-main.h (CP0_operation): New enum.
	(DecodeCoproc): Updated macro.
	(IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
	MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16, MICROMIPS_DELAYSLOT_SIZE_32,
	ISA_MODE_MIPS32 and ISA_MODE_MICROMIPS): New defines.
	(sim_state): Add isa_mode field.

	sim/testsuite/sim/mips/
       * basic.exp (run_micromips_test, run_sim_tests): New functions
	Add support for micromips tests.
	* hilo-hazard-4.s: New file.
	* testutils.inc (_dowrite): Changed reserved instruction encoding.
	(writemsg): Moved the la and li instructions before the data they are
	assigned to, which prevents a bug where MIPS32 relocations are used instead
	of micromips relocations when building for micromips.

1 files changed, 284 insertions, 40 deletions

diff --git a/sim/mips/Makefile.in b/sim/mips/Makefile.in
index 17eeab6..f02e1bd 100644
--- a/sim/mips/Makefile.in
+++ b/sim/mips/Makefile.in
@@ -35,7 +35,29 @@ SIM_M16_OBJ = \
 	itable.o \
 	m16run.o \
 
-SIM_MULTI_OBJ = itable.o @sim_multi_obj@
+SIM_MICROMIPS_OBJ = \
+	micromips16_support.o \
+	micromips16_semantics.o \
+	micromips16_idecode.o \
+	micromips16_icache.o \
+	\
+	micromips32_support.o \
+	micromips32_semantics.o \
+	micromips32_idecode.o \
+	micromips32_icache.o \
+	\
+	micromips_m32_support.o \
+	micromips_m32_semantics.o \
+	micromips_m32_idecode.o \
+	micromips_m32_icache.o \
+	\
+	itable.o \
+	micromipsrun.o \
+
+
+SIM_MULTI_OBJ = @sim_multi_obj@ \
+		itable.o \
+		multi-run.o \
 
 MIPS_EXTRA_LIBS = @mips_extra_libs@
 
@@ -68,11 +90,11 @@ SIM_EXTRA_LIBS = $(MIPS_EXTRA_LIBS)
 ## COMMON_POST_CONFIG_FRAG
 
 interp.o: $(srcdir)/interp.c config.h sim-main.h itable.h
-cp1.o: $(srcdir)/cp1.c config.h sim-main.h
 
-mdmx.o: $(srcdir)/mdmx.c $(srcdir)/sim-main.h
+m16run.o: sim-main.h m16_idecode.h m32_idecode.h m16run.c $(SIM_EXTRA_DEPS)
 
-dsp.o: $(srcdir)/dsp.c $(srcdir)/sim-main.h
+micromipsrun.o: sim-main.h micromips16_idecode.h micromips32_idecode.h \
+		micromips_m32_idecode.h micromipsrun.c $(SIM_EXTRA_DEPS)
 
 multi-run.o: multi-include.h tmp-mach-multi
 
@@ -83,7 +105,11 @@ IGEN_TRACE= # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejec
 IGEN_INSN=$(srcdir)/mips.igen
 IGEN_DC=$(srcdir)/mips.dc
 M16_DC=$(srcdir)/m16.dc
+MICROMIPS32_DC=$(srcdir)/micromips.dc
+MICROMIPS16_DC=$(srcdir)/micromips16.dc
 IGEN_INCLUDE=\
+	$(srcdir)/micromipsdsp.igen \
+	$(srcdir)/micromips.igen \
 	$(srcdir)/m16.igen \
 	$(srcdir)/m16e.igen \
 	$(srcdir)/mdmx.igen \
@@ -104,6 +130,7 @@ BUILT_SRC_FROM_GEN = \
 
 SIM_IGEN_ALL = tmp-igen
 SIM_M16_ALL = tmp-m16
+SIM_MICROMIPS_ALL = tmp-micromips
 SIM_MULTI_ALL = tmp-multi
 
 $(BUILT_SRC_FROM_GEN): $(SIM_@sim_gen@_ALL)
@@ -174,25 +201,6 @@ tmp-igen: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
 	$(SHELL) $(srcdir)/../../move-if-change tmp-irun.c irun.c
 	touch tmp-igen
 
-semantics.o: sim-main.h semantics.c $(SIM_EXTRA_DEPS)
-engine.o: sim-main.h engine.c $(SIM_EXTRA_DEPS)
-support.o: sim-main.h support.c $(SIM_EXTRA_DEPS)
-idecode.o: sim-main.h idecode.c $(SIM_EXTRA_DEPS)
-itable.o: sim-main.h itable.c $(SIM_EXTRA_DEPS)
-m16run.o: sim-main.h m16_idecode.h m32_idecode.h $(SIM_EXTRA_DEPS)
-
-m16_semantics.o: sim-main.h m16_semantics.c $(SIM_EXTRA_DEPS)
-m16_support.o: sim-main.h m16_support.c $(SIM_EXTRA_DEPS)
-m16_idecode.o: sim-main.h m16_idecode.c $(SIM_EXTRA_DEPS)
-m16_icache.o: sim-main.h m16_icache.c $(SIM_EXTRA_DEPS)
-
-m32_semantics.o: sim-main.h m32_semantics.c $(SIM_EXTRA_DEPS)
-m32_support.o: sim-main.h m32_support.c $(SIM_EXTRA_DEPS)
-m32_idecode.o: sim-main.h m32_idecode.c $(SIM_EXTRA_DEPS)
-m32_icache.o: sim-main.h m32_icache.c $(SIM_EXTRA_DEPS)
-
-$(SIM_MULTI_OBJ): sim-main.h $(SIM_EXTRA_DEPS)
-
 BUILT_SRC_FROM_M16 = \
 	m16_icache.h \
 	m16_icache.c \
@@ -284,8 +292,10 @@ tmp-m16: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
 	$(SHELL) $(srcdir)/../../move-if-change tmp-icache.c m32_icache.c
 	$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.h m32_idecode.h
 	$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.c m32_idecode.c
-	$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h m32_semantics.h
-	$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c m32_semantics.c
+	$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h \
+						m32_semantics.h
+	$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c \
+						m32_semantics.c
 	$(SHELL) $(srcdir)/../../move-if-change tmp-model.h m32_model.h
 	$(SHELL) $(srcdir)/../../move-if-change tmp-model.c m32_model.c
 	$(SHELL) $(srcdir)/../../move-if-change tmp-support.h m32_support.h
@@ -307,6 +317,196 @@ tmp-m16: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
 	$(SHELL) $(srcdir)/../../move-if-change tmp-itable.c itable.c
 	touch tmp-m16
 
+BUILT_SRC_FROM_MICROMIPS = \
+	micromips16_icache.h \
+	micromips16_icache.c \
+	micromips16_idecode.h \
+	micromips16_idecode.c \
+	micromips16_semantics.h \
+	micromips16_semantics.c \
+	micromips16_model.h \
+	micromips16_model.c \
+	micromips16_support.h \
+	micromips16_support.c \
+	\
+	micromips32_icache.h \
+	micromips32_icache.c \
+	micromips32_idecode.h \
+	micromips32_idecode.c \
+	micromips32_semantics.h \
+	micromips32_semantics.c \
+	micromips32_model.h \
+	micromips32_model.c \
+	micromips32_support.h \
+	micromips32_support.c \
+	\
+	micromips_m32_icache.h \
+	micromips_m32_icache.c \
+	micromips_m32_idecode.h \
+	micromips_m32_idecode.c \
+	micromips_m32_semantics.h \
+	micromips_m32_semantics.c \
+	micromips_m32_model.h \
+	micromips_m32_model.c \
+	micromips_m32_support.h \
+	micromips_m32_support.c \
+
+$(BUILT_SRC_FROM_MICROMIPS): tmp-micromips
+
+tmp-micromips: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
+	cd ../igen && $(MAKE)
+	../igen/igen \
+		$(IGEN_TRACE) \
+		-I $(srcdir) \
+		-Werror \
+		-Wnodiscard \
+		@sim_micromips16_flags@ \
+		-G gen-direct-access \
+		-G gen-zero-r0 \
+		-B 16 \
+		-H 15 \
+		-i $(IGEN_INSN) \
+		-o $(MICROMIPS16_DC) \
+		-P micromips16_ \
+		-x \
+		-n micromips16_icache.h    -hc tmp-icache.h \
+		-n micromips16_icache.c    -c  tmp-icache.c \
+		-n micromips16_semantics.h -hs tmp-semantics.h \
+		-n micromips16_semantics.c -s  tmp-semantics.c \
+		-n micromips16_idecode.h   -hd tmp-idecode.h \
+		-n micromips16_idecode.c   -d  tmp-idecode.c \
+		-n micromips16_model.h     -hm tmp-model.h \
+		-n micromips16_model.c     -m  tmp-model.c \
+		-n micromips16_support.h   -hf tmp-support.h \
+		-n micromips16_support.c   -f  tmp-support.c \
+		#
+	$(SHELL) $(srcdir)/../../move-if-change tmp-icache.h \
+						micromips16_icache.h
+	$(SHELL) $(srcdir)/../../move-if-change tmp-icache.c \
+						micromips16_icache.c
+	$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.h \
+						micromips16_idecode.h
+	$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.c \
+						micromips16_idecode.c
+	$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h \
+						micromips16_semantics.h
+	$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c \
+						micromips16_semantics.c
+	$(SHELL) $(srcdir)/../../move-if-change tmp-model.h \
+						micromips16_model.h
+	$(SHELL) $(srcdir)/../../move-if-change tmp-model.c \
+						micromips16_model.c
+	$(SHELL) $(srcdir)/../../move-if-change tmp-support.h \
+						micromips16_support.h
+	$(SHELL) $(srcdir)/../../move-if-change tmp-support.c \
+						micromips16_support.c
+	cd ../igen && $(MAKE)
+	../igen/igen \
+		$(IGEN_TRACE) \
+		-I $(srcdir) \
+		-Werror \
+		-Wnodiscard \
+		@sim_micromips_flags@ \
+		-G gen-direct-access \
+		-G gen-zero-r0 \
+		-B 32 \
+		-H 31 \
+		-i $(IGEN_INSN) \
+		-o $(MICROMIPS32_DC) \
+		-P micromips32_ \
+		-x \
+		-n micromips32_icache.h    -hc tmp-icache.h \
+		-n micromips32_icache.c    -c  tmp-icache.c \
+		-n micromips32_semantics.h -hs tmp-semantics.h \
+		-n micromips32_semantics.c -s  tmp-semantics.c \
+		-n micromips32_idecode.h   -hd tmp-idecode.h \
+		-n micromips32_idecode.c   -d  tmp-idecode.c \
+		-n micromips32_model.h     -hm tmp-model.h \
+		-n micromips32_model.c     -m  tmp-model.c \
+		-n micromips32_support.h   -hf tmp-support.h \
+		-n micromips32_support.c   -f  tmp-support.c \
+		#
+	$(SHELL) $(srcdir)/../../move-if-change tmp-icache.h \
+						micromips32_icache.h
+	$(SHELL) $(srcdir)/../../move-if-change tmp-icache.c \
+						micromips32_icache.c
+	$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.h  \
+						micromips32_idecode.h
+	$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.c \
+						micromips32_idecode.c
+	$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h \
+						micromips32_semantics.h
+	$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c \
+						micromips32_semantics.c
+	$(SHELL) $(srcdir)/../../move-if-change tmp-model.h \
+						micromips32_model.h
+	$(SHELL) $(srcdir)/../../move-if-change tmp-model.c  \
+						micromips32_model.c
+	$(SHELL) $(srcdir)/../../move-if-change tmp-support.h \
+						micromips32_support.h
+	$(SHELL) $(srcdir)/../../move-if-change tmp-support.c \
+						micromips32_support.c
+	../igen/igen \
+		$(IGEN_TRACE) \
+		-I $(srcdir) \
+		-Werror \
+		-Wnodiscard \
+		@sim_igen_flags@ \
+		-G gen-direct-access \
+		-G gen-zero-r0 \
+		-B 32 \
+		-H 31 \
+		-i $(IGEN_INSN) \
+		-o $(IGEN_DC) \
+		-P micromips_m32_ \
+		-x \
+		-n micromips_m32_icache.h    -hc tmp-icache.h \
+		-n micromips_m32_icache.c    -c  tmp-icache.c \
+		-n micromips_m32_semantics.h -hs tmp-semantics.h \
+		-n micromips_m32_semantics.c -s  tmp-semantics.c \
+		-n micromips_m32_idecode.h   -hd tmp-idecode.h \
+		-n micromips_m32_idecode.c   -d  tmp-idecode.c \
+		-n micromips_m32_model.h     -hm tmp-model.h \
+		-n micromips_m32_model.c     -m  tmp-model.c \
+		-n micromips_m32_support.h   -hf tmp-support.h \
+		-n micromips_m32_support.c   -f  tmp-support.c \
+		#
+	$(SHELL) $(srcdir)/../../move-if-change tmp-icache.h \
+						micromips_m32_icache.h
+	$(SHELL) $(srcdir)/../../move-if-change tmp-icache.c \
+						micromips_m32_icache.c
+	$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.h \
+						micromips_m32_idecode.h
+	$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.c \
+						micromips_m32_idecode.c
+	$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h \
+						micromips_m32_semantics.h
+	$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c \
+						micromips_m32_semantics.c
+	$(SHELL) $(srcdir)/../../move-if-change tmp-model.h \
+						micromips_m32_model.h
+	$(SHELL) $(srcdir)/../../move-if-change tmp-model.c \
+						micromips_m32_model.c
+	$(SHELL) $(srcdir)/../../move-if-change tmp-support.h \
+						micromips_m32_support.h
+	$(SHELL) $(srcdir)/../../move-if-change tmp-support.c \
+						micromips_m32_support.c
+	../igen/igen \
+		$(IGEN_TRACE) \
+		-I $(srcdir) \
+		-Werror \
+		-Wnodiscard \
+		-Wnowidth \
+		@sim_igen_flags@ @sim_micromips_flags@ @sim_micromips16_flags@\
+		-G gen-direct-access \
+		-G gen-zero-r0 \
+		-i $(IGEN_INSN) \
+		-n itable.h    -ht tmp-itable.h \
+		-n itable.c    -t  tmp-itable.c \
+		#
+	$(SHELL) $(srcdir)/../../move-if-change tmp-itable.h itable.h
+	$(SHELL) $(srcdir)/../../move-if-change tmp-itable.c itable.c
+	touch tmp-micromips
 
 BUILT_SRC_FROM_MULTI = @sim_multi_src@
 SIM_MULTI_IGEN_CONFIGS = @sim_multi_igen_configs@
@@ -319,6 +519,15 @@ tmp-mach-multi: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
 	  m=`echo $${t} | sed -e 's/.*:\(.*\):.*/\1/'` ; \
 	  f=`echo $${t} | sed -e 's/.*://'` ; \
 	  case $${p} in \
+	    micromips16*) e="-B 16 -H 15 -o $(MICROMIPS16_DC) -F 16" ;; \
+	    micromips32* | micromips64*) \
+		e="-B 32 -H 31 -o $(MICROMIPS32_DC) -F $${f}" ;; \
+	    micromips_m32*) \
+		e="-B 32 -H 31 -o $(IGEN_DC) -F $${f}"; \
+		m="mips32r2,mips3d,mdmx,dsp,dsp2,smartmips" ;; \
+	    micromips_m64*) \
+		e="-B 32 -H 31 -o $(IGEN_DC) -F $${f}"; \
+		m="mips64r2,mips3d,mdmx,dsp,dsp2,smartmips" ;; \
 	    m16*) e="-B 16 -H 15 -o $(M16_DC) -F 16" ;; \
 	    *) e="-B 32 -H 31 -o $(IGEN_DC) -F $${f}" ;; \
 	  esac; \
@@ -348,18 +557,30 @@ tmp-mach-multi: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
 		-n $${p}_engine.h    -he tmp-engine.h \
 		-n $${p}_engine.c    -e  tmp-engine.c \
 	  || exit; \
-	  $(SHELL) $(srcdir)/../../move-if-change tmp-icache.h $${p}_icache.h ; \
-	  $(SHELL) $(srcdir)/../../move-if-change tmp-icache.c $${p}_icache.c ; \
-	  $(SHELL) $(srcdir)/../../move-if-change tmp-idecode.h $${p}_idecode.h ; \
-	  $(SHELL) $(srcdir)/../../move-if-change tmp-idecode.c $${p}_idecode.c ; \
-	  $(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h $${p}_semantics.h ; \
-	  $(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c $${p}_semantics.c ; \
-	  $(SHELL) $(srcdir)/../../move-if-change tmp-model.h $${p}_model.h ; \
-	  $(SHELL) $(srcdir)/../../move-if-change tmp-model.c $${p}_model.c ; \
-	  $(SHELL) $(srcdir)/../../move-if-change tmp-support.h $${p}_support.h ; \
-	  $(SHELL) $(srcdir)/../../move-if-change tmp-support.c $${p}_support.c ; \
-	  $(SHELL) $(srcdir)/../../move-if-change tmp-engine.h $${p}_engine.h ; \
-	  $(SHELL) $(srcdir)/../../move-if-change tmp-engine.c $${p}_engine.c ; \
+	  $(SHELL) $(srcdir)/../../move-if-change tmp-icache.h \
+						  $${p}_icache.h ; \
+	  $(SHELL) $(srcdir)/../../move-if-change tmp-icache.c \
+						  $${p}_icache.c ; \
+	  $(SHELL) $(srcdir)/../../move-if-change tmp-idecode.h \
+						  $${p}_idecode.h ; \
+	  $(SHELL) $(srcdir)/../../move-if-change tmp-idecode.c \
+						  $${p}_idecode.c ; \
+	  $(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h \
+						  $${p}_semantics.h ; \
+	  $(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c \
+						  $${p}_semantics.c ; \
+	  $(SHELL) $(srcdir)/../../move-if-change tmp-model.h \
+						  $${p}_model.h ; \
+	  $(SHELL) $(srcdir)/../../move-if-change tmp-model.c \
+						  $${p}_model.c ; \
+	  $(SHELL) $(srcdir)/../../move-if-change tmp-support.h \
+						  $${p}_support.h ; \
+	  $(SHELL) $(srcdir)/../../move-if-change tmp-support.c \
+						  $${p}_support.c ; \
+	  $(SHELL) $(srcdir)/../../move-if-change tmp-engine.h \
+						  $${p}_engine.h ; \
+	  $(SHELL) $(srcdir)/../../move-if-change tmp-engine.c \
+						  $${p}_engine.c ; \
 	done
 	touch tmp-mach-multi
 tmp-itable-multi: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
@@ -380,7 +601,7 @@ tmp-itable-multi: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
 	$(SHELL) $(srcdir)/../../move-if-change tmp-itable.h itable.h
 	$(SHELL) $(srcdir)/../../move-if-change tmp-itable.c itable.c
 	touch tmp-itable-multi
-tmp-run-multi: $(srcdir)/m16run.c
+tmp-run-multi: $(srcdir)/m16run.c $(srcdir)/micromipsrun.c
 	for t in $(SIM_MULTI_IGEN_CONFIGS); do \
 	  case $${t} in \
 	    m16*) \
@@ -389,7 +610,29 @@ tmp-run-multi: $(srcdir)/m16run.c
 		    -e "s/^sim_/m16$${m}_/" \
 		    -e "s/m16_/m16$${m}_/" \
 		    -e "s/m32_/m32$${m}_/" ; \
-	      $(SHELL) $(srcdir)/../../move-if-change tmp-run m16$${m}_run.c ; \
+	      $(SHELL) $(srcdir)/../../move-if-change tmp-run \
+						      m16$${m}_run.c ; \
+            ;;\
+	    micromips32*) \
+	      m=`echo $${t} | sed -e 's/^micromips32//' -e 's/:.*//'`; \
+	      sed <  $(srcdir)/micromipsrun.c > tmp-run \
+		    -e "s/^sim_/micromips32$${m}_/" \
+		    -e "s/micromips16_/micromips16$${m}_/" \
+		    -e "s/micromips32_/micromips32$${m}_/" \
+		    -e "s/m32_/m32$${m}_/" ; \
+	      $(SHELL) $(srcdir)/../../move-if-change tmp-run \
+						      micromips$${m}_run.c ; \
+             ;;\
+	    micromips64*) \
+	      m=`echo $${t} | sed -e 's/^micromips64//' -e 's/:.*//'`; \
+	      sed <  $(srcdir)/micromipsrun.c > tmp-run \
+		    -e "s/^sim_/micromips64$${m}_/" \
+		    -e "s/micromips16_/micromips16$${m}_/" \
+		    -e "s/micromips32_/micromips64$${m}_/" \
+		    -e "s/m32_/m64$${m}_/" ; \
+	      $(SHELL) $(srcdir)/../../move-if-change tmp-run \
+						      micromips$${m}_run.c ; \
+             ;;\
 	  esac \
 	done
 	touch tmp-run-multi
@@ -398,9 +641,10 @@ clean-extra:
 	rm -f $(BUILT_SRC_FROM_GEN)
 	rm -f $(BUILT_SRC_FROM_IGEN)
 	rm -f $(BUILT_SRC_FROM_M16)
+	rm -f $(BUILT_SRC_FROM_MICROMIPS)
 	rm -f $(BUILT_SRC_FROM_MULTI)
 	rm -f tmp-*
-	rm -f m16*.o m32*.o itable*.o
+	rm -f micromips16*.o micromips32*.o m16*.o m32*.o itable*.o
 
 distclean-extra:
 	rm -f multi-include.h multi-run.c