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| author | Andrew Cagney <cagney@redhat.com> | 1997-11-05 08:17:26 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 1997-11-05 08:17:26 +0000 |
| commit | 63be8febf762353b62e794963fdc65f1280a7498 (patch) | |
| tree | 3d79e72b7f56c6597f4285efcc55562938d902ef /sim/mips/Makefile.in | |
| parent | 22de994d0e830082802fdd9033af16fb34f58dde (diff) | |
| download | gdb-63be8febf762353b62e794963fdc65f1280a7498.zip gdb-63be8febf762353b62e794963fdc65f1280a7498.tar.gz gdb-63be8febf762353b62e794963fdc65f1280a7498.tar.bz2 | |
Rewrite the MIPS simulator's memory model so that it uses the generic
common/sim-core.
Add support for 3, 5, 6, 7 byte transfers to sim core.
Diffstat (limited to 'sim/mips/Makefile.in')
| -rw-r--r-- | sim/mips/Makefile.in | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/sim/mips/Makefile.in b/sim/mips/Makefile.in index 1b5e503..c8e42c0 100644 --- a/sim/mips/Makefile.in +++ b/sim/mips/Makefile.in @@ -38,6 +38,7 @@ SIM_OBJS = \ sim-config.o \ sim-endian.o \ sim-engine.o \ + sim-memopt.o \ sim-stop.o \ sim-resume.o \ sim-reason.o \ |