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| author | Andrew Cagney <cagney@redhat.com> | 1997-11-11 07:50:13 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 1997-11-11 07:50:13 +0000 |
| commit | 030843d7f82aaf1ea2752cbdbb79013256acb847 (patch) | |
| tree | caeb7f66c0f776b6771bc03d7a554e3ada068658 /sim/mips/ChangeLog | |
| parent | f445a8902d6862078a541defb2b8ae29daa6d37d (diff) | |
| download | gdb-030843d7f82aaf1ea2752cbdbb79013256acb847.zip gdb-030843d7f82aaf1ea2752cbdbb79013256acb847.tar.gz gdb-030843d7f82aaf1ea2752cbdbb79013256acb847.tar.bz2 | |
Fix IGEN version of MFC0, MTC0, SWC1, LWC1, SDC1, LDC1, LWXC1,
SWXC1MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1, MULT, MULTU, BEQZ, ...MTHI,
MFHI instructions.
Trace nullified instruction.
Diffstat (limited to 'sim/mips/ChangeLog')
| -rw-r--r-- | sim/mips/ChangeLog | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog index 16a6e24..53a3d30 100644 --- a/sim/mips/ChangeLog +++ b/sim/mips/ChangeLog @@ -1,3 +1,22 @@ +Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * mips.igen: Delay slot branches add OFFSET to NIA not CIA. + (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement. + (start-sanitize-r5900): + (LWXC1, SWXC1): Delete from r5900 instruction set. + (end-sanitize-r5900): + (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non + PENDING_FILL versions of instructions. + (X): New function. + (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of + instructions. + (BEQZ, ...): Explicitly cast GPR to a signed value. + (MTHI, MFHI): Disable code checking HI-LO. + + * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh + global. + (NULLIFY_NEXT_INSTRUCTION): Call dotrace. + Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com> * gencode.c (build_mips16_operands): Replace IPC with cia. |