* m68hc11_sim.c (cpu_move8): Call sim_engine_abort in default case.

	(cpu_move16): Likewise.
	(sim_memory_error): Use sim_io_printf.
	(cpu_option_handler): Fix compilation warning.
	* interp.c (sim_hw_configure): Fix compilation warning;
	remove m68hc12sio@2 device.
	(sim_open): Likewise.
	* dv-m68hc11tim.c (m68hc11tim_port_event): Fix clear of TFLG2
	flags when reset.
	(cycle_to_string): Improve convertion of cpu cycle number.
	(m68hc11tim_info): Print info about PACNT.
	(m68hc11tim_io_write_buffer): Fix clearing of TFLG2; handle
	TCTL1 and TCTL2 registers.
	* dv-m68hc11.c (m68hc11_info): Print 6811 current running mode.

1 files changed, 33 insertions, 20 deletions

diff --git a/sim/m68hc11/dv-m68hc11tim.c b/sim/m68hc11/dv-m68hc11tim.c
index 9b0f338..3edcac0 100644
--- a/sim/m68hc11/dv-m68hc11tim.c
+++ b/sim/m68hc11/dv-m68hc11tim.c
@@ -194,13 +194,13 @@ m68hc11tim_port_event (struct hw *me,
           }
 
         /* Reset the state of Timer registers.  This also restarts
-           the timer events (overflow and RTI clock).  */
+           the timer events (overflow and RTI clock).  The pending
+           flags (TFLG2) must be cleared explicitly here.  */
         val = 0;
+        cpu->ios[M6811_TFLG2] = 0;
         m68hc11tim_io_write_buffer (me, &val, io_map,
                                     (unsigned_word) M6811_TMSK2, 1);
         m68hc11tim_io_write_buffer (me, &val, io_map,
-                                    (unsigned_word) M6811_TFLG2, 1);
-        m68hc11tim_io_write_buffer (me, &val, io_map,
                                     (unsigned_word) M6811_PACTL, 1);
         break;
       }
@@ -436,17 +436,19 @@ const char*
 cycle_to_string (sim_cpu *cpu, signed64 t)
 {
   double dt;
+  char tbuf[32];
   static char buf[64];
-  
+
   dt = to_realtime (cpu, t);
   if (dt < 0.001)
-    sprintf (buf, "%llu cycle%s (%3.1f us)", t,
-             (t > 1 ? "s" : ""), dt * 1000000.0);
+    sprintf (tbuf, "(%3.1f us)", dt * 1000000.0);
   else if (dt < 1.0)
-    sprintf (buf, "%llu cycles (%3.1f ms)", t, dt * 1000.0);
+    sprintf (tbuf, "(%3.1f ms)", dt * 1000.0);
   else
-    sprintf (buf, "%llu cycles (%3.1f s)", t, dt);
+    sprintf (tbuf, "(%3.1f s)", dt);
 
+  sprintf (buf, "%llu cycle%s %10.10s", t,
+             (t > 1 ? "s" : ""), tbuf);
   return buf;
 }
 
@@ -503,6 +505,10 @@ m68hc11tim_info (struct hw *me)
   print_io_byte (sd, "PACTL", pactl_desc, val, base + M6811_PACTL);
   sim_io_printf (sd, "\n");
 
+  val = cpu->ios[M6811_PACNT];
+  print_io_byte (sd, "PACNT", 0, val, base + M6811_PACNT);
+  sim_io_printf (sd, "\n");
+
   /* Give info about the next timer interrupts.  */
   m68hc11tim_print_timer (me, "RTI", controller->rti_timer_event);
   m68hc11tim_print_timer (me, "COP", controller->cop_timer_event);
@@ -625,7 +631,7 @@ m68hc11tim_io_write_buffer (struct hw *me,
 
         case M6811_TMSK2:
 
-      /* Timer prescaler cannot be changed after 64 bus cycles.  */
+          /* Timer prescaler cannot be changed after 64 bus cycles.  */
           if (cpu->cpu_absolute_cycle >= 64)
             {
               val &= ~(M6811_PR1 | M6811_PR0);
@@ -665,21 +671,22 @@ m68hc11tim_io_write_buffer (struct hw *me,
           break;
       
         case M6811_TFLG2:
-          if (val & M6811_TOF)
-            val &= ~M6811_TOF;
-          else
-            val |= cpu->ios[M6811_TFLG2] & M6811_TOF;
+          val &= cpu->ios[M6811_TFLG2];
+          cpu->ios[M6811_TFLG2] &= ~val;
+          interrupts_update_pending (&cpu->cpu_interrupts);
+          break;
 
-      /* Clear the Real Time interrupt flag. */
-          if (val & M6811_RTIF)
-            val &= ~M6811_RTIF;
-          else
-            val |= cpu->ios[M6811_TFLG2] & M6811_RTIF;
-      
-          cpu->ios[base] = val;
+        case M6811_TMSK1:
+          cpu->ios[M6811_TMSK1] = val;
           interrupts_update_pending (&cpu->cpu_interrupts);
           break;
 
+        case M6811_TFLG1:
+          val &= cpu->ios[M6811_TFLG1];
+          cpu->ios[M6811_TFLG1] &= ~val;
+          interrupts_update_pending (&cpu->cpu_interrupts);          
+          break;
+
         case M6811_TOC1:
         case M6811_TOC2:
         case M6811_TOC3:
@@ -689,7 +696,13 @@ m68hc11tim_io_write_buffer (struct hw *me,
           reset_compare = 1;
           break;
       
+        case M6811_TCTL1:
+        case M6811_TCTL2:
+          cpu->ios[base] = val;
+          break;
+
         default:
+          cpu->ios[base] = val;
           break;
         }