aboutsummaryrefslogtreecommitdiff
path: root/sim/m68hc11/ChangeLog
diff options
context:
space:
mode:
authorStephane Carrez <stcarrez@nerim.fr>2002-08-13 07:46:09 +0000
committerStephane Carrez <stcarrez@nerim.fr>2002-08-13 07:46:09 +0000
commit63f36def60e0ebb54113a819db684887d036b387 (patch)
tree9733144136e5c4f171c1dd6c92c1d1e0f664cfc2 /sim/m68hc11/ChangeLog
parentbed69f0439536ace7602fdfc7a04dde1dc68d31a (diff)
downloadgdb-63f36def60e0ebb54113a819db684887d036b387.zip
gdb-63f36def60e0ebb54113a819db684887d036b387.tar.gz
gdb-63f36def60e0ebb54113a819db684887d036b387.tar.bz2
* m68hc11_sim.c (cpu_special): Handle call and rtc instructions.
* sim-main.h (M6812_CALL_INDIRECT): Add to enum. (m6811_regs): Add page register. (cpu_set_page, cpu_get_page): New macros. (phys_to_virt): New function. (cpu_get_indexed_operand_addr, cpu_return): Declare. * gencode.c: Identify indirect addressing mode for call and fix daa. (gen_function_entry): New param to tell if src8/dst8 locals are necessary. (gen_interpreter): Use it to avoid generation of unused variables. * interp.c (sim_fetch_register): Allow to read page register; page register, A, B and CCR are only 1 byte wide. (sim_store_register): Likewise for writing.
Diffstat (limited to 'sim/m68hc11/ChangeLog')
-rw-r--r--sim/m68hc11/ChangeLog16
1 files changed, 16 insertions, 0 deletions
diff --git a/sim/m68hc11/ChangeLog b/sim/m68hc11/ChangeLog
index 7c08019..95047da 100644
--- a/sim/m68hc11/ChangeLog
+++ b/sim/m68hc11/ChangeLog
@@ -1,3 +1,19 @@
+2002-08-13 Stephane Carrez <stcarrez@nerim.fr>
+
+ * m68hc11_sim.c (cpu_special): Handle call and rtc instructions.
+ * sim-main.h (M6812_CALL_INDIRECT): Add to enum.
+ (m6811_regs): Add page register.
+ (cpu_set_page, cpu_get_page): New macros.
+ (phys_to_virt): New function.
+ (cpu_get_indexed_operand_addr, cpu_return): Declare.
+ * gencode.c: Identify indirect addressing mode for call and fix daa.
+ (gen_function_entry): New param to tell if src8/dst8 locals are
+ necessary.
+ (gen_interpreter): Use it to avoid generation of unused variables.
+ * interp.c (sim_fetch_register): Allow to read page register; page
+ register, A, B and CCR are only 1 byte wide.
+ (sim_store_register): Likewise for writing.
+
2002-06-16 Andrew Cagney <ac131313@redhat.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.