import gdb-19990422 snapshot

14 files changed, 691 insertions, 1001 deletions

diff --git a/sim/m32r/ChangeLog b/sim/m32r/ChangeLog
index aba789a..010f2a4 100644
--- a/sim/m32r/ChangeLog
+++ b/sim/m32r/ChangeLog
@@ -1,3 +1,45 @@
+Fri Apr 16 16:47:43 1999  Doug Evans  <devans@charmed.cygnus.com>
+
+	* devices.c (device_io_read_buffer): New arg `sd'.
+	(device_io_write_buffer): New arg `sd'.
+	(device_error): Give proper arg spec.
+
+1999-04-10  Doug Evans  <devans@casey.cygnus.com>
+
+	* sem-switch.c,sem.c: Rebuild.
+
+1999-03-27  Doug Evans  <devans@casey.cygnus.com>
+
+	* decode.c: Rebuild.
+
+1999-03-26  Doug Evans  <devans@casey.cygnus.com>
+
+	* m32r-sim.h (M32R_DEVICE_LEN): Fix off by one error.
+
+1999-03-22  Doug Evans  <devans@casey.cygnus.com>
+
+	* arch.c,arch.h,model.c: Rebuild.
+	* m32r-sim.h (a_m32r_h_gr_get,a_m32r_h_gr_set): Declare.
+	(a_m32r_h_cr_get,a_m32r_h_cr_set): Declare.
+	* m32r.c (m32rbf_fetch_register): Replace calls to a_m32r_h_pc_get,
+	a_m32r_h_accum_get with appropriate calls to m32rbf_*.
+	(m32rbf_store_register): Ditto.
+	(a_m32r_h_gr_get,a_m32r_h_gr_set): New functions.
+	(a_m32r_h_cr_get,a_m32r_h_cr_set): Ditto.
+	* sim-if.c (sim_open): Update call to m32r_cgen_cpu_open.
+	* traps.c (m32r_core_signal): Replace calls to a_m32r_h_*,
+	with appropriate calls to m32rbf_*.
+
+1999-03-11  Doug Evans  <devans@casey.cygnus.com>
+
+	* arch.c,arch.h,cpu.c,cpu.h,sem.c,sem-switch.c: Rebuild.
+	* m32r-sim.h (GET_H_*,SET_H_*, except GET_H_SM): Delete.
+	* sim-if.c (sim_open): Update call to m32r_cgen_cpu_open.
+
+1999-02-25  Doug Evans  <devans@casey.cygnus.com>
+
+	* cpu.c,cpu.h: Rebuild.
+
 1999-02-09  Doug Evans  <devans@casey.cygnus.com>
 
 	* Makefile.in (SIM_EXTRA_DEPS): Add m32r-desc.h, delete cpu-opc.h.
diff --git a/sim/m32r/arch.c b/sim/m32r/arch.c
index 2caa300..c6da47c 100644
--- a/sim/m32r/arch.c
+++ b/sim/m32r/arch.c
@@ -33,324 +33,3 @@ const MACH *sim_machs[] =
   0
 };
 
-/* Get the value of h-pc.  */
-
-USI
-a_m32r_h_pc_get (SIM_CPU *current_cpu)
-{
-  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
-    {
-#ifdef HAVE_CPU_M32RBF
-    case bfd_mach_m32r : 
-      return m32rbf_h_pc_get (current_cpu);
-#endif
-    default :
-      abort ();
-    }
-}
-
-/* Set a value for h-pc.  */
-
-void
-a_m32r_h_pc_set (SIM_CPU *current_cpu, USI newval)
-{
-  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
-    {
-#ifdef HAVE_CPU_M32RBF
-    case bfd_mach_m32r : 
-      m32rbf_h_pc_set (current_cpu, newval);
-      break;
-#endif
-    default :
-      abort ();
-    }
-}
-
-/* Get the value of h-gr.  */
-
-SI
-a_m32r_h_gr_get (SIM_CPU *current_cpu, UINT regno)
-{
-  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
-    {
-#ifdef HAVE_CPU_M32RBF
-    case bfd_mach_m32r : 
-      return m32rbf_h_gr_get (current_cpu, regno);
-#endif
-    default :
-      abort ();
-    }
-}
-
-/* Set a value for h-gr.  */
-
-void
-a_m32r_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
-{
-  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
-    {
-#ifdef HAVE_CPU_M32RBF
-    case bfd_mach_m32r : 
-      m32rbf_h_gr_set (current_cpu, regno, newval);
-      break;
-#endif
-    default :
-      abort ();
-    }
-}
-
-/* Get the value of h-cr.  */
-
-USI
-a_m32r_h_cr_get (SIM_CPU *current_cpu, UINT regno)
-{
-  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
-    {
-#ifdef HAVE_CPU_M32RBF
-    case bfd_mach_m32r : 
-      return m32rbf_h_cr_get (current_cpu, regno);
-#endif
-    default :
-      abort ();
-    }
-}
-
-/* Set a value for h-cr.  */
-
-void
-a_m32r_h_cr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
-{
-  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
-    {
-#ifdef HAVE_CPU_M32RBF
-    case bfd_mach_m32r : 
-      m32rbf_h_cr_set (current_cpu, regno, newval);
-      break;
-#endif
-    default :
-      abort ();
-    }
-}
-
-/* Get the value of h-accum.  */
-
-DI
-a_m32r_h_accum_get (SIM_CPU *current_cpu)
-{
-  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
-    {
-#ifdef HAVE_CPU_M32RBF
-    case bfd_mach_m32r : 
-      return m32rbf_h_accum_get (current_cpu);
-#endif
-    default :
-      abort ();
-    }
-}
-
-/* Set a value for h-accum.  */
-
-void
-a_m32r_h_accum_set (SIM_CPU *current_cpu, DI newval)
-{
-  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
-    {
-#ifdef HAVE_CPU_M32RBF
-    case bfd_mach_m32r : 
-      m32rbf_h_accum_set (current_cpu, newval);
-      break;
-#endif
-    default :
-      abort ();
-    }
-}
-
-/* Get the value of h-accums.  */
-
-DI
-a_m32r_h_accums_get (SIM_CPU *current_cpu, UINT regno)
-{
-  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
-    {
-    default :
-      abort ();
-    }
-}
-
-/* Set a value for h-accums.  */
-
-void
-a_m32r_h_accums_set (SIM_CPU *current_cpu, UINT regno, DI newval)
-{
-  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
-    {
-    default :
-      abort ();
-    }
-}
-
-/* Get the value of h-cond.  */
-
-BI
-a_m32r_h_cond_get (SIM_CPU *current_cpu)
-{
-  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
-    {
-#ifdef HAVE_CPU_M32RBF
-    case bfd_mach_m32r : 
-      return m32rbf_h_cond_get (current_cpu);
-#endif
-    default :
-      abort ();
-    }
-}
-
-/* Set a value for h-cond.  */
-
-void
-a_m32r_h_cond_set (SIM_CPU *current_cpu, BI newval)
-{
-  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
-    {
-#ifdef HAVE_CPU_M32RBF
-    case bfd_mach_m32r : 
-      m32rbf_h_cond_set (current_cpu, newval);
-      break;
-#endif
-    default :
-      abort ();
-    }
-}
-
-/* Get the value of h-psw.  */
-
-UQI
-a_m32r_h_psw_get (SIM_CPU *current_cpu)
-{
-  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
-    {
-#ifdef HAVE_CPU_M32RBF
-    case bfd_mach_m32r : 
-      return m32rbf_h_psw_get (current_cpu);
-#endif
-    default :
-      abort ();
-    }
-}
-
-/* Set a value for h-psw.  */
-
-void
-a_m32r_h_psw_set (SIM_CPU *current_cpu, UQI newval)
-{
-  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
-    {
-#ifdef HAVE_CPU_M32RBF
-    case bfd_mach_m32r : 
-      m32rbf_h_psw_set (current_cpu, newval);
-      break;
-#endif
-    default :
-      abort ();
-    }
-}
-
-/* Get the value of h-bpsw.  */
-
-UQI
-a_m32r_h_bpsw_get (SIM_CPU *current_cpu)
-{
-  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
-    {
-#ifdef HAVE_CPU_M32RBF
-    case bfd_mach_m32r : 
-      return m32rbf_h_bpsw_get (current_cpu);
-#endif
-    default :
-      abort ();
-    }
-}
-
-/* Set a value for h-bpsw.  */
-
-void
-a_m32r_h_bpsw_set (SIM_CPU *current_cpu, UQI newval)
-{
-  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
-    {
-#ifdef HAVE_CPU_M32RBF
-    case bfd_mach_m32r : 
-      m32rbf_h_bpsw_set (current_cpu, newval);
-      break;
-#endif
-    default :
-      abort ();
-    }
-}
-
-/* Get the value of h-bbpsw.  */
-
-UQI
-a_m32r_h_bbpsw_get (SIM_CPU *current_cpu)
-{
-  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
-    {
-#ifdef HAVE_CPU_M32RBF
-    case bfd_mach_m32r : 
-      return m32rbf_h_bbpsw_get (current_cpu);
-#endif
-    default :
-      abort ();
-    }
-}
-
-/* Set a value for h-bbpsw.  */
-
-void
-a_m32r_h_bbpsw_set (SIM_CPU *current_cpu, UQI newval)
-{
-  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
-    {
-#ifdef HAVE_CPU_M32RBF
-    case bfd_mach_m32r : 
-      m32rbf_h_bbpsw_set (current_cpu, newval);
-      break;
-#endif
-    default :
-      abort ();
-    }
-}
-
-/* Get the value of h-lock.  */
-
-BI
-a_m32r_h_lock_get (SIM_CPU *current_cpu)
-{
-  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
-    {
-#ifdef HAVE_CPU_M32RBF
-    case bfd_mach_m32r : 
-      return m32rbf_h_lock_get (current_cpu);
-#endif
-    default :
-      abort ();
-    }
-}
-
-/* Set a value for h-lock.  */
-
-void
-a_m32r_h_lock_set (SIM_CPU *current_cpu, BI newval)
-{
-  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
-    {
-#ifdef HAVE_CPU_M32RBF
-    case bfd_mach_m32r : 
-      m32rbf_h_lock_set (current_cpu, newval);
-      break;
-#endif
-    default :
-      abort ();
-    }
-}
-
diff --git a/sim/m32r/arch.h b/sim/m32r/arch.h
index ace8104..f5ea3b2 100644
--- a/sim/m32r/arch.h
+++ b/sim/m32r/arch.h
@@ -27,28 +27,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 
 #define TARGET_BIG_ENDIAN 1
 
-/* Cover fns for register access.  */
-USI a_m32r_h_pc_get (SIM_CPU *);
-void a_m32r_h_pc_set (SIM_CPU *, USI);
-SI a_m32r_h_gr_get (SIM_CPU *, UINT);
-void a_m32r_h_gr_set (SIM_CPU *, UINT, SI);
-USI a_m32r_h_cr_get (SIM_CPU *, UINT);
-void a_m32r_h_cr_set (SIM_CPU *, UINT, USI);
-DI a_m32r_h_accum_get (SIM_CPU *);
-void a_m32r_h_accum_set (SIM_CPU *, DI);
-DI a_m32r_h_accums_get (SIM_CPU *, UINT);
-void a_m32r_h_accums_set (SIM_CPU *, UINT, DI);
-BI a_m32r_h_cond_get (SIM_CPU *);
-void a_m32r_h_cond_set (SIM_CPU *, BI);
-UQI a_m32r_h_psw_get (SIM_CPU *);
-void a_m32r_h_psw_set (SIM_CPU *, UQI);
-UQI a_m32r_h_bpsw_get (SIM_CPU *);
-void a_m32r_h_bpsw_set (SIM_CPU *, UQI);
-UQI a_m32r_h_bbpsw_get (SIM_CPU *);
-void a_m32r_h_bbpsw_set (SIM_CPU *, UQI);
-BI a_m32r_h_lock_get (SIM_CPU *);
-void a_m32r_h_lock_set (SIM_CPU *, BI);
-
 /* Enum declaration for model types.  */
 typedef enum model_type {
   MODEL_M32R_D, MODEL_TEST
diff --git a/sim/m32r/cpu.c b/sim/m32r/cpu.c
index fb856f5..f6474a0 100644
--- a/sim/m32r/cpu.c
+++ b/sim/m32r/cpu.c
@@ -26,6 +26,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #define WANT_CPU_M32RBF
 
 #include "sim-main.h"
+#include "cgen-ops.h"
 
 /* Get the value of h-pc.  */
 
@@ -91,22 +92,6 @@ m32rbf_h_accum_set (SIM_CPU *current_cpu, DI newval)
   SET_H_ACCUM (newval);
 }
 
-/* Get the value of h-accums.  */
-
-DI
-m32rbf_h_accums_get (SIM_CPU *current_cpu, UINT regno)
-{
-  return GET_H_ACCUMS (regno);
-}
-
-/* Set a value for h-accums.  */
-
-void
-m32rbf_h_accums_set (SIM_CPU *current_cpu, UINT regno, DI newval)
-{
-  SET_H_ACCUMS (regno, newval);
-}
-
 /* Get the value of h-cond.  */
 
 BI
diff --git a/sim/m32r/cpu.h b/sim/m32r/cpu.h
index ccb4676..6ebe199 100644
--- a/sim/m32r/cpu.h
+++ b/sim/m32r/cpu.h
@@ -46,20 +46,29 @@ typedef struct {
 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
   /* control registers */
   USI h_cr[16];
-/* GET_H_CR macro user-written */
-/* SET_H_CR macro user-written */
+#define GET_H_CR(index) m32rbf_h_cr_get_handler (current_cpu, index)
+#define SET_H_CR(index, x) \
+do { \
+m32rbf_h_cr_set_handler (current_cpu, (index), (x));\
+} while (0)
   /* accumulator */
   DI h_accum;
-/* GET_H_ACCUM macro user-written */
-/* SET_H_ACCUM macro user-written */
+#define GET_H_ACCUM() m32rbf_h_accum_get_handler (current_cpu)
+#define SET_H_ACCUM(x) \
+do { \
+m32rbf_h_accum_set_handler (current_cpu, (x));\
+} while (0)
   /* condition bit */
   BI h_cond;
 #define GET_H_COND() CPU (h_cond)
 #define SET_H_COND(x) (CPU (h_cond) = (x))
   /* psw part of psw */
   UQI h_psw;
-/* GET_H_PSW macro user-written */
-/* SET_H_PSW macro user-written */
+#define GET_H_PSW() m32rbf_h_psw_get_handler (current_cpu)
+#define SET_H_PSW(x) \
+do { \
+m32rbf_h_psw_set_handler (current_cpu, (x));\
+} while (0)
   /* backup psw */
   UQI h_bpsw;
 #define GET_H_BPSW() CPU (h_bpsw)
@@ -85,8 +94,6 @@ USI m32rbf_h_cr_get (SIM_CPU *, UINT);
 void m32rbf_h_cr_set (SIM_CPU *, UINT, USI);
 DI m32rbf_h_accum_get (SIM_CPU *);
 void m32rbf_h_accum_set (SIM_CPU *, DI);
-DI m32rbf_h_accums_get (SIM_CPU *, UINT);
-void m32rbf_h_accums_set (SIM_CPU *, UINT, DI);
 BI m32rbf_h_cond_get (SIM_CPU *);
 void m32rbf_h_cond_set (SIM_CPU *, BI);
 UQI m32rbf_h_psw_get (SIM_CPU *);
diff --git a/sim/m32r/decode.c b/sim/m32r/decode.c
index 63913af..8bac0ef 100644
--- a/sim/m32r/decode.c
+++ b/sim/m32r/decode.c
@@ -46,6 +46,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #define FAST(fn)
 #endif
 
+/* The INSN_ prefix is not here and is instead part of the `insn' argument
+   to avoid collisions with header files (e.g. `AND' in ansidecl.h).  */
+#define IDX(insn) CONCAT2 (M32RBF_,insn)
+#define TYPE(insn) CONCAT2 (M32R_,insn)
+
 /* The instruction descriptor array.
    This is computed at runtime.  Space for it is not malloc'd to save a
    teensy bit of cpu in the decoder.  Moving it to malloc space is trivial
@@ -53,11 +58,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
    addition of instructions nor an SMP machine with different cpus).  */
 static IDESC m32rbf_insn_data[M32RBF_INSN_MAX];
 
-/* The INSN_ prefix is not here and is instead part of the `insn' argument
-   to avoid collisions with header files (e.g. `AND' in ansidecl.h).  */
-#define IDX(insn) CONCAT2 (M32RBF_,insn)
-#define TYPE(insn) CONCAT2 (M32R_,insn)
-
 /* Commas between elements are contained in the macros.
    Some of these are conditionally compiled out.  */
 
@@ -175,6 +175,9 @@ static const struct insn_sem m32rbf_insn_sem_invalid =
   VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), FULL (x_invalid) FAST (x_invalid)
 };
 
+#undef FMT
+#undef FULL
+#undef FAST
 #undef IDX
 #undef TYPE
 
@@ -236,50 +239,6 @@ m32rbf_init_idesc_table (SIM_CPU *cpu)
   CPU_IDESC (cpu) = table;
 }
 
-/* Enum declaration for all instruction semantic formats.  */
-typedef enum sfmt {
-  FMT_EMPTY, FMT_ADD, FMT_ADD3, FMT_AND3
- , FMT_OR3, FMT_ADDI, FMT_ADDV, FMT_ADDV3
- , FMT_ADDX, FMT_BC8, FMT_BC24, FMT_BEQ
- , FMT_BEQZ, FMT_BL8, FMT_BL24, FMT_BRA8
- , FMT_BRA24, FMT_CMP, FMT_CMPI, FMT_DIV
- , FMT_JL, FMT_JMP, FMT_LD, FMT_LD_D
- , FMT_LDB, FMT_LDB_D, FMT_LDH, FMT_LDH_D
- , FMT_LD_PLUS, FMT_LD24, FMT_LDI8, FMT_LDI16
- , FMT_LOCK, FMT_MACHI, FMT_MULHI, FMT_MV
- , FMT_MVFACHI, FMT_MVFC, FMT_MVTACHI, FMT_MVTC
- , FMT_NOP, FMT_RAC, FMT_RTE, FMT_SETH
- , FMT_SLL3, FMT_SLLI, FMT_ST, FMT_ST_D
- , FMT_STB, FMT_STB_D, FMT_STH, FMT_STH_D
- , FMT_ST_PLUS, FMT_TRAP, FMT_UNLOCK
-} SFMT;
-
-/* The decoder uses this to record insns and direct extraction handling.  */
-
-typedef struct {
-  const IDESC *idesc;
-#ifdef __GNUC__
-  void *sfmt;
-#else
-  enum sfmt sfmt;
-#endif
-} DECODE_DESC;
-
-/* Macro to go from decode phase to extraction phase.  */
-
-#ifdef __GNUC__
-#define GOTO_EXTRACT(id) goto *(id)->sfmt
-#else
-#define GOTO_EXTRACT(id) goto extract
-#endif
-
-/* The decoder needs a slightly different computed goto switch control.  */
-#ifdef __GNUC__
-#define DECODE_SWITCH(N, X) goto *labels_##N[X];
-#else
-#define DECODE_SWITCH(N, X) switch (X)
-#endif
-
 /* Given an instruction, return a pointer to its IDESC entry.  */
 
 const IDESC *
@@ -287,370 +246,254 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
               CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn,
               ARGBUF *abuf)
 {
-  /* Result of decoder, used by extractor.  */
-  const DECODE_DESC *idecode;
-
-  /* First decode the instruction.  */
+  /* Result of decoder.  */
+  M32RBF_INSN_TYPE itype;
 
   {
-#define I(insn) & m32rbf_insn_data[CONCAT2 (M32RBF_,insn)]
-#ifdef __GNUC__
-#define E(fmt) && case_ex_##fmt
-#else
-#define E(fmt) fmt
-#endif
     CGEN_INSN_INT insn = base_insn;
-    static const DECODE_DESC idecode_invalid = { I (INSN_X_INVALID), E (FMT_EMPTY) };
 
     {
-#ifdef __GNUC__
-      static const void *labels_0[256] = {
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && case_0_28, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && case_0_87, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && case_0_95, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && case_0_112, && case_0_113, && case_0_114, && case_0_115, 
-        && case_0_116, && case_0_117, && case_0_118, && case_0_119, 
-        && case_0_120, && case_0_121, && case_0_122, && case_0_123, 
-        && case_0_124, && case_0_125, && case_0_126, && case_0_127, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && case_0_240, && case_0_241, && case_0_242, && case_0_243, 
-        && case_0_244, && case_0_245, && case_0_246, && case_0_247, 
-        && case_0_248, && case_0_249, && case_0_250, && case_0_251, 
-        && case_0_252, && case_0_253, && case_0_254, && case_0_255, 
-      };
-#endif
-      static const DECODE_DESC insns[256] = {
-        { I (INSN_SUBV), E (FMT_ADDV) }, { I (INSN_SUBX), E (FMT_ADDX) }, 
-        { I (INSN_SUB), E (FMT_ADD) }, { I (INSN_NEG), E (FMT_MV) }, 
-        { I (INSN_CMP), E (FMT_CMP) }, { I (INSN_CMPU), E (FMT_CMP) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_ADDV), E (FMT_ADDV) }, { I (INSN_ADDX), E (FMT_ADDX) }, 
-        { I (INSN_ADD), E (FMT_ADD) }, { I (INSN_NOT), E (FMT_MV) }, 
-        { I (INSN_AND), E (FMT_ADD) }, { I (INSN_XOR), E (FMT_ADD) }, 
-        { I (INSN_OR), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_SRL), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_SRA), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_SLL), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_MUL), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_MV), E (FMT_MV) }, { I (INSN_MVFC), E (FMT_MVFC) }, 
-        { I (INSN_MVTC), E (FMT_MVTC) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { 0 }, { I (INSN_RTE), E (FMT_RTE) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_TRAP), E (FMT_TRAP) }, 
-        { I (INSN_STB), E (FMT_STB) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_STH), E (FMT_STH) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_ST), E (FMT_ST) }, { I (INSN_UNLOCK), E (FMT_UNLOCK) }, 
-        { I (INSN_ST_PLUS), E (FMT_ST_PLUS) }, { I (INSN_ST_MINUS), E (FMT_ST_PLUS) }, 
-        { I (INSN_LDB), E (FMT_LDB) }, { I (INSN_LDUB), E (FMT_LDB) }, 
-        { I (INSN_LDH), E (FMT_LDH) }, { I (INSN_LDUH), E (FMT_LDH) }, 
-        { I (INSN_LD), E (FMT_LD) }, { I (INSN_LOCK), E (FMT_LOCK) }, 
-        { I (INSN_LD_PLUS), E (FMT_LD_PLUS) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_MULHI), E (FMT_MULHI) }, { I (INSN_MULLO), E (FMT_MULHI) }, 
-        { I (INSN_MULWHI), E (FMT_MULHI) }, { I (INSN_MULWLO), E (FMT_MULHI) }, 
-        { I (INSN_MACHI), E (FMT_MACHI) }, { I (INSN_MACLO), E (FMT_MACHI) }, 
-        { I (INSN_MACWHI), E (FMT_MACHI) }, { I (INSN_MACWLO), E (FMT_MACHI) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, 
-        { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, 
-        { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, 
-        { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, 
-        { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, 
-        { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, 
-        { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, 
-        { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, 
-        { I (INSN_SRLI), E (FMT_SLLI) }, { I (INSN_SRLI), E (FMT_SLLI) }, 
-        { I (INSN_SRAI), E (FMT_SLLI) }, { I (INSN_SRAI), E (FMT_SLLI) }, 
-        { I (INSN_SLLI), E (FMT_SLLI) }, { I (INSN_SLLI), E (FMT_SLLI) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { 0 }, 
-        { I (INSN_RACH), E (FMT_RAC) }, { I (INSN_RAC), E (FMT_RAC) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { 0 }, 
-        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
-        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
-        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
-        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
-        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
-        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
-        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
-        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_CMPI), E (FMT_CMPI) }, { I (INSN_CMPUI), E (FMT_CMPI) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_ADDV3), E (FMT_ADDV3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_ADD3), E (FMT_ADD3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_AND3), E (FMT_AND3) }, { I (INSN_XOR3), E (FMT_AND3) }, 
-        { I (INSN_OR3), E (FMT_OR3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_DIV), E (FMT_DIV) }, { I (INSN_DIVU), E (FMT_DIV) }, 
-        { I (INSN_REM), E (FMT_DIV) }, { I (INSN_REMU), E (FMT_DIV) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_SRL3), E (FMT_SLL3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_SRA3), E (FMT_SLL3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_SLL3), E (FMT_SLL3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LDI16), E (FMT_LDI16) }, 
-        { I (INSN_STB_D), E (FMT_STB_D) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_STH_D), E (FMT_STH_D) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_ST_D), E (FMT_ST_D) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_LDB_D), E (FMT_LDB_D) }, { I (INSN_LDUB_D), E (FMT_LDB_D) }, 
-        { I (INSN_LDH_D), E (FMT_LDH_D) }, { I (INSN_LDUH_D), E (FMT_LDH_D) }, 
-        { I (INSN_LD_D), E (FMT_LD_D) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_BEQ), E (FMT_BEQ) }, { I (INSN_BNE), E (FMT_BEQ) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_BEQZ), E (FMT_BEQZ) }, { I (INSN_BNEZ), E (FMT_BEQZ) }, 
-        { I (INSN_BLTZ), E (FMT_BEQZ) }, { I (INSN_BGEZ), E (FMT_BEQZ) }, 
-        { I (INSN_BLEZ), E (FMT_BEQZ) }, { I (INSN_BGTZ), E (FMT_BEQZ) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_SETH), E (FMT_SETH) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, 
-        { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, 
-        { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, 
-        { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, 
-        { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, 
-        { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, 
-        { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, 
-        { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-      };
-      unsigned int val;
-      val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
-      DECODE_SWITCH (0, val)
+      unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
+      switch (val)
+      {
+      case 0 : itype = M32RBF_INSN_SUBV; goto extract_fmt_addv;
+      case 1 : itype = M32RBF_INSN_SUBX; goto extract_fmt_addx;
+      case 2 : itype = M32RBF_INSN_SUB; goto extract_fmt_add;
+      case 3 : itype = M32RBF_INSN_NEG; goto extract_fmt_mv;
+      case 4 : itype = M32RBF_INSN_CMP; goto extract_fmt_cmp;
+      case 5 : itype = M32RBF_INSN_CMPU; goto extract_fmt_cmp;
+      case 8 : itype = M32RBF_INSN_ADDV; goto extract_fmt_addv;
+      case 9 : itype = M32RBF_INSN_ADDX; goto extract_fmt_addx;
+      case 10 : itype = M32RBF_INSN_ADD; goto extract_fmt_add;
+      case 11 : itype = M32RBF_INSN_NOT; goto extract_fmt_mv;
+      case 12 : itype = M32RBF_INSN_AND; goto extract_fmt_add;
+      case 13 : itype = M32RBF_INSN_XOR; goto extract_fmt_add;
+      case 14 : itype = M32RBF_INSN_OR; goto extract_fmt_add;
+      case 16 : itype = M32RBF_INSN_SRL; goto extract_fmt_add;
+      case 18 : itype = M32RBF_INSN_SRA; goto extract_fmt_add;
+      case 20 : itype = M32RBF_INSN_SLL; goto extract_fmt_add;
+      case 22 : itype = M32RBF_INSN_MUL; goto extract_fmt_add;
+      case 24 : itype = M32RBF_INSN_MV; goto extract_fmt_mv;
+      case 25 : itype = M32RBF_INSN_MVFC; goto extract_fmt_mvfc;
+      case 26 : itype = M32RBF_INSN_MVTC; goto extract_fmt_mvtc;
+      case 28 :
         {
-        CASE (0, 28) :
+          unsigned int val = (((insn >> 8) & (15 << 0)));
+          switch (val)
           {
-            static const DECODE_DESC insns[16] = {
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_JL), E (FMT_JL) }, { I (INSN_JMP), E (FMT_JMP) }, 
-            };
-            unsigned int val = (((insn >> 8) & (15 << 0)));
-            idecode = &insns[val];
-            GOTO_EXTRACT (idecode);
+          case 14 : itype = M32RBF_INSN_JL; goto extract_fmt_jl;
+          case 15 : itype = M32RBF_INSN_JMP; goto extract_fmt_jmp;
+          default : itype = M32RBF_INSN_X_INVALID; goto extract_fmt_empty;
           }
-        CASE (0, 87) :
+        }
+      case 29 : itype = M32RBF_INSN_RTE; goto extract_fmt_rte;
+      case 31 : itype = M32RBF_INSN_TRAP; goto extract_fmt_trap;
+      case 32 : itype = M32RBF_INSN_STB; goto extract_fmt_stb;
+      case 34 : itype = M32RBF_INSN_STH; goto extract_fmt_sth;
+      case 36 : itype = M32RBF_INSN_ST; goto extract_fmt_st;
+      case 37 : itype = M32RBF_INSN_UNLOCK; goto extract_fmt_unlock;
+      case 38 : itype = M32RBF_INSN_ST_PLUS; goto extract_fmt_st_plus;
+      case 39 : itype = M32RBF_INSN_ST_MINUS; goto extract_fmt_st_plus;
+      case 40 : itype = M32RBF_INSN_LDB; goto extract_fmt_ldb;
+      case 41 : itype = M32RBF_INSN_LDUB; goto extract_fmt_ldb;
+      case 42 : itype = M32RBF_INSN_LDH; goto extract_fmt_ldh;
+      case 43 : itype = M32RBF_INSN_LDUH; goto extract_fmt_ldh;
+      case 44 : itype = M32RBF_INSN_LD; goto extract_fmt_ld;
+      case 45 : itype = M32RBF_INSN_LOCK; goto extract_fmt_lock;
+      case 46 : itype = M32RBF_INSN_LD_PLUS; goto extract_fmt_ld_plus;
+      case 48 : itype = M32RBF_INSN_MULHI; goto extract_fmt_mulhi;
+      case 49 : itype = M32RBF_INSN_MULLO; goto extract_fmt_mulhi;
+      case 50 : itype = M32RBF_INSN_MULWHI; goto extract_fmt_mulhi;
+      case 51 : itype = M32RBF_INSN_MULWLO; goto extract_fmt_mulhi;
+      case 52 : itype = M32RBF_INSN_MACHI; goto extract_fmt_machi;
+      case 53 : itype = M32RBF_INSN_MACLO; goto extract_fmt_machi;
+      case 54 : itype = M32RBF_INSN_MACWHI; goto extract_fmt_machi;
+      case 55 : itype = M32RBF_INSN_MACWLO; goto extract_fmt_machi;
+      case 64 : /* fall through */
+      case 65 : /* fall through */
+      case 66 : /* fall through */
+      case 67 : /* fall through */
+      case 68 : /* fall through */
+      case 69 : /* fall through */
+      case 70 : /* fall through */
+      case 71 : /* fall through */
+      case 72 : /* fall through */
+      case 73 : /* fall through */
+      case 74 : /* fall through */
+      case 75 : /* fall through */
+      case 76 : /* fall through */
+      case 77 : /* fall through */
+      case 78 : /* fall through */
+      case 79 : itype = M32RBF_INSN_ADDI; goto extract_fmt_addi;
+      case 80 : /* fall through */
+      case 81 : itype = M32RBF_INSN_SRLI; goto extract_fmt_slli;
+      case 82 : /* fall through */
+      case 83 : itype = M32RBF_INSN_SRAI; goto extract_fmt_slli;
+      case 84 : /* fall through */
+      case 85 : itype = M32RBF_INSN_SLLI; goto extract_fmt_slli;
+      case 87 :
+        {
+          unsigned int val = (((insn >> 0) & (15 << 0)));
+          switch (val)
           {
-            static const DECODE_DESC insns[16] = {
-              { I (INSN_MVTACHI), E (FMT_MVTACHI) }, { I (INSN_MVTACLO), E (FMT_MVTACHI) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-            };
-            unsigned int val = (((insn >> 0) & (15 << 0)));
-            idecode = &insns[val];
-            GOTO_EXTRACT (idecode);
+          case 0 : itype = M32RBF_INSN_MVTACHI; goto extract_fmt_mvtachi;
+          case 1 : itype = M32RBF_INSN_MVTACLO; goto extract_fmt_mvtachi;
+          default : itype = M32RBF_INSN_X_INVALID; goto extract_fmt_empty;
           }
-        CASE (0, 95) :
+        }
+      case 88 : itype = M32RBF_INSN_RACH; goto extract_fmt_rac;
+      case 89 : itype = M32RBF_INSN_RAC; goto extract_fmt_rac;
+      case 95 :
+        {
+          unsigned int val = (((insn >> 0) & (15 << 0)));
+          switch (val)
           {
-            static const DECODE_DESC insns[16] = {
-              { I (INSN_MVFACHI), E (FMT_MVFACHI) }, { I (INSN_MVFACLO), E (FMT_MVFACHI) }, 
-              { I (INSN_MVFACMI), E (FMT_MVFACHI) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-            };
-            unsigned int val = (((insn >> 0) & (15 << 0)));
-            idecode = &insns[val];
-            GOTO_EXTRACT (idecode);
+          case 0 : itype = M32RBF_INSN_MVFACHI; goto extract_fmt_mvfachi;
+          case 1 : itype = M32RBF_INSN_MVFACLO; goto extract_fmt_mvfachi;
+          case 2 : itype = M32RBF_INSN_MVFACMI; goto extract_fmt_mvfachi;
+          default : itype = M32RBF_INSN_X_INVALID; goto extract_fmt_empty;
           }
-        CASE (0, 112) :
+        }
+      case 96 : /* fall through */
+      case 97 : /* fall through */
+      case 98 : /* fall through */
+      case 99 : /* fall through */
+      case 100 : /* fall through */
+      case 101 : /* fall through */
+      case 102 : /* fall through */
+      case 103 : /* fall through */
+      case 104 : /* fall through */
+      case 105 : /* fall through */
+      case 106 : /* fall through */
+      case 107 : /* fall through */
+      case 108 : /* fall through */
+      case 109 : /* fall through */
+      case 110 : /* fall through */
+      case 111 : itype = M32RBF_INSN_LDI8; goto extract_fmt_ldi8;
+      case 112 :
+        {
+          unsigned int val = (((insn >> 8) & (15 << 0)));
+          switch (val)
           {
-            static const DECODE_DESC insns[16] = {
-              { I (INSN_NOP), E (FMT_NOP) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_BC8), E (FMT_BC8) }, { I (INSN_BNC8), E (FMT_BC8) }, 
-              { I (INSN_BL8), E (FMT_BL8) }, { I (INSN_BRA8), E (FMT_BRA8) }, 
-            };
-            unsigned int val = (((insn >> 8) & (15 << 0)));
-            idecode = &insns[val];
-            GOTO_EXTRACT (idecode);
+          case 0 : itype = M32RBF_INSN_NOP; goto extract_fmt_nop;
+          case 12 : itype = M32RBF_INSN_BC8; goto extract_fmt_bc8;
+          case 13 : itype = M32RBF_INSN_BNC8; goto extract_fmt_bc8;
+          case 14 : itype = M32RBF_INSN_BL8; goto extract_fmt_bl8;
+          case 15 : itype = M32RBF_INSN_BRA8; goto extract_fmt_bra8;
+          default : itype = M32RBF_INSN_X_INVALID; goto extract_fmt_empty;
           }
-        CASE (0, 113) : /* fall through */
-        CASE (0, 114) : /* fall through */
-        CASE (0, 115) : /* fall through */
-        CASE (0, 116) : /* fall through */
-        CASE (0, 117) : /* fall through */
-        CASE (0, 118) : /* fall through */
-        CASE (0, 119) : /* fall through */
-        CASE (0, 120) : /* fall through */
-        CASE (0, 121) : /* fall through */
-        CASE (0, 122) : /* fall through */
-        CASE (0, 123) : /* fall through */
-        CASE (0, 124) : /* fall through */
-        CASE (0, 125) : /* fall through */
-        CASE (0, 126) : /* fall through */
-        CASE (0, 127) :
+        }
+      case 113 : /* fall through */
+      case 114 : /* fall through */
+      case 115 : /* fall through */
+      case 116 : /* fall through */
+      case 117 : /* fall through */
+      case 118 : /* fall through */
+      case 119 : /* fall through */
+      case 120 : /* fall through */
+      case 121 : /* fall through */
+      case 122 : /* fall through */
+      case 123 : /* fall through */
+      case 124 : /* fall through */
+      case 125 : /* fall through */
+      case 126 : /* fall through */
+      case 127 :
+        {
+          unsigned int val = (((insn >> 8) & (15 << 0)));
+          switch (val)
           {
-            static const DECODE_DESC insns[16] = {
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_BC8), E (FMT_BC8) }, { I (INSN_BNC8), E (FMT_BC8) }, 
-              { I (INSN_BL8), E (FMT_BL8) }, { I (INSN_BRA8), E (FMT_BRA8) }, 
-            };
-            unsigned int val = (((insn >> 8) & (15 << 0)));
-            idecode = &insns[val];
-            GOTO_EXTRACT (idecode);
+          case 12 : itype = M32RBF_INSN_BC8; goto extract_fmt_bc8;
+          case 13 : itype = M32RBF_INSN_BNC8; goto extract_fmt_bc8;
+          case 14 : itype = M32RBF_INSN_BL8; goto extract_fmt_bl8;
+          case 15 : itype = M32RBF_INSN_BRA8; goto extract_fmt_bra8;
+          default : itype = M32RBF_INSN_X_INVALID; goto extract_fmt_empty;
           }
-        CASE (0, 240) : /* fall through */
-        CASE (0, 241) : /* fall through */
-        CASE (0, 242) : /* fall through */
-        CASE (0, 243) : /* fall through */
-        CASE (0, 244) : /* fall through */
-        CASE (0, 245) : /* fall through */
-        CASE (0, 246) : /* fall through */
-        CASE (0, 247) : /* fall through */
-        CASE (0, 248) : /* fall through */
-        CASE (0, 249) : /* fall through */
-        CASE (0, 250) : /* fall through */
-        CASE (0, 251) : /* fall through */
-        CASE (0, 252) : /* fall through */
-        CASE (0, 253) : /* fall through */
-        CASE (0, 254) : /* fall through */
-        CASE (0, 255) :
+        }
+      case 132 : itype = M32RBF_INSN_CMPI; goto extract_fmt_cmpi;
+      case 133 : itype = M32RBF_INSN_CMPUI; goto extract_fmt_cmpi;
+      case 136 : itype = M32RBF_INSN_ADDV3; goto extract_fmt_addv3;
+      case 138 : itype = M32RBF_INSN_ADD3; goto extract_fmt_add3;
+      case 140 : itype = M32RBF_INSN_AND3; goto extract_fmt_and3;
+      case 141 : itype = M32RBF_INSN_XOR3; goto extract_fmt_and3;
+      case 142 : itype = M32RBF_INSN_OR3; goto extract_fmt_or3;
+      case 144 : itype = M32RBF_INSN_DIV; goto extract_fmt_div;
+      case 145 : itype = M32RBF_INSN_DIVU; goto extract_fmt_div;
+      case 146 : itype = M32RBF_INSN_REM; goto extract_fmt_div;
+      case 147 : itype = M32RBF_INSN_REMU; goto extract_fmt_div;
+      case 152 : itype = M32RBF_INSN_SRL3; goto extract_fmt_sll3;
+      case 154 : itype = M32RBF_INSN_SRA3; goto extract_fmt_sll3;
+      case 156 : itype = M32RBF_INSN_SLL3; goto extract_fmt_sll3;
+      case 159 : itype = M32RBF_INSN_LDI16; goto extract_fmt_ldi16;
+      case 160 : itype = M32RBF_INSN_STB_D; goto extract_fmt_stb_d;
+      case 162 : itype = M32RBF_INSN_STH_D; goto extract_fmt_sth_d;
+      case 164 : itype = M32RBF_INSN_ST_D; goto extract_fmt_st_d;
+      case 168 : itype = M32RBF_INSN_LDB_D; goto extract_fmt_ldb_d;
+      case 169 : itype = M32RBF_INSN_LDUB_D; goto extract_fmt_ldb_d;
+      case 170 : itype = M32RBF_INSN_LDH_D; goto extract_fmt_ldh_d;
+      case 171 : itype = M32RBF_INSN_LDUH_D; goto extract_fmt_ldh_d;
+      case 172 : itype = M32RBF_INSN_LD_D; goto extract_fmt_ld_d;
+      case 176 : itype = M32RBF_INSN_BEQ; goto extract_fmt_beq;
+      case 177 : itype = M32RBF_INSN_BNE; goto extract_fmt_beq;
+      case 184 : itype = M32RBF_INSN_BEQZ; goto extract_fmt_beqz;
+      case 185 : itype = M32RBF_INSN_BNEZ; goto extract_fmt_beqz;
+      case 186 : itype = M32RBF_INSN_BLTZ; goto extract_fmt_beqz;
+      case 187 : itype = M32RBF_INSN_BGEZ; goto extract_fmt_beqz;
+      case 188 : itype = M32RBF_INSN_BLEZ; goto extract_fmt_beqz;
+      case 189 : itype = M32RBF_INSN_BGTZ; goto extract_fmt_beqz;
+      case 220 : itype = M32RBF_INSN_SETH; goto extract_fmt_seth;
+      case 224 : /* fall through */
+      case 225 : /* fall through */
+      case 226 : /* fall through */
+      case 227 : /* fall through */
+      case 228 : /* fall through */
+      case 229 : /* fall through */
+      case 230 : /* fall through */
+      case 231 : /* fall through */
+      case 232 : /* fall through */
+      case 233 : /* fall through */
+      case 234 : /* fall through */
+      case 235 : /* fall through */
+      case 236 : /* fall through */
+      case 237 : /* fall through */
+      case 238 : /* fall through */
+      case 239 : itype = M32RBF_INSN_LD24; goto extract_fmt_ld24;
+      case 240 : /* fall through */
+      case 241 : /* fall through */
+      case 242 : /* fall through */
+      case 243 : /* fall through */
+      case 244 : /* fall through */
+      case 245 : /* fall through */
+      case 246 : /* fall through */
+      case 247 : /* fall through */
+      case 248 : /* fall through */
+      case 249 : /* fall through */
+      case 250 : /* fall through */
+      case 251 : /* fall through */
+      case 252 : /* fall through */
+      case 253 : /* fall through */
+      case 254 : /* fall through */
+      case 255 :
+        {
+          unsigned int val = (((insn >> 8) & (15 << 0)));
+          switch (val)
           {
-            static const DECODE_DESC insns[16] = {
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_BC24), E (FMT_BC24) }, { I (INSN_BNC24), E (FMT_BC24) }, 
-              { I (INSN_BL24), E (FMT_BL24) }, { I (INSN_BRA24), E (FMT_BRA24) }, 
-            };
-            unsigned int val = (((insn >> 8) & (15 << 0)));
-            idecode = &insns[val];
-            GOTO_EXTRACT (idecode);
+          case 12 : itype = M32RBF_INSN_BC24; goto extract_fmt_bc24;
+          case 13 : itype = M32RBF_INSN_BNC24; goto extract_fmt_bc24;
+          case 14 : itype = M32RBF_INSN_BL24; goto extract_fmt_bl24;
+          case 15 : itype = M32RBF_INSN_BRA24; goto extract_fmt_bra24;
+          default : itype = M32RBF_INSN_X_INVALID; goto extract_fmt_empty;
           }
-        DEFAULT (0) :
-          idecode = &insns[val];
-          GOTO_EXTRACT (idecode);
         }
-      ENDSWITCH (0)
+      default : itype = M32RBF_INSN_X_INVALID; goto extract_fmt_empty;
+      }
     }
-#undef I
-#undef E
   }
 
   /* The instruction has been decoded, now extract the fields.  */
 
- extract:
-  {
-#ifndef __GNUC__
-    switch (idecode->sfmt)
-#endif
-      {
-
-  CASE (ex, FMT_EMPTY) :
+ extract_fmt_empty:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_empty.f
   EXTRACT_IFMT_EMPTY_VARS /* */
@@ -661,11 +504,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_empty", (char *) 0));
 
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_ADD) :
+ extract_fmt_add:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_add.f
   EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
@@ -687,11 +531,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_ADD3) :
+ extract_fmt_add3:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_add3.f
   EXTRACT_IFMT_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
@@ -713,11 +558,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_AND3) :
+ extract_fmt_and3:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_and3.f
   EXTRACT_IFMT_AND3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
@@ -739,11 +585,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_OR3) :
+ extract_fmt_or3:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_or3.f
   EXTRACT_IFMT_OR3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
@@ -765,11 +612,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_ADDI) :
+ extract_fmt_addi:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_addi.f
   EXTRACT_IFMT_ADDI_VARS /* f-op1 f-r1 f-simm8 */
@@ -790,11 +638,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_ADDV) :
+ extract_fmt_addv:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_addv.f
   EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
@@ -816,11 +665,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_ADDV3) :
+ extract_fmt_addv3:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_addv3.f
   EXTRACT_IFMT_ADDV3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
@@ -842,11 +692,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_ADDX) :
+ extract_fmt_addx:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_addx.f
   EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
@@ -868,11 +719,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_BC8) :
+ extract_fmt_bc8:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
   EXTRACT_IFMT_BC8_VARS /* f-op1 f-r1 f-disp8 */
@@ -891,11 +743,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_BC24) :
+ extract_fmt_bc24:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
   EXTRACT_IFMT_BC24_VARS /* f-op1 f-r1 f-disp24 */
@@ -914,11 +767,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_BEQ) :
+ extract_fmt_beq:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.cti.fields.fmt_beq.f
   EXTRACT_IFMT_BEQ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
@@ -941,11 +795,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_BEQZ) :
+ extract_fmt_beqz:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
   EXTRACT_IFMT_BEQZ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
@@ -966,11 +821,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_BL8) :
+ extract_fmt_bl8:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.cti.fields.fmt_bl8.f
   EXTRACT_IFMT_BC8_VARS /* f-op1 f-r1 f-disp8 */
@@ -990,11 +846,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_BL24) :
+ extract_fmt_bl24:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.cti.fields.fmt_bl24.f
   EXTRACT_IFMT_BC24_VARS /* f-op1 f-r1 f-disp24 */
@@ -1014,11 +871,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_BRA8) :
+ extract_fmt_bra8:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.cti.fields.fmt_bra8.f
   EXTRACT_IFMT_BC8_VARS /* f-op1 f-r1 f-disp8 */
@@ -1037,11 +895,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_BRA24) :
+ extract_fmt_bra24:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.cti.fields.fmt_bra24.f
   EXTRACT_IFMT_BC24_VARS /* f-op1 f-r1 f-disp24 */
@@ -1060,11 +919,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_CMP) :
+ extract_fmt_cmp:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_cmp.f
   EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
@@ -1085,11 +945,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_CMPI) :
+ extract_fmt_cmpi:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_cmpi.f
   EXTRACT_IFMT_CMPI_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
@@ -1109,11 +970,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_DIV) :
+ extract_fmt_div:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_div.f
   EXTRACT_IFMT_DIV_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
@@ -1135,11 +997,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_JL) :
+ extract_fmt_jl:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.cti.fields.fmt_jl.f
   EXTRACT_IFMT_JL_VARS /* f-op1 f-r1 f-op2 f-r2 */
@@ -1160,11 +1023,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_JMP) :
+ extract_fmt_jmp:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
   EXTRACT_IFMT_JL_VARS /* f-op1 f-r1 f-op2 f-r2 */
@@ -1184,11 +1048,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_LD) :
+ extract_fmt_ld:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_ld.f
   EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
@@ -1209,11 +1074,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_LD_D) :
+ extract_fmt_ld_d:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_ld_d.f
   EXTRACT_IFMT_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
@@ -1235,11 +1101,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_LDB) :
+ extract_fmt_ldb:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_ldb.f
   EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
@@ -1260,11 +1127,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_LDB_D) :
+ extract_fmt_ldb_d:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_ldb_d.f
   EXTRACT_IFMT_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
@@ -1286,11 +1154,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_LDH) :
+ extract_fmt_ldh:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_ldh.f
   EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
@@ -1311,11 +1180,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_LDH_D) :
+ extract_fmt_ldh_d:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_ldh_d.f
   EXTRACT_IFMT_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
@@ -1337,11 +1207,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_LD_PLUS) :
+ extract_fmt_ld_plus:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_ld_plus.f
   EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
@@ -1363,11 +1234,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_LD24) :
+ extract_fmt_ld24:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_ld24.f
   EXTRACT_IFMT_LD24_VARS /* f-op1 f-r1 f-uimm24 */
@@ -1387,11 +1259,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_LDI8) :
+ extract_fmt_ldi8:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_ldi8.f
   EXTRACT_IFMT_ADDI_VARS /* f-op1 f-r1 f-simm8 */
@@ -1411,11 +1284,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_LDI16) :
+ extract_fmt_ldi16:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_ldi16.f
   EXTRACT_IFMT_LDI16_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
@@ -1435,11 +1309,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_LOCK) :
+ extract_fmt_lock:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_lock.f
   EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
@@ -1460,11 +1335,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_MACHI) :
+ extract_fmt_machi:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_machi.f
   EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
@@ -1485,11 +1361,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_MULHI) :
+ extract_fmt_mulhi:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_mulhi.f
   EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
@@ -1510,11 +1387,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_MV) :
+ extract_fmt_mv:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_mv.f
   EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
@@ -1535,11 +1413,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_MVFACHI) :
+ extract_fmt_mvfachi:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_mvfachi.f
   EXTRACT_IFMT_MVFACHI_VARS /* f-op1 f-r1 f-op2 f-r2 */
@@ -1558,11 +1437,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_MVFC) :
+ extract_fmt_mvfc:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_mvfc.f
   EXTRACT_IFMT_MVFC_VARS /* f-op1 f-r1 f-op2 f-r2 */
@@ -1582,11 +1462,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_MVTACHI) :
+ extract_fmt_mvtachi:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_mvtachi.f
   EXTRACT_IFMT_MVTACHI_VARS /* f-op1 f-r1 f-op2 f-r2 */
@@ -1605,11 +1486,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_MVTC) :
+ extract_fmt_mvtc:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_mvtc.f
   EXTRACT_IFMT_MVTC_VARS /* f-op1 f-r1 f-op2 f-r2 */
@@ -1629,11 +1511,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_NOP) :
+ extract_fmt_nop:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_nop.f
   EXTRACT_IFMT_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */
@@ -1644,11 +1527,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_nop", (char *) 0));
 
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_RAC) :
+ extract_fmt_rac:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_rac.f
   EXTRACT_IFMT_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */
@@ -1659,11 +1543,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_rac", (char *) 0));
 
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_RTE) :
+ extract_fmt_rte:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.cti.fields.fmt_rte.f
   EXTRACT_IFMT_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */
@@ -1681,11 +1566,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_SETH) :
+ extract_fmt_seth:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_seth.f
   EXTRACT_IFMT_SETH_VARS /* f-op1 f-r1 f-op2 f-r2 f-hi16 */
@@ -1705,11 +1591,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_SLL3) :
+ extract_fmt_sll3:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_sll3.f
   EXTRACT_IFMT_ADDV3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
@@ -1731,11 +1618,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_SLLI) :
+ extract_fmt_slli:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_slli.f
   EXTRACT_IFMT_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */
@@ -1756,11 +1644,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_ST) :
+ extract_fmt_st:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_st.f
   EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
@@ -1781,11 +1670,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_ST_D) :
+ extract_fmt_st_d:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_st_d.f
   EXTRACT_IFMT_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
@@ -1807,11 +1697,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_STB) :
+ extract_fmt_stb:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_stb.f
   EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
@@ -1832,11 +1723,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_STB_D) :
+ extract_fmt_stb_d:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_stb_d.f
   EXTRACT_IFMT_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
@@ -1858,11 +1750,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_STH) :
+ extract_fmt_sth:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_sth.f
   EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
@@ -1883,11 +1776,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_STH_D) :
+ extract_fmt_sth_d:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_sth_d.f
   EXTRACT_IFMT_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
@@ -1909,11 +1803,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_ST_PLUS) :
+ extract_fmt_st_plus:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_st_plus.f
   EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
@@ -1935,11 +1830,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_TRAP) :
+ extract_fmt_trap:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.cti.fields.fmt_trap.f
   EXTRACT_IFMT_TRAP_VARS /* f-op1 f-r1 f-op2 f-uimm4 */
@@ -1958,11 +1854,12 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
+    return idesc;
   }
 
-  CASE (ex, FMT_UNLOCK) :
+ extract_fmt_unlock:
   {
+    const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_unlock.f
   EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
@@ -1983,14 +1880,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     }
 #endif
 #undef FLD
-  BREAK (ex);
-  }
-
-
-      }
-    ENDSWITCH (ex)
-
+    return idesc;
   }
 
-  return idecode->idesc;
 }
diff --git a/sim/m32r/devices.c b/sim/m32r/devices.c
index d706869..032c8e7 100644
--- a/sim/m32r/devices.c
+++ b/sim/m32r/devices.c
@@ -32,10 +32,8 @@ device m32r_devices;
 int
 device_io_read_buffer (device *me, void *source, int space,
 		       address_word addr, unsigned nr_bytes,
-		       SIM_CPU *cpu, sim_cia cia)
+		       SIM_DESC sd, SIM_CPU *cpu, sim_cia cia)
 {
-  SIM_DESC sd = CPU_STATE (cpu);
-
   if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
     return nr_bytes;
 
@@ -70,10 +68,8 @@ device_io_read_buffer (device *me, void *source, int space,
 int
 device_io_write_buffer (device *me, const void *source, int space,
 			address_word addr, unsigned nr_bytes,
-			SIM_CPU *cpu, sim_cia cia)
+			SIM_DESC sd, SIM_CPU *cpu, sim_cia cia)
 {
-  SIM_DESC sd = CPU_STATE (cpu);
-
 #if WITH_SCACHE
   /* MSPR support is deprecated but is kept in for upward compatibility
      with existing overlay support.  */
@@ -105,4 +101,7 @@ device_io_write_buffer (device *me, const void *source, int space,
   return nr_bytes;
 }
 
-void device_error () {}
+void
+device_error (device *me, char *message, ...)
+{
+}
diff --git a/sim/m32r/m32r-sim.h b/sim/m32r/m32r-sim.h
index 1dd1878..d0fae5e 100644
--- a/sim/m32r/m32r-sim.h
+++ b/sim/m32r/m32r-sim.h
@@ -41,26 +41,19 @@ extern int m32r_decode_gdb_ctrl_regnum (int);
    FIXME: Eventually move to cgen.  */
 #define GET_H_SM() ((CPU (h_psw) & 0x80) != 0)
 
+extern SI a_m32r_h_gr_get (SIM_CPU *, UINT);
+extern void a_m32r_h_gr_set (SIM_CPU *, UINT, SI);
+extern USI a_m32r_h_cr_get (SIM_CPU *, UINT);
+extern void a_m32r_h_cr_set (SIM_CPU *, UINT, USI);
+
 extern USI m32rbf_h_cr_get_handler (SIM_CPU *, UINT);
 extern void m32rbf_h_cr_set_handler (SIM_CPU *, UINT, USI);
-#define GET_H_CR(regno) \
-  XCONCAT2 (WANT_CPU,_h_cr_get_handler) (current_cpu, (regno))
-#define SET_H_CR(regno, val) \
-  XCONCAT2 (WANT_CPU,_h_cr_set_handler) (current_cpu, (regno), (val))
 
 extern UQI m32rbf_h_psw_get_handler (SIM_CPU *);
 extern void m32rbf_h_psw_set_handler (SIM_CPU *, UQI);
-#define GET_H_PSW() \
-  XCONCAT2 (WANT_CPU,_h_psw_get_handler) (current_cpu)
-#define SET_H_PSW(val) \
-  XCONCAT2 (WANT_CPU,_h_psw_set_handler) (current_cpu, (val))
 
 extern DI m32rbf_h_accum_get_handler (SIM_CPU *);
 extern void m32rbf_h_accum_set_handler (SIM_CPU *, DI);
-#define GET_H_ACCUM() \
-  XCONCAT2 (WANT_CPU,_h_accum_get_handler) (current_cpu)
-#define SET_H_ACCUM(val) \
-  XCONCAT2 (WANT_CPU,_h_accum_set_handler) (current_cpu, (val))
 
 
 /* Misc. profile data.  */
@@ -189,7 +182,7 @@ do { \
 
 /* Start address and length of all device support.  */
 #define M32R_DEVICE_ADDR	0xff000000
-#define M32R_DEVICE_LEN		0x00ffffff
+#define M32R_DEVICE_LEN		0x01000000
 
 /* sim_core_attach device argument.  */
 extern device m32r_devices;
diff --git a/sim/m32r/m32r.c b/sim/m32r/m32r.c
index 13e71e6..3e5e4aa 100644
--- a/sim/m32r/m32r.c
+++ b/sim/m32r/m32r.c
@@ -48,6 +48,8 @@ m32r_decode_gdb_ctrl_regnum (int gdb_regnum)
 int
 m32rbf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
 {
+  int mach = MACH_NUM (CPU_MACH (current_cpu));
+
   if (rn < 16)
     SETTWI (buf, a_m32r_h_gr_get (current_cpu, rn));
   else
@@ -64,13 +66,22 @@ m32rbf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len
 				      m32r_decode_gdb_ctrl_regnum (rn)));
 	break;
       case PC_REGNUM :
-	SETTWI (buf, a_m32r_h_pc_get (current_cpu));
+	if (mach == MACH_M32R)
+	  SETTWI (buf, m32rbf_h_pc_get (current_cpu));
+	else
+	  SETTWI (buf, m32rxf_h_pc_get (current_cpu));
 	break;
       case ACCL_REGNUM :
-	SETTWI (buf, GETLODI (a_m32r_h_accum_get (current_cpu)));
+	if (mach == MACH_M32R)
+	  SETTWI (buf, GETLODI (m32rbf_h_accum_get (current_cpu)));
+	else
+	  SETTWI (buf, GETLODI (m32rxf_h_accum_get (current_cpu)));
 	break;
       case ACCH_REGNUM :
-	SETTWI (buf, GETHIDI (a_m32r_h_accum_get (current_cpu)));
+	if (mach == MACH_M32R)
+	  SETTWI (buf, GETHIDI (m32rbf_h_accum_get (current_cpu)));
+	else
+	  SETTWI (buf, GETHIDI (m32rxf_h_accum_get (current_cpu)));
 	break;
       default :
 	return 0;
@@ -84,6 +95,8 @@ m32rbf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len
 int
 m32rbf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
 {
+  int mach = MACH_NUM (CPU_MACH (current_cpu));
+
   if (rn < 16)
     a_m32r_h_gr_set (current_cpu, rn, GETTWI (buf));
   else
@@ -101,20 +114,37 @@ m32rbf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len
 			 GETTWI (buf));
 	break;
       case PC_REGNUM :
-	a_m32r_h_pc_set (current_cpu, GETTWI (buf));
+	if (mach == MACH_M32R)
+	  m32rbf_h_pc_set (current_cpu, GETTWI (buf));
+	else
+	  m32rxf_h_pc_set (current_cpu, GETTWI (buf));
 	break;
       case ACCL_REGNUM :
 	{
-	  DI val = a_m32r_h_accum_get (current_cpu);
+	  DI val;
+	  if (mach == MACH_M32R)
+	    val = m32rbf_h_accum_get (current_cpu);
+	  else
+	    val = m32rxf_h_accum_get (current_cpu);
 	  SETLODI (val, GETTWI (buf));
-	  a_m32r_h_accum_set (current_cpu, val);
+	  if (mach == MACH_M32R)
+	    m32rbf_h_accum_set (current_cpu, val);
+	  else
+	    m32rxf_h_accum_set (current_cpu, val);
 	  break;
 	}
       case ACCH_REGNUM :
 	{
-	  DI val = a_m32r_h_accum_get (current_cpu);
+	  DI val;
+	  if (mach == MACH_M32R)
+	    val = m32rbf_h_accum_get (current_cpu);
+	  else
+	    val = m32rxf_h_accum_get (current_cpu);
 	  SETHIDI (val, GETTWI (buf));
-	  a_m32r_h_accum_set (current_cpu, val);
+	  if (mach == MACH_M32R)
+	    m32rbf_h_accum_set (current_cpu, val);
+	  else
+	    m32rxf_h_accum_set (current_cpu, val);
 	  break;
 	}
       default :
@@ -124,6 +154,84 @@ m32rbf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len
   return -1; /*FIXME*/
 }
 
+/* Cover fns for mach independent register accesses.  */
+
+SI
+a_m32r_h_gr_get (SIM_CPU *current_cpu, UINT regno)
+{
+  switch (MACH_NUM (CPU_MACH (current_cpu)))
+    {
+#ifdef HAVE_CPU_M32RBF
+    case MACH_M32R : 
+      return m32rbf_h_gr_get (current_cpu, regno);
+#endif
+#ifdef HAVE_CPU_M32RXF
+    case MACH_M32RX : 
+      return m32rxf_h_gr_get (current_cpu, regno);
+#endif
+    default :
+      abort ();
+    }
+}
+
+void
+a_m32r_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+  switch (MACH_NUM (CPU_MACH (current_cpu)))
+    {
+#ifdef HAVE_CPU_M32RBF
+    case MACH_M32R : 
+      m32rbf_h_gr_set (current_cpu, regno, newval);
+      break;
+#endif
+#ifdef HAVE_CPU_M32RXF
+    case MACH_M32RX : 
+      m32rxf_h_gr_set (current_cpu, regno, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
+USI
+a_m32r_h_cr_get (SIM_CPU *current_cpu, UINT regno)
+{
+  switch (MACH_NUM (CPU_MACH (current_cpu)))
+    {
+#ifdef HAVE_CPU_M32RBF
+    case MACH_M32R : 
+      return m32rbf_h_cr_get (current_cpu, regno);
+#endif
+#ifdef HAVE_CPU_M32RXF
+    case MACH_M32RX : 
+      return m32rxf_h_cr_get (current_cpu, regno);
+#endif
+    default :
+      abort ();
+    }
+}
+
+void
+a_m32r_h_cr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
+{
+  switch (MACH_NUM (CPU_MACH (current_cpu)))
+    {
+#ifdef HAVE_CPU_M32RBF
+    case MACH_M32R : 
+      m32rbf_h_cr_set (current_cpu, regno, newval);
+      break;
+#endif
+#ifdef HAVE_CPU_M32RXF
+    case MACH_M32RX : 
+      m32rxf_h_cr_set (current_cpu, regno, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
 USI
 m32rbf_h_cr_get_handler (SIM_CPU *current_cpu, UINT cr)
 {
diff --git a/sim/m32r/model.c b/sim/m32r/model.c
index 8e0454e..e82881e 100644
--- a/sim/m32r/model.c
+++ b/sim/m32r/model.c
@@ -4160,7 +4160,7 @@ m32r_init_cpu (SIM_CPU *cpu)
 
 const MACH m32r_mach =
 {
-  "m32r", "m32r",
+  "m32r", "m32r", MACH_M32R,
   32, 32, & m32r_models[0], & m32rbf_imp_properties,
   m32r_init_cpu,
   m32rbf_prepare_run
diff --git a/sim/m32r/sem-switch.c b/sim/m32r/sem-switch.c
index b729074..673b836 100644
--- a/sim/m32r/sem-switch.c
+++ b/sim/m32r/sem-switch.c
@@ -508,8 +508,8 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
-do {
-  BI temp1;SI temp0;
+{
+  SI temp0;BI temp1;
   temp0 = ADDSI (* FLD (i_dr), * FLD (i_sr));
   temp1 = ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0);
   {
@@ -522,7 +522,7 @@ do {
     CPU (h_cond) = opval;
     TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
   }
-} while (0);
+}
 
 #undef FLD
 }
@@ -537,8 +537,8 @@ do {
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
-do {
-  BI temp1;SI temp0;
+{
+  SI temp0;BI temp1;
   temp0 = ADDSI (* FLD (i_sr), FLD (f_simm16));
   temp1 = ADDOFSI (* FLD (i_sr), FLD (f_simm16), 0);
   {
@@ -551,7 +551,7 @@ do {
     CPU (h_cond) = opval;
     TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
   }
-} while (0);
+}
 
 #undef FLD
 }
@@ -566,8 +566,8 @@ do {
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
-do {
-  BI temp1;SI temp0;
+{
+  SI temp0;BI temp1;
   temp0 = ADDCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
   temp1 = ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
   {
@@ -580,7 +580,7 @@ do {
     CPU (h_cond) = opval;
     TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
   }
-} while (0);
+}
 
 #undef FLD
 }
@@ -821,7 +821,7 @@ if (NESI (* FLD (i_src2), 0)) {
   SEM_BRANCH_INIT
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
-do {
+{
   {
     SI opval = ADDSI (ANDSI (pc, -4), 4);
     CPU (h_gr[((UINT) 14)]) = opval;
@@ -832,7 +832,7 @@ do {
     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
   }
-} while (0);
+}
 
   SEM_BRANCH_FINI (vpc);
 #undef FLD
@@ -849,7 +849,7 @@ do {
   SEM_BRANCH_INIT
   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
-do {
+{
   {
     SI opval = ADDSI (pc, 4);
     CPU (h_gr[((UINT) 14)]) = opval;
@@ -860,7 +860,7 @@ do {
     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
   }
-} while (0);
+}
 
   SEM_BRANCH_FINI (vpc);
 #undef FLD
@@ -1162,8 +1162,8 @@ if (NESI (* FLD (i_sr), 0)) {
   SEM_BRANCH_INIT
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
-do {
-  USI temp1;SI temp0;
+{
+  SI temp0;USI temp1;
   temp0 = ADDSI (ANDSI (pc, -4), 4);
   temp1 = ANDSI (* FLD (i_sr), -4);
   {
@@ -1176,7 +1176,7 @@ do {
     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
   }
-} while (0);
+}
 
   SEM_BRANCH_FINI (vpc);
 #undef FLD
@@ -1403,8 +1403,8 @@ do {
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
-do {
-  SI temp1;SI temp0;
+{
+  SI temp0;SI temp1;
   temp0 = GETMEMSI (current_cpu, pc, * FLD (i_sr));
   temp1 = ADDSI (* FLD (i_sr), 4);
   {
@@ -1417,7 +1417,7 @@ do {
     * FLD (i_sr) = opval;
     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
   }
-} while (0);
+}
 
 #undef FLD
 }
@@ -1489,18 +1489,18 @@ do {
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
-do {
+{
   {
     BI opval = 1;
     CPU (h_lock) = opval;
-    TRACE_RESULT (current_cpu, abuf, "lock-0", 'x', opval);
+    TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
   }
   {
     SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
     * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
   }
-} while (0);
+}
 
 #undef FLD
 }
@@ -1891,7 +1891,7 @@ PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
-do {
+{
   DI tmp_tmp1;
   tmp_tmp1 = SLLDI (GET_H_ACCUM (), 1);
   tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768));
@@ -1900,7 +1900,7 @@ do {
     SET_H_ACCUM (opval);
     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
   }
-} while (0);
+}
 
 #undef FLD
 }
@@ -1915,7 +1915,7 @@ do {
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
-do {
+{
   DI tmp_tmp1;
   tmp_tmp1 = ANDDI (GET_H_ACCUM (), MAKEDI (16777215, 0xffffffff));
 if (ANDIF (GEDI (tmp_tmp1, MAKEDI (16383, 0x80000000)), LEDI (tmp_tmp1, MAKEDI (8388607, 0xffffffff)))) {
@@ -1933,7 +1933,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083
     SET_H_ACCUM (opval);
     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
   }
-} while (0);
+}
 
 #undef FLD
 }
@@ -1949,7 +1949,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083
   SEM_BRANCH_INIT
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
-do {
+{
   {
     USI opval = ANDSI (GET_H_CR (((UINT) 6)), -4);
     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
@@ -1963,14 +1963,14 @@ do {
   {
     UQI opval = CPU (h_bpsw);
     SET_H_PSW (opval);
-    TRACE_RESULT (current_cpu, abuf, "psw-0", 'x', opval);
+    TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
   }
   {
     UQI opval = CPU (h_bbpsw);
     CPU (h_bpsw) = opval;
-    TRACE_RESULT (current_cpu, abuf, "bpsw-0", 'x', opval);
+    TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
   }
-} while (0);
+}
 
   SEM_BRANCH_FINI (vpc);
 #undef FLD
@@ -2290,7 +2290,7 @@ do {
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
-do {
+{
   SI tmp_new_src2;
   tmp_new_src2 = ADDSI (* FLD (i_src2), 4);
   {
@@ -2303,7 +2303,7 @@ do {
     * FLD (i_src2) = opval;
     TRACE_RESULT (current_cpu, abuf, "src2", 'x', opval);
   }
-} while (0);
+}
 
 #undef FLD
 }
@@ -2318,7 +2318,7 @@ do {
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
-do {
+{
   SI tmp_new_src2;
   tmp_new_src2 = SUBSI (* FLD (i_src2), 4);
   {
@@ -2331,7 +2331,7 @@ do {
     * FLD (i_src2) = opval;
     TRACE_RESULT (current_cpu, abuf, "src2", 'x', opval);
   }
-} while (0);
+}
 
 #undef FLD
 }
@@ -2365,8 +2365,8 @@ do {
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
-do {
-  BI temp1;SI temp0;
+{
+  SI temp0;BI temp1;
   temp0 = SUBSI (* FLD (i_dr), * FLD (i_sr));
   temp1 = SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0);
   {
@@ -2379,7 +2379,7 @@ do {
     CPU (h_cond) = opval;
     TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
   }
-} while (0);
+}
 
 #undef FLD
 }
@@ -2394,8 +2394,8 @@ do {
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
-do {
-  BI temp1;SI temp0;
+{
+  SI temp0;BI temp1;
   temp0 = SUBCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
   temp1 = SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
   {
@@ -2408,7 +2408,7 @@ do {
     CPU (h_cond) = opval;
     TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
   }
-} while (0);
+}
 
 #undef FLD
 }
@@ -2424,7 +2424,7 @@ do {
   SEM_BRANCH_INIT
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
-do {
+{
   {
     USI opval = GET_H_CR (((UINT) 6));
     SET_H_CR (((UINT) 14), opval);
@@ -2438,24 +2438,24 @@ do {
   {
     UQI opval = CPU (h_bpsw);
     CPU (h_bbpsw) = opval;
-    TRACE_RESULT (current_cpu, abuf, "bbpsw-0", 'x', opval);
+    TRACE_RESULT (current_cpu, abuf, "bbpsw", 'x', opval);
   }
   {
     UQI opval = GET_H_PSW ();
     CPU (h_bpsw) = opval;
-    TRACE_RESULT (current_cpu, abuf, "bpsw-0", 'x', opval);
+    TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
   }
   {
     UQI opval = ANDQI (GET_H_PSW (), 128);
     SET_H_PSW (opval);
-    TRACE_RESULT (current_cpu, abuf, "psw-0", 'x', opval);
+    TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
   }
   {
     SI opval = m32r_trap (current_cpu, pc, FLD (f_uimm4));
     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
   }
-} while (0);
+}
 
   SEM_BRANCH_FINI (vpc);
 #undef FLD
@@ -2471,7 +2471,7 @@ do {
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
-do {
+{
 if (CPU (h_lock)) {
   {
     SI opval = * FLD (i_src1);
@@ -2483,9 +2483,9 @@ if (CPU (h_lock)) {
   {
     BI opval = 0;
     CPU (h_lock) = opval;
-    TRACE_RESULT (current_cpu, abuf, "lock-0", 'x', opval);
+    TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
   }
-} while (0);
+}
 
   abuf->written = written;
 #undef FLD
diff --git a/sim/m32r/sem.c b/sim/m32r/sem.c
index 62fe70c..03b0a6f 100644
--- a/sim/m32r/sem.c
+++ b/sim/m32r/sem.c
@@ -380,8 +380,8 @@ SEM_FN_NAME (m32rbf,addv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   IADDR UNUSED pc = abuf->addr;
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
-do {
-  BI temp1;SI temp0;
+{
+  SI temp0;BI temp1;
   temp0 = ADDSI (* FLD (i_dr), * FLD (i_sr));
   temp1 = ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0);
   {
@@ -394,7 +394,7 @@ do {
     CPU (h_cond) = opval;
     TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
   }
-} while (0);
+}
 
   return vpc;
 #undef FLD
@@ -411,8 +411,8 @@ SEM_FN_NAME (m32rbf,addv3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   IADDR UNUSED pc = abuf->addr;
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
-do {
-  BI temp1;SI temp0;
+{
+  SI temp0;BI temp1;
   temp0 = ADDSI (* FLD (i_sr), FLD (f_simm16));
   temp1 = ADDOFSI (* FLD (i_sr), FLD (f_simm16), 0);
   {
@@ -425,7 +425,7 @@ do {
     CPU (h_cond) = opval;
     TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
   }
-} while (0);
+}
 
   return vpc;
 #undef FLD
@@ -442,8 +442,8 @@ SEM_FN_NAME (m32rbf,addx) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   IADDR UNUSED pc = abuf->addr;
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
-do {
-  BI temp1;SI temp0;
+{
+  SI temp0;BI temp1;
   temp0 = ADDCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
   temp1 = ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
   {
@@ -456,7 +456,7 @@ do {
     CPU (h_cond) = opval;
     TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
   }
-} while (0);
+}
 
   return vpc;
 #undef FLD
@@ -717,7 +717,7 @@ SEM_FN_NAME (m32rbf,bl8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   SEM_BRANCH_INIT
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
-do {
+{
   {
     SI opval = ADDSI (ANDSI (pc, -4), 4);
     CPU (h_gr[((UINT) 14)]) = opval;
@@ -728,7 +728,7 @@ do {
     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
   }
-} while (0);
+}
 
   SEM_BRANCH_FINI (vpc);
   return vpc;
@@ -747,7 +747,7 @@ SEM_FN_NAME (m32rbf,bl24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   SEM_BRANCH_INIT
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 
-do {
+{
   {
     SI opval = ADDSI (pc, 4);
     CPU (h_gr[((UINT) 14)]) = opval;
@@ -758,7 +758,7 @@ do {
     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
   }
-} while (0);
+}
 
   SEM_BRANCH_FINI (vpc);
   return vpc;
@@ -1088,8 +1088,8 @@ SEM_FN_NAME (m32rbf,jl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   SEM_BRANCH_INIT
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
-do {
-  USI temp1;SI temp0;
+{
+  SI temp0;USI temp1;
   temp0 = ADDSI (ANDSI (pc, -4), 4);
   temp1 = ANDSI (* FLD (i_sr), -4);
   {
@@ -1102,7 +1102,7 @@ do {
     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
   }
-} while (0);
+}
 
   SEM_BRANCH_FINI (vpc);
   return vpc;
@@ -1353,8 +1353,8 @@ SEM_FN_NAME (m32rbf,ld_plus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   IADDR UNUSED pc = abuf->addr;
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
-do {
-  SI temp1;SI temp0;
+{
+  SI temp0;SI temp1;
   temp0 = GETMEMSI (current_cpu, pc, * FLD (i_sr));
   temp1 = ADDSI (* FLD (i_sr), 4);
   {
@@ -1367,7 +1367,7 @@ do {
     * FLD (i_sr) = opval;
     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
   }
-} while (0);
+}
 
   return vpc;
 #undef FLD
@@ -1447,18 +1447,18 @@ SEM_FN_NAME (m32rbf,lock) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   IADDR UNUSED pc = abuf->addr;
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
-do {
+{
   {
     BI opval = 1;
     CPU (h_lock) = opval;
-    TRACE_RESULT (current_cpu, abuf, "lock-0", 'x', opval);
+    TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
   }
   {
     SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
     * FLD (i_dr) = opval;
     TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
   }
-} while (0);
+}
 
   return vpc;
 #undef FLD
@@ -1891,7 +1891,7 @@ SEM_FN_NAME (m32rbf,rac) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   IADDR UNUSED pc = abuf->addr;
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
-do {
+{
   DI tmp_tmp1;
   tmp_tmp1 = SLLDI (GET_H_ACCUM (), 1);
   tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768));
@@ -1900,7 +1900,7 @@ do {
     SET_H_ACCUM (opval);
     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
   }
-} while (0);
+}
 
   return vpc;
 #undef FLD
@@ -1917,7 +1917,7 @@ SEM_FN_NAME (m32rbf,rach) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   IADDR UNUSED pc = abuf->addr;
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
-do {
+{
   DI tmp_tmp1;
   tmp_tmp1 = ANDDI (GET_H_ACCUM (), MAKEDI (16777215, 0xffffffff));
 if (ANDIF (GEDI (tmp_tmp1, MAKEDI (16383, 0x80000000)), LEDI (tmp_tmp1, MAKEDI (8388607, 0xffffffff)))) {
@@ -1935,7 +1935,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083
     SET_H_ACCUM (opval);
     TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
   }
-} while (0);
+}
 
   return vpc;
 #undef FLD
@@ -1953,7 +1953,7 @@ SEM_FN_NAME (m32rbf,rte) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   SEM_BRANCH_INIT
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
-do {
+{
   {
     USI opval = ANDSI (GET_H_CR (((UINT) 6)), -4);
     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
@@ -1967,14 +1967,14 @@ do {
   {
     UQI opval = CPU (h_bpsw);
     SET_H_PSW (opval);
-    TRACE_RESULT (current_cpu, abuf, "psw-0", 'x', opval);
+    TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
   }
   {
     UQI opval = CPU (h_bbpsw);
     CPU (h_bpsw) = opval;
-    TRACE_RESULT (current_cpu, abuf, "bpsw-0", 'x', opval);
+    TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
   }
-} while (0);
+}
 
   SEM_BRANCH_FINI (vpc);
   return vpc;
@@ -2328,7 +2328,7 @@ SEM_FN_NAME (m32rbf,st_plus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   IADDR UNUSED pc = abuf->addr;
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
-do {
+{
   SI tmp_new_src2;
   tmp_new_src2 = ADDSI (* FLD (i_src2), 4);
   {
@@ -2341,7 +2341,7 @@ do {
     * FLD (i_src2) = opval;
     TRACE_RESULT (current_cpu, abuf, "src2", 'x', opval);
   }
-} while (0);
+}
 
   return vpc;
 #undef FLD
@@ -2358,7 +2358,7 @@ SEM_FN_NAME (m32rbf,st_minus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   IADDR UNUSED pc = abuf->addr;
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
-do {
+{
   SI tmp_new_src2;
   tmp_new_src2 = SUBSI (* FLD (i_src2), 4);
   {
@@ -2371,7 +2371,7 @@ do {
     * FLD (i_src2) = opval;
     TRACE_RESULT (current_cpu, abuf, "src2", 'x', opval);
   }
-} while (0);
+}
 
   return vpc;
 #undef FLD
@@ -2409,8 +2409,8 @@ SEM_FN_NAME (m32rbf,subv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   IADDR UNUSED pc = abuf->addr;
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
-do {
-  BI temp1;SI temp0;
+{
+  SI temp0;BI temp1;
   temp0 = SUBSI (* FLD (i_dr), * FLD (i_sr));
   temp1 = SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0);
   {
@@ -2423,7 +2423,7 @@ do {
     CPU (h_cond) = opval;
     TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
   }
-} while (0);
+}
 
   return vpc;
 #undef FLD
@@ -2440,8 +2440,8 @@ SEM_FN_NAME (m32rbf,subx) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   IADDR UNUSED pc = abuf->addr;
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
-do {
-  BI temp1;SI temp0;
+{
+  SI temp0;BI temp1;
   temp0 = SUBCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
   temp1 = SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
   {
@@ -2454,7 +2454,7 @@ do {
     CPU (h_cond) = opval;
     TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
   }
-} while (0);
+}
 
   return vpc;
 #undef FLD
@@ -2472,7 +2472,7 @@ SEM_FN_NAME (m32rbf,trap) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   SEM_BRANCH_INIT
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
-do {
+{
   {
     USI opval = GET_H_CR (((UINT) 6));
     SET_H_CR (((UINT) 14), opval);
@@ -2486,24 +2486,24 @@ do {
   {
     UQI opval = CPU (h_bpsw);
     CPU (h_bbpsw) = opval;
-    TRACE_RESULT (current_cpu, abuf, "bbpsw-0", 'x', opval);
+    TRACE_RESULT (current_cpu, abuf, "bbpsw", 'x', opval);
   }
   {
     UQI opval = GET_H_PSW ();
     CPU (h_bpsw) = opval;
-    TRACE_RESULT (current_cpu, abuf, "bpsw-0", 'x', opval);
+    TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
   }
   {
     UQI opval = ANDQI (GET_H_PSW (), 128);
     SET_H_PSW (opval);
-    TRACE_RESULT (current_cpu, abuf, "psw-0", 'x', opval);
+    TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
   }
   {
     SI opval = m32r_trap (current_cpu, pc, FLD (f_uimm4));
     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
   }
-} while (0);
+}
 
   SEM_BRANCH_FINI (vpc);
   return vpc;
@@ -2521,7 +2521,7 @@ SEM_FN_NAME (m32rbf,unlock) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   IADDR UNUSED pc = abuf->addr;
   SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 
-do {
+{
 if (CPU (h_lock)) {
   {
     SI opval = * FLD (i_src1);
@@ -2533,9 +2533,9 @@ if (CPU (h_lock)) {
   {
     BI opval = 0;
     CPU (h_lock) = opval;
-    TRACE_RESULT (current_cpu, abuf, "lock-0", 'x', opval);
+    TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
   }
-} while (0);
+}
 
   abuf->written = written;
   return vpc;
diff --git a/sim/m32r/sim-if.c b/sim/m32r/sim-if.c
index 6116af8..3ef5a31 100644
--- a/sim/m32r/sim-if.c
+++ b/sim/m32r/sim-if.c
@@ -155,8 +155,8 @@ sim_open (kind, callback, abfd, argv)
 
   /* Open a copy of the cpu descriptor table.  */
   {
-    CGEN_CPU_DESC cd = m32r_cgen_cpu_open (STATE_ARCHITECTURE (sd)->mach,
-					   CGEN_ENDIAN_BIG);
+    CGEN_CPU_DESC cd = m32r_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name,
+					     CGEN_ENDIAN_BIG);
     for (i = 0; i < MAX_NR_PROCESSORS; ++i)
       {
 	SIM_CPU *cpu = STATE_CPU (sd, i);
diff --git a/sim/m32r/traps.c b/sim/m32r/traps.c
index c81a862..f3009f3 100644
--- a/sim/m32r/traps.c
+++ b/sim/m32r/traps.c
@@ -59,9 +59,18 @@ m32r_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia,
     {
       a_m32r_h_cr_set (current_cpu, H_CR_BBPC,
 		       a_m32r_h_cr_get (current_cpu, H_CR_BPC));
-      a_m32r_h_bpsw_set (current_cpu, a_m32r_h_psw_get (current_cpu));
-      /* sm not changed */
-      a_m32r_h_psw_set (current_cpu, a_m32r_h_psw_get (current_cpu) & 0x80);
+      if (MACH_NUM (CPU_MACH (current_cpu)) == MACH_M32R)
+	{
+	  m32rbf_h_bpsw_set (current_cpu, m32rbf_h_psw_get (current_cpu));
+	  /* sm not changed */
+	  m32rbf_h_psw_set (current_cpu, m32rbf_h_psw_get (current_cpu) & 0x80);
+	}
+      else
+	{
+	  m32rxf_h_bpsw_set (current_cpu, m32rxf_h_psw_get (current_cpu));
+	  /* sm not changed */
+	  m32rxf_h_psw_set (current_cpu, m32rxf_h_psw_get (current_cpu) & 0x80);
+	}
       a_m32r_h_cr_set (current_cpu, H_CR_BPC, cia);
 
       sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,