Initial creation of sourceware repository

33 files changed, 0 insertions, 33776 deletions

diff --git a/sim/m32r/.Sanitize b/sim/m32r/.Sanitize
deleted file mode 100644
index b6b3fba..0000000
--- a/sim/m32r/.Sanitize
+++ /dev/null
@@ -1,93 +0,0 @@
-# Sanitize.in for sim/m32r
-# $Id$
-
-# Each directory to survive it's way into a release will need a file
-# like this one called "./.Sanitize".  All keyword lines must exist,
-# and must exist in the order specified by this file.  Each directory
-# in the tree will be processed, top down, in the following order.
-
-# Hash started lines like this one are comments and will be deleted
-# before anything else is done.  Blank lines will also be squashed
-# out.
-
-# The lines between the "Do-first:" line and the "Things-to-keep:"
-# line are executed as a /bin/sh shell script before anything else is
-# done in this 
-
-Do-first:
-
-cygnus_files="cpux.c cpux.h decodex.c decodex.h m32rx.c mloopx.in modelx.c semx-switch.c"
-if ( echo $* | grep keep\-cygnus > /dev/null ) ; then
-        keep_these_too="${cygnus_files} ${keep_these_too}"
-else
-        lose_these_too="${cygnus_files} ${lose_these_too}"
-fi
-
-# All files listed between the "Things-to-keep:" line and the
-# "Files-to-sed:" line will be kept.  All other files will be removed.
-# Directories listed in this section will have their own Sanitize
-# called.  Directories not listed will be removed in their entirety
-# with rm -rf.
-
-Things-to-keep:
-
-ChangeLog
-Makefile.in
-README
-TODO
-acconfig.h
-arch.c
-arch.h
-config.in
-configure
-configure.in
-cpu.c
-cpu.h
-cpuall.h
-decode.c
-decode.h
-devices.c
-m32r-sim.h
-m32r.c
-mloop.in
-model.c
-sem-switch.c
-sem.c
-sim-if.c
-sim-main.h
-tconfig.in
-traps.c
-
-Things-to-lose:
-
-Do-last:
-
-cygnus_files="ChangeLog Makefile.in sim-if.c sim-main.h arch.h arch.c cpuall.h cpu.h m32r-sim.h tconfig.in"
-if ( echo $* | grep keep\-cygnus > /dev/null ) ; then
-        for i in $cygnus_files ; do
-                if test ! -d $i && (grep sanitize-cygnus $i > /dev/null) ; then
-                        if [ -n "${verbose}" ] ; then
-                                echo Keeping cygnus stuff in $i
-                        fi
-                fi
-        done
-else
-        for i in $cygnus_files ; do
-                if test ! -d $i && (grep sanitize-cygnus $i > /dev/null) ; then
-                        if [ -n "${verbose}" ] ; then
-                                echo Removing traces of \"cygnus\" from $i...
-                        fi
-                        cp $i new
-                        sed '/start\-sanitize\-cygnus/,/end-\sanitize\-cygnus/d' < $i > new
-                        if [ -n "${safe}" -a ! -f .Recover/$i ] ; then
-                                if [ -n "${verbose}" ] ; then
-                                        echo Caching $i in .Recover...
-                                fi
-                                mv $i .Recover
-                        fi
-                        mv new $i
-                fi
-        done
-fi
-
-# End of file.
diff --git a/sim/m32r/ChangeLog b/sim/m32r/ChangeLog
deleted file mode 100644
index 8fad75f..0000000
--- a/sim/m32r/ChangeLog
+++ /dev/null
@@ -1,1354 +0,0 @@
-1999-02-09  Doug Evans  <devans@casey.cygnus.com>
-
-	* Makefile.in (SIM_EXTRA_DEPS): Add m32r-desc.h, delete cpu-opc.h.
-	(stamp-arch,stamp-cpu): Update FLAGS variable, option syntax changed.
-start-sanitize-cygnus
-	(stamp-xmloop): s/-parallel/-parallel-write/.
-	(stamp-xcpu): Update FLAGS variable, option syntax changed.
-end-sanitize-cygnus
-	* configure.in (sim_link_files,sim_link_links): Delete.
-	* configure: Rebuild.
-	* decode.c,decode.h,model.c,sem-switch.c,sem.c: Rebuild.
-start-sanitize-cygnus
-	* decodex.c,decodex.h,modelx.c,semx-switch.c: Rebuild.
-end-sanitize-cygnus
-	* mloop.in (execute): CGEN_INSN_ATTR renamed to CGEN_INSN_ATTR_VALUE.
-	* sim-if.c (sim_open): m32r_cgen_cpu_open renamed from
-	m32r_cgen_opcode_open.  Set disassembler.
-	(sim_close): m32r_cgen_cpu_open renamed from m32r_cgen_opcode_open.
-	* sim-main.h: Don't include cpu-opc.h,cpu-sim.h. Include
-	m32r-desc.h,m32r-opc.h,m32r-sim.h.
-
-start-sanitize-cygnus
-Thu Feb  4 16:04:26 1999  Doug Evans  <devans@canuck.cygnus.com>
-
-	* cpux.h,decodex.c,modelx.c,semx-switch.c: Regenerate.
-
-end-sanitize-cygnus
-1999-01-27  Doug Evans  <devans@casey.cygnus.com>
-
-	* cpu.h,decode.c,model.c,sem-switch.c,sem.c: Rebuild.
-start-sanitize-cygnus
-	* cpux.h,decodex.c,modelx.c,semx-switch.c: Rebuild.
-end-sanitize-cygnus
-
-1999-01-15  Doug Evans  <devans@casey.cygnus.com>
-
-	* decode.h,model.c: Regenerate.
-start-sanitize-cygnus
-	* decodex.h,modelx.c: Regenerate.
-end-sanitize-cygnus
-
-1999-01-14  Doug Evans  <devans@casey.cygnus.com>
-
-start-sanitize-cygnus
-	* Makefile.in (stamp-arch): Pass FLAGS to cgen.
-end-sanitize-cygnus
-	* arch.c,arch.h,cpuall.h: Regenerate.
-	* cpu.c,cpu.h,decode.c,decode.h,model.c,sem-switch.c,sem.c: Regenerate.
-	* traps.c (sim_engine_invalid_insn): PCADDR->IADDR.
-start-sanitize-cygnus
-	* cpux.c,cpux.h,decodex.c,decodex.h,modelx.c,semx-switch.c: Regenerate.
-end-sanitize-cygnus
-
-1999-01-11  Doug Evans  <devans@casey.cygnus.com>
-
-	* Makefile.in (m32r-clean): rm eng.h.
-	* sim-main.h: Delete inclusion of ansidecl.h.
-	* cpu.h: Regenerate.
-start-sanitize-cygnus
-	* cpux.h: Regenerate.
-end-sanitize-cygnus
-
-1999-01-06  Doug Evans  <devans@casey.cygnus.com>
-
-	* cpu.h: Regenerate.
-start-sanitize-cygnus
-	* cpux.h: Regenerate.
-end-sanitize-cygnus
-
-1999-01-05  Doug Evans  <devans@casey.cygnus.com>
-
-	* Makefile.in (MAIN_INCLUDE_DEPS): Delete.
-	(INCLUDE_DEPS,OPS_INCLUDE_DEPS): Delete.
-	(sim-if.o): Use SIM_MAIN_DEPS.
-	(arch.o,traps.o,devices.o): Ditto.
-	(M32RBF_INCLUDE_DEPS): Use CGEN_MAIN_CPU_DEPS.
-	(m32r.o,mloop.o,cpu.o,decode.o,sem.o,model.o): Simplify dependencies.
-start-sanitize-cygnus
-	(m32rx.o,mloopx.o,cpux.o,decodex.o,semx.o,modelx.o): Ditto.
-end-sanitize-cygnus
-	(stamp-arch): Pass mach=all to cgen-arch.
-	* cpu.c,cpu.h,decode.c,model.c,sem-switch.c,sem.c: Regenerate.
-	* m32r-sim.h (m32rbf_h_cr_[gs]et_handler): Declare.
-	([GS]ET_H_CR): Define.
-	(m32rbf_h_psw_[gs]et_handler): Declare.
-	([GS]ET_H_PSW): Define.
-	(m32rbf_h_accum_[gs]et_handler): Declare.
-	([GS]ET_H_ACCUM): Define.
-start-sanitize-cygnus
-	(m32rxf_h_{cr,psw,accum}_[gs]et_handler): Declare.
-	(m32rxf_h_accums_[gs]et_handler): Declare.
-	([GS]ET_H_ACCUMS): Define.
-end-sanitize-cygnus
-	* sim-if.c (sim_open): Model probing code moved to sim-model.c.
-	* m32r.c (WANT_CPU): Define as m32rbf.
-	(all register access fns): Rename to ..._handler.
-start-sanitize-cygnus
-	* cpux.c,cpux.h,decodex.c,modelx.c,semx.c: Regenerate.
-	* m32rx.c (WANT_CPU): Define as m32rxf.
-	(all register access fns): Rename to ..._handler.
-end-sanitize-cygnus
-
-1998-12-14  Doug Evans  <devans@casey.cygnus.com>
-
-	* configure.in: --enable-cgen-maint support moved to common/aclocal.m4.
-	(SIM_AC_OPTION_ALIGNMENT): Make strict.
-	* configure: Regenerate.
-
-	* sem-switch.c,sem.c,semx-switch.c: Regenerate.
-	* sim-main.h (SIM_ENGINE_HALT_HOOK,SIM_ENGINE_RESTART_HOOK): Define.
-	* traps.c (m32r_core_signal): Handle --environment=operating.
-
-1998-12-09  Doug Evans  <devans@casey.cygnus.com>
-
-	* cpu.h,decode.c,sem-switch.c,sem.c: Regenerate.
-start-sanitize-cygnus
-	* cpux.h,decodex.c,semx-switch.c: Regenerate.
-end-sanitize-cygnus
-
-	* sim-if.c: Include string.h or strings.h if present.
-
-1998-12-04  Doug Evans  <devans@casey.cygnus.com>
-
-	* configure.in: Call SIM_AC_OPTION_INLINE.
-	* configure: Regenerate.
-	* sim-main.h: Protect against multiple inclusion.
-	Don't include cgen-scache.h,cgen-cpu.h,cgen-trace.h,cpuall.h.
-	Done by cgen-sim.h now.
-	* tconfig.in (SIM_HAVE_MODEL): Delete, moved to cgen-types.h.
-	* cpuall.h: Regenerate.
-	* cpu.h,decode.c,sem-switch.c,sem.c: Regenerate.
-	* mloop.in (extract16): Make static inline again.
-	Simplify with call to @cpu@_fill_argbuf,@cpu@_fill_argbuf_tp.
-	(extract32): Ditto.
-	Simplify with call to @cpu@_fill_argbuf,@cpu@_fill_argbuf_tp.
-	(execute): Test ARGBUF_PROFILE_P before profiling.
-	Update calls to TRACE_INSN_INIT,TRACE_INSN_FINI.
-start-sanitize-cygnus
-	* cpux.h,decodex.c,modelx.c,semx-switch.c: Regenerate.
-	* mloopx.in: Rewrite.
-end-sanitize-cygnus
-
-1998-11-22  Doug Evans  <devans@tobor.to.cygnus.com>
-
-	* devices.c (device_io_write_buffer): Fix typo.
-	* sim-if.c (sim_open): Hack in call to dv_sockser_install.
-	* tconfig.in (HAVE_DV_SOCKSER): Add but comment out.
-
-1998-11-18  Doug Evans  <devans@casey.cygnus.com>
-
-	* Makefile.in (M32R_OBJS): Delete extract.o.
-	(extract.o): Delete.
-	(stamp-arch): Depend on $(CGEN_ARCH_SCM).
-	(stamp-cpu): Don't build extract.c.
-	* cpu.c,cpu.h,decode.c,decode.h,sem-switch.c,sem.c: Rebuild.
-	* mloop.in (extract16): Update type of `insn' arg.
-	Delete call to d->extract.
-	(extract32): Ditto.
-start-sanitize-cygnus
-	* Makefile.in (M32RX_OBJS): Delete extractx.o.
-	(extractx.o): Delete.
-	(stamp-xcpu): Don't build extractx.c.
-	* cpux.c,cpux.h,decodex.c,decodex.h,semx-switch.c: Rebuild.
-	* mloopx.in (extractx16): Update type of `insn' arg.
-	Delete call to d->extract.  Delete arg pbb_p.  All callers updated.
-	(extract-simple,full-exec-simple,fast-exec-simple): Delete.
-	(extractx32): Ditto.
-end-sanitize-cygnus
-
-Wed Nov  4 23:55:37 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* sim-main.h: Delete inclusion of config.h, include sim-basics.h
-	before cgen-types.h.
-	* tconfig.in: Guard against multiple inclusion.
-	* cpu.h: Delete decls moved to genmloop.sh.
-start-sanitize-cygnus
-	* cpux.h: Ditto.
-end-sanitize-cygnus
-
-Mon Oct 19 14:13:05 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* sim-main.h: #include cpu-opc.h.
-	* arch.c,arch.h,decode.c,extract.c,model.c,sem.c: Regenerate
-	to get #include cleanup.
-start-sanitize-cygnus
-	* decodex.c,extractx.c,modelx.c: Ditto.
-end-sanitize-cygnus
-
-	* Makefile.in (SIM_EXTRA_DEPS): Replace cgen headers with
-	CGEN_INCLUDE_DEPS.
-	(M32RBF_INCLUDE_DEPS): Define.
-	(m32r .o's): Depend on it.
-	(mloop.c): Update call to genmloop.sh.
-	* cpu.h,cpuall.h: Regenerate.
-	* sim-main.h: Delete inclusion of cpu.h,decode.h, moved to cpuall.h.
-	#include cgen-scache.h,cgen-cpu.h.
-	* tconfig.in (WITH_FOO semantic macros): Delete.
-start-sanitize-cygnus
-	* Makefile.in (M32RXF_INCLUDE_DEPS): Define.
-	(m32rx .o's): Depend on it.
-	(mloopx.c): Update call to genmloop.sh.
-	* cpux.h: Regenerate.
-end-sanitize-cygnus
-
-Fri Oct 16 09:15:29 1998  Doug Evans  <devans@charmed.cygnus.com>
-
-	* sim-if.c (sim_do_command): Handle "sim info reg {bbpsw,bbpc}".
-
-Wed Oct 14 14:49:50 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* Makefile.in (mloop.o): Don't depend on stamp-cpu, depend on
-	explicit files.
-start-sanitize-cygnus
-	(mloopx.o): Ditto for stamp-xcpu.
-end-sanitize-cygnus
-
-Fri Oct  9 16:11:58 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	Add pseudo-basic-block execution support.
-	* Makefile.in (SIM_OBJS): Add sim-reg.o, cgen-run.o, sim-stop.o.
-	(SIM_EXTRA_DEPS): Add include/opcode/cgen.h.
-	(INCLUDE_DEPS): Delete cpu-sim.h, include/opcode/cgen.h.
-	(mloop.c): Build pseudo-basic-block version.  Depend on stamp-cpu.
-	(stamp-decode): Delete, build decode files with other cpu files.
-	* arch.c,arch.h,cpuall.h: Regenerate.
-	* cpu.c,cpu.h,decode.c,decode.h,extract.c,model.c: Regenerate.
-	* sem-switch.c,sem.c: Regenerate.
-	* m32r-sim.h (M32R_MISC_PROFILE): New members load_regs,
-	load_regs_pending.
-	* m32r.c (m32rbf_fetch_register): Renamed from m32rb_fetch_register.
-	(m32rbf_store_register,m32rbf_h_cr_get,m32rbf_h_cr_set,
-	m32rbf_h_psw_get,m32rbf_h_psw_set,m32rbf_h_accum_get,
-	m32rbf_h_accum_set): Likewise.
-	(m32r_model_{init,update}_insn_cycles): Delete.
-	(m32rbf_model_insn_{before,after}): New fns.
-	(m32r_model_record_cti,m32r_model_record_cycles): Delete.
-	(m32rb_model_mark_get_h_gr,m32rb_model_mark_set_h_gr): Delete.
-	(m32rb_model_mark_busy_reg,m32rb_model_mark_unbusy_reg): Delete.
-	(check_load_stall): New fn.
-	(m32rbf_model_m32r_d_u_{exec,cmp,mac,cti,load,store}): New fns.
-	(m32rbf_model_test_u_exec): New fn.
-	* mloop.in: Rewrite, use pbb support.
-	* sim-if.c (sim_stop,sim_sync_stop,sim_resume): Delete.
-	(sim_fetch_register,sim_store_register): Delete.
-	* sim-main.h (CIA_GET,CIA_SET): Fix.
-	(SIM_ENGINE_HALT_HOOK,SIM_ENGINE_RESTART_HOOK): Delete.
-	* tconfig.in (WITH_SCACHE_PBB): Define.
-	(WITH_SCACHE_PBB_M32RBF): Define.
-	* traps.c (sim_engine_invalid_insn): Renamed from ..._illegal_....
-	(m32r_trap): Pass pc to sim_engine_halt.
-	* configure.in (SIM_AC_OPTION_SCACHE): Change 1024 to 16384.
-	* configure: Regenerate.
-start-sanitize-cygnus
-	* Makefile.in (M32RX_OBJS): Delete semx.o, add extract.o.
-	(mloopx.c): Build pseudo-basic-block version.  Depend on stamp-xcpu.
-	(semx.o): Delete.
-	(extractx.o): Add.
-	(stamp-xdecode): Delete, build decode files with other cpu files.
-	* cpux.c,cpux.h,decodex.c,decodex.h,modelx.c: Regenerate.
-	* readx.c: Delete.
-	* semx.c: Delete.
-	* extractx.c: New file.
-	* semx-switch.c: New file.
-	* m32r-sim.h (BRANCH_NEW_PC): Delete.
-	(SEM_SKIP_INSN): New macro.
-	* m32rx.c (m32rxf_fetch_register): Renamed from m32rx_fetch_register.
-	(m32rxf_store_register,m32rxf_h_cr_get,m32rxf_h_cr_set,
-	m32rxf_h_psw_get,m32rxf_h_psw_set,m32rxf_h_accum_get,
-	m32rxf_h_accum_set,m32rxf_h_accums_get,m32rxf_h_accums_set): Likewise.
-	(m32rxf_model_insn_{before,after}): New fns.
-	(m32rx_model_mark_get_h_gr,m32rx_model_mark_set_h_gr): Delete.
-	(m32rx_model_mark_busy_reg,m32rx_model_mark_unbusy_reg): Delete.
-	(check_load_stall): New fn.
-	(m32rxf_model_m32rx_u_{exec,cmp,mac,cti,load,store}): New fns.
-	* mloopx.in: Rewrite, use pbb support.
-	* tconfig.in (WITH_SCACHE_PBB_M32RXF): Define.
-	(WITH_SEM_SWITCH_FULL): Change from 0 to 1.
-end-sanitize-cygnus
-
-Wed Sep 16 18:22:27 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* m32r-sim.h ({PSW,CBR,SPI,SPU,BPC,BBPSW,BBPC}_REGNUM): New macros.
-	({ACC1L,ACC1H}_REGNUM): New macros.
-	(m32r_decode_gdb_ctrl_regnum): Add prototype.
-	* m32r.c (m32r_decode_gdb_ctrl_regnum): New function.
-	(m32r_fetch_register,m32r_store_register): Rewrite.
-start-sanitize-cygnus
-	* m32rx.c (m32rx_fetch_register,m32rx_store_register): Rewrite.
-end-sanitize-cygnus
-
-Tue Sep 15 15:01:14 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* m32r-sim.h (GET_H_SM): New macro.
-	(UART params): Update to msa2000.
-	* devices.c (device_io_read_buffer): Update to msa2000.
-	* m32r.c (m32rb_h_cr_get,m32rb_h_cr_set): Handle bbpc,bbpsw.
-	(m32rb_h_psw_get,m32rb_h_psw_set): New functions.
-	* arch.c,arch.h,cpu.c,cpu.h,sem-switch.c,sem.c: Regenerate.
-start-sanitize-cygnus
-	* m32rx.c (m32rx_h_cr_get,m32rx_h_cr_set): Handle bbpc,bbpsw.
-	(m32rx_h_psw_get,m32rx_h_psw_set): New functions.
-	* cpux.c,cpux.h,readx.c,semx.c: Regenerate.
-end-sanitize-cygnus
-
-Wed Sep  9 15:29:36 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* m32r-sim.h (m32r_trap): Update prototype.
-	* traps.c (m32r_trap): New arg `pc'.
-	* sem.c,sem-switch.c: Regenerated.
-start-sanitize-cygnus
-	* cpux.h,readx.c,semx.c: Regenerated.
-end-sanitize-cygnus
-
-Mon Aug  3 12:59:17 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	Rename cpu m32r to m32rb to distinguish from architecture name.
-	* Makefile.in (mloop.c): cpu m32r renamed to m32rb.
-	(stamp-cpu): Ditto.
-	* sim-main.h (WANT_CPU_M32RB): Renamed from WANT_CPU_M32R.
-	* tconfig.in (WANT_CPU_M32RB): Ditto.
-	* m32r.c (WANT_CPU_M32RB): Ditto.
-	(*): m32r_ cpu fns renamed to m32rb_.
-	* sim-if.c (sim_stop,sim_sync_stop,sim_resume): Update.
-	* arch.h,arch.c: Regenerate.
-	* cpu.c,cpu.h,decode.c,decode.h,extract.c,model.c: Regenerate.
-	* sem-switch.c,sem.c: Regenerate.
-
-	* sim-if.c (sim_open): Don't allocate memory on top of any user
-	specified memory.
-	(h_gr_get,h_gr_set): Delete.
-	* sim-main.h (h_gr_get,h_gr_set): Delete.
-	* traps.c (m32r_trap): Replace calls to h_gr_[gs]et with
-	a_m32r_h_gr_[gs]et.
-
-	* Makefile.in (INCLUDE_DEPS): Add include/opcode/cgen.h.
-
-	* sim-if.c (sim_open): Open opcode table.
-	(sim_close): Close it.
-
-start-sanitize-cygnus
-Tue Jul 28 13:06:19 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	Add support for new versions of mulwhi,mulwlo,macwhi,macwlo that
-	accept an accumulator choice.
-	* cpux.c,decodex.c,decodex.h,modelx.c,readx.c,semx.c: Regenerate.
-
-end-sanitize-cygnus
-Fri Jul 24 13:00:29 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* m32r.c: Include cgen-mem.h.
-	* traps.c (m32r_trap): Tweak for -Wall.
-start-sanitize-cygnus
-	* m32rx.c: Include cgen-mem.h.
-	* semx.c: Regenerate, get -Wall cleanups.
-end-sanitize-cygnus
-
-Tue Jul 21 16:53:10 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* cpu.h,extract.c: Regenerate.  pc-rel calcs done on f_dispNN now.
-start-sanitize-cygnus
-	* cpux.h,readx.c,semx.c: Ditto.
-end-sanitize-cygnus
-
-Wed Jul  1 16:51:15 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* Makefile.in: cgen_maint -> CGEN_MAINT.
-	* configure.in: AC_SUBST cgen,cgendir.  No longer look for guile.
-	* configure: Regenerate.
-	* arch.c,arch.h,cpuall.h: Regenerate.
-	* cpu.c,cpu.h,decode.c,decode.h,extract.c,model.c: Regenerate.
-	* sem-switch.c,sem.c: Regenerate.
-start-sanitize-cygnus
-	* cpux.c,cpux.h,decodex.c,decodex.h,modelx.c,readx.c: Regenerate.
-	* semx.c: Regenerate.
-	* mloopx.in (icount): Moved here from genmloop.sh.
-end-sanitize-cygnus
-
-Sat Jun 13 07:49:23 1998  Doug Evans  <devans@fallis.cygnus.com>
-
-	* m32r-sim.h (M32R_MISC_PROFILE): New members insn_cycles, cti_stall,
-	load_stall,biggest_cycles.
-	* m32r.c (m32r_model_mark_get_h_gr): Update.
-	(m32r_model_init_insn_cycles,m32r_model_update_insn_cycles): New fns.
-	(m32r_model_record_cti,m32r_model_record_cycles): New functions.
-	* mloop.in: Call cycle init/update fns.
-	* model.c: Regenerate.
-start-sanitize-cygnus
-	* m32rx.c (m32rx_model_mark_get_h_gr): Update.
-	* mloopx.in: Call cycle init/update fns.
-	* modelx.c: Regenerate.
-end-sanitize-cygnus
-
-Thu Jun 11 23:39:53 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* Makefile.in (stamp-{arch,cpu,decode}): Pass CGEN_FLAGS_TO_PASS
-	to recursive makes.
-start-sanitize-cygnus
-	(stamp-{xcpu,xdecode}): Ditto.
-end-sanitize-cygnus
-
-Wed Jun 10 17:39:29 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* traps.c: New file.  Trap support moved here from sim-if.c.
-	* Makefile.in (SIM_OBJS): Add traps.o
-	* sim-if.c: Don't include targ-vals.h.
-	(sim_engine_illegal_insn): Moved to traps.c
-	* sim-main.h (SIM_CORE_SIGNAL): Define.
-	(m32r_core_signal): Declare.
-	* m32r-sim.h (m32r_trap): Declare.
-
-	* devices.c (device_io_read_buffer): Handle cache purging via MCCR
-	register.
-
-	* m32r-sim.h (M32R_MISC_PROFILE): Move here from sim-main.h.
-	(PROFILE_COUNT_SHORTINSNS,PROFILE_COUNT_LONGINSNS): New macros.
-	(TRAP_SYSCALL,TRAP_BREAKPOINT): New macros.
-
-	* extract.c,sem-switch.c,sem.c: Regenerate.
-start-sanitize-cygnus
-	* cpux.h,readx.c,semx.c: Regenerate.
-end-sanitize-cygnus
-
-Wed May 20 00:10:40 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* m32r-sim.h (PROFILE_COUNT_PARINSNS): New macro.
-	* mloopx.in (extract): Set abuf.addr for proper fill nop counting.
-	(execute): Count parallel insns.
-	* sim-if.c (print_m32r_misc_cpu): Print count.
-	* sim-main.h (M32R_MISC_PROFILE): New member parallel_count.
-
-	Zero bottom two bits of pc in jmp,jl insns.
-	* sem.c,sem-switch.c: Regenerate.
-start-sanitize-cygnus
-	* semx.c: Regenerate.
-end-sanitize-cygnus
-
-Tue May 19 16:45:33 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* sim-if.c (do_trap): Treat traps 2-15 as hardware does.
-
-Sat May 16 13:04:30 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* sim-if.c (sim_stop): Update call to @cpu@_engine_stop.
-	(sim_sync_stop): New function.
-
-Fri May 15 16:43:27 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* Makefile.in (devices.o): Add dependencies.
-
-	* arch.h,cpu.c,cpu.h,cpuall.h: Regenerate.
-	* sem-switch.c,sem.c: Regenerate.
-	* mloop.in (execute): Update calls to TRACE_INSN_{INIT,FINI}.
-start-sanitize-cygnus
-	* cpux.c,cpux.h,modelx.c,semx.c: Regenerate.
-	* m32rx.c (m32rx_model_mark_{busy,unbusy}_reg): New functions.
-	* mloopx.in (execute): Update calls to TRACE_INSN_{INIT,FINI}.
-	Fix pc value passed to TRACE_INSN for second parallel insn.
-end-sanitize-cygnus
-
-Thu May  7 02:51:35 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* Makefile.in (SIM_OBJS): Add sim-cpu.o.
-
-Wed May  6 14:51:39 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* arch.h,arch.c,cpu.h,cpuall.h: Regenerate, tweaks mostly.
-	* model.c: Ditto.  Reorganize model/mach data.
-start-sanitize-cygnus
-	* cpux.h: Ditto.
-	* modelx.c: Ditto.
-end-sanitize-cygnus
-
-	* Makefile.in (m32r.o,mloop.o,cpu.o,model.o): Add decode.h dependency.
-start-sanitize-cygnus
-	(m32rx.o,mloopx.o,cpux.o,modelx.o): Add decodex.h dependency.
-end-sanitize-cygnus
-	* decode.c,decode.h: Regenerate, introduces IDESC table.
-	* mloop.in (extract16,extract32): Add IDESC support.
-	Update names of semantic handler member names.
-	(execute): Ditto.  Delete call to PROFILE_COUNT_INSN.
-start-sanitize-cygnus
-	* decodex.c,decodex.h: Regenerate, introduces IDESC table.
-	* mloopx.in: Add IDESC support.
-	Update names of semantic handler member names.
-	Delete call to PROFILE_COUNT_INSN.
-end-sanitize-cygnus
-
-	* sem-switch.c: Regenerate.  Redo computed goto label handling.
-	* sem.c: Regenerate.  Call PROFILE_COUNT_INSN.
-start-sanitize-cygnus
-	* readx.c: Regenerate.  Redo computed goto label handling.
-	* semx.c: Regenerate.  Call PROFILE_COUNT_INSN.  Finish profiling
-	support.
-	* Makefile.in (stamp-xcpu): Turn on profiling support.
-end-sanitize-cygnus
-
-	* m32r.c (m32r_fetch_register): Change result type and args to
-	conform to sim_fetch_register interface.
-	(m32r_store_register): Ditto for sim_store_register interface.
-start-sanitize-cygnus
-	* m32rx.c (m32rx_fetch_register): Change result type and args to
-	conform to sim_fetch_register interface.
-	(m32rx_store_register): Ditto for sim_store_register interface.
-end-sanitize-cygnus
-
-	* sim-if.c (alloc_cpu): Delete.
-	(free_state): Uninstall modules here ...
-	(sim_open): ... and not here.  Call sim_cpu_alloc_all.
-	Set default architecture/model if not specified.
-	(sim_fetch_register,sim_store_register): Rewrite.
-
-	* sim-if.c (h_pc_get,h_pc_set): Delete.  Renamed to sim_pc_[gs]et
-	and moved to common/sim-cpu.c.
-	(sim_create_inferior): Update.
-	(do_trap): Update.
-	* sim-main.h (h_pc_get,h_pc_set): Delete.
-
-	* sim-main.h (sim_cia): Change to USI.
-	(sim_cpu): Move m32r_misc_profile before machine generated part.
-
-Fri May  1 18:25:41 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* Makefile.in: Replace @MAINT@ with $(CGEN_MAINT).
-	(CGEN_MAINT): New variable.
-	* configure.in: Add support for --enable-cgen-maint.
-	* configure: Regenerate.
-
-Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
-
-        * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Tue Apr 28 18:05:53 1998  Nick Clifton  <nickc@cygnus.com>
-
-	* model.c: Rebuilt.
-start-sanitize-cygnus
-	* modelx.c: Rebuilt.
-end-sanitize-cygnus
-
-Mon Apr 27 15:36:30 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* cpu.h,model.c,sem-switch.c,sem.c: Regenerated.  Mostly comment
-	and variable renaming due to macro insn additions.
-	* mloop.in: Update to use CGEN_INSN_NUM.
-start-sanitize-cygnus
-	* cpux.h,modelx.c,readx.c,semx.c: Regenerated.
-	* mloopx.in: Update to use CGEN_INSN_NUM.
-end-sanitize-cygnus
-
-Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-	* config.in: Ditto.
-
-Sun Apr 26 15:20:05 1998  Tom Tromey  <tromey@cygnus.com>
-
-	* acconfig.h: New file.
-	* configure.in: Reverted change of Apr 24; use sinclude again.
-
-Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-	* config.in: Ditto.
-
-Fri Apr 24 11:19:26 1998  Tom Tromey  <tromey@cygnus.com>
-
-	* configure.in: Don't call sinclude.
-
-Mon Apr 20 16:12:35 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* cpu.c,sem.c,sem-switch.c: Regenerate.  From
-	- cgen/m32r.cpu (h-accum): Add attribute FUN-ACCESS.
-	* m32r.c (m32r_h_accum_get,m32r_h_accum_set): New functions.
-	#include cgen-ops.h.
-start-sanitize-cygnus
-	* cpux.c,readx.c,semx.c: Regenerate.
-	* m32rx.c (m32r_h_accum_get,m32r_h_accum_set): New functions.
-	#include cgen-ops.h.  Delete inclusion of several unnecessary headers.
-	(m32r_h_accums_get): Sign extend top 8 bits.
-end-sanitize-cygnus
-
-start-sanitize-cygnus
-Tue Apr 14 14:04:07 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* semx.c: Regenerate.
-
-end-sanitize-cygnus
-Fri Apr 10 18:22:41 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* cpu.h,decode.c,decode.h,extract.c,sem.c,sem-switch.c: Regenerate.
-start-sanitize-cygnus
-	* cpux.h,decodex.c,decodex.h,readx.c,semx.c: Regenerate.
-end-sanitize-cygnus
-
-Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Sat Mar 14 20:53:36 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* config.in (HAVE_FCNTL_H): Add.
-	* configure: Regenerate.
-	* Makefile.in (SIM_OBJS): Add devices.o.
-	* m32r-sim.h (m32r_devices): Renamed from m32r_mspr_device.
-	(UART_*): Define m32r serial port parameters.
-	(M32R_DEVICE_ADDR,M32R_DEVICE_LEN): Define.
-	* m32r.c (device_io_{read,write}_buffer,device_error): Move from here,
-	* devices.c: To here.
-	* sim-if.c: Don't include signal.h,sim-core.h.
-	(sim_open): Use M32R_DEVICE_{ADDR,LEN} in sim_core_attach call.
-	(sim_resume): Call sim_module_{resume,suspend}.
-	* m32r.c (m32r_h_cr_{get,set}): Use register number enums.
-
-	* tconfig.in (SIM_HANDLES_LMA): Define.
-
-	* sim-if.c (do_trap): Result is new pc.
-	Handle --environment=operating.
-	* sem-switch.c,sem.c: Regenerate.
-start-sanitize-cygnus
-	* semx.c: Regenerate.
-end-sanitize-cygnus
-
-Wed Mar 11 14:07:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* sim-if.c (syscall_read_mem, syscall_write_mem): Replace
- 	sim_core_*_map with read_map, write_map, exec_map resp.
-
-Wed Mar  4 11:36:51 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* Makefile.in (SIM_EXTRA_DEPS): Add cpu-opc.h.
-	(arch.o): Delete cpu-opc.h dependency.
-	(decode.o,model.o): Likewise.
-start-sanitize-cygnus
-	(decodex.o,modelx.o): Likewise.
-end-sanitize-cygnus
-
-	* cpu.h,model.c,sem-switch.c,sem.c: Regenerate.
-start-sanitize-cygnus
-	* cpux.h,decodex.[ch],modelx.c,readx.c,semx.c: Regenerate.
-end-sanitize-cygnus
-
-Thu Feb 26 18:38:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* sim-if.c (sim_open): Initialize PROFILE_INFO_CPU_CALLBACK.
-
-	* sim-if.c (sim_info): Delete.
-
-start-sanitize-cygnus
-Fri Feb 27 10:14:29 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* mloopx.in: Fix handling of branch in parallel with another insn.
-	* semx.c: Regenerate.
-
-end-sanitize-cygnus
-Mon Feb 23 13:30:46 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* sim-main.h: #include symcat.h.
-	* m32r-sim.h (BRANCH_NEW_PC): Delete current_cpu arg.
-	(NEW_PC_{BASE,SKIP,2,4,BRANCH_P}): New macros.
-	* cpu.[ch],decode.[ch],extract.c,model.c: Regenerate.
-	* sem.c,sem-switch.c: Regenerate.
-start-sanitize-cygnus
-	* m32r-sim.h (SEM_NEXT_PC): Modify to handle parallel exec.
-	* mloopx.in: Rewrite.
-	* cpux.[ch],decodex.[ch],readx.c,semx.c: Regenerate.
-end-sanitize-cygnus
-
-Mon Feb 23 12:27:52 1998  Nick Clifton  <nickc@cygnus.com>
-
-	* m32r.c (m32r_h_cr_set, m32r_h_cr_get): Shadow control register 6
-	in the backup PC register.
-start-sanitize-cygnus
-	* m32rx.c (m32r_h_cr_set, m32r_h_cr_get): Shadow control register 6
-	in the backup PC register.
-end-sanitize-cygnus
-
-Thu Feb 19 16:39:35 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* m32r.c (do_lock,do_unlock): Delete.
-	* cpu.[ch],decode.[ch],extract.c,model.c: Regenerate.
-	* sem.c,sem-switch.c: Regenerate.
-start-sanitize-cygnus
-	* cpux.[ch],decodex.[ch],readx.c,semx.c: Regenerate.
-end-sanitize-cygnus
-
-Tue Feb 17 18:18:10 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* Makefile.in (M32R_OBJS): Add cpu.o.
-	(cpu.o): Add rule for.
-	(NL_TARGET): Define.
-	* configure.in: Add AC_CHECK_PROG(SCHEME).
-	* cpu.c: New file.
-	* cpuall.h,cpu.h,decode.c,decode.h,extract.c,model.c: Regenerate.
-	* sem-switch.c,sem.c: Regenerate.
-	* mloop.in (execute): Update call to semantic fn.
-start-sanitize-cygnus
-	(M32RX_OBJS): Add cpux.o.
-	(cpux.o): Add rule for.
-	cpux.c: New file.
-	* cpux.h,decodex.c,decodex.h,modelx.c,readx.c,semx.c: Regenerate.
-	* m32rx.c (m32rx_h_accums_{get,set}): Rewrite.
-	(m32rx_h_cr_{get,set}): New functions.
-	(m32rx_h_accums_{get,set}): New functions.
-	* mloopx.in: Rewrite main loop.
-end-sanitize-cygnus
-
-	* m32r.c (do_trap): Move from here.
-	* sim-if.c (do_trap): To here, and rewrite to use CB_SYSCALL support.
-	(sim_create_inferior): Use h_pc_set.
-	(h_pc_{get,set}): New functions.
-	(h_gr_{get,set}): New functions.
-	(syscall_{read,write}_mem): New functions.
-	* sim-main.h (h_{gr,pc}_{get,set}): Declare.
-
-Tue Feb 17 12:44:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* sim-if.c (sim_store_register, sim_fetch_register): Pass in
- 	length parameter.  Return -1.
-	(sim_create_inferior): Pass 4 sim_store_register.
-
-Wed Feb 11 19:53:48 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* sim-main.h (CIA_GET,CIA_SET): Provide dummy definitions for now.
-
-	* decode.c, decode.h, sem.c, sem-switch.c, model.c: Regenerate.
-start-sanitize-cygnus
-	* cpux.c, decodex.c, decodex.h, readx.c, semx.c, modelx.c: Regenerate.
-end-sanitize-cygnus
-
-Mon Feb  9 19:41:54 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* decode.c, sem.c: Regenerate.
-start-sanitize-cygnus
-	* cpux.h, decodex.c, readx.c, semx.c: Regenerate.
-	* m32rx.c (m32rx_h_accums_set): New function.
-	(m32rx_model_mark_[gs]et_h_gr): New function.
-	* mloopx.in: Rewrite.
-	* Makefile.in (mloopx.o): Build with -parallel.
-	* sim-main.h (_sim_cpu): Delete member `par_exec'.
-	* tconfig.in (WITH_SEM_SWITCH_FULL): Define as 0 for m32rx.
-end-sanitize-cygnus
-
-Thu Feb  5 12:44:31 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* Makefile.in (m32r.o): Depend on cpu.h
-	(extract.o): Pass -DSCACHE_P.
-	* mloop.in (extract{16,32}): Update call to m32r_decode.
-	* arch.h,cpu.h,cpuall.h,decode.[ch]: Regenerate.
-	* extract.c,model.c,sem-switch.c,sem.c: Regenerate.
-	* sim-main.h: #include "ansidecl.h".
-	Don't include cpu-opc.h, done by arch.h.
-start-sanitize-cygnus
-	* Makefile.in (M32RX_OBJS): Build m32rx support now.
-	(m32rx.o): New rule.
-	* m32r-sim.h (m32rx_h_cr_[gs]et): Define.
-	* m32rx.c (m32rx_{fetch,store}_register): Update {get,set} of PC.
-	(m32rx_h_accums_get): New function.
-	* mloopx.in: Update call to m32rx_decode.  Rewrite exec loop.
-	* cpux.h,decodex.[ch],modelx.c,readx.c,semx.c: Regenerate.
-end-sanitize-cygnus
-
-Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-start-sanitize-cygnus
-Thu Jan 29 11:22:00 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* Makefile.in (M32RX_OBJS): Comment out until m32rx port working.
-	* arch.h (HAVE_CPU_M32R{,X}): Delete, moved to m32r-opc.h.
-	* arch.c (machs): Check ifdef HAVE_CPU_FOO for each entry.
-
-end-sanitize-cygnus
-Tue Jan 20 14:16:02 1998  Nick Clifton  <nickc@cygnus.com>
-
-	* cpux.h: Fix duplicate definition of h_accums field for
-	fmt_53_sadd structure.
-
-start-sanitize-cygnus
-Tue Jan 20 01:42:17 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* Makefile.in: Add m32rx objs, and rules to build them.
-	* cpux.h, decodex.h, decodex.c, readx.c, semx.c, modelx.c: New files.
-	* m32rx.c, mloopx.in: New files.
-
-end-sanitize-cygnus
-Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Mon Jan 19 14:13:40 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* arch.c, arch.h, cpuall.h: New files.
-	* arch-defs.h: Deleted.
-	* mloop.in: Renamed from mainloop.in.
-	* Makefile.in: Update.
-	* sem-ops.h: Deleted.
-	* mem-ops.h: Deleted.
-start-sanitize-cygnus
-	Add cgen support for generating files.
-end-sanitize-cygnus
-	(arch): Renamed from CPU.
-	* cpu.h: New file.
-	* decode.c: Redone.
-	* decode.h: Redone.
-	* extract.c: Redone.
-	* model.c: Redone.
-	* sem-switch.c: Redone.
-	* sem.c: Renamed from semantics.c, and redone.
-	* m32r-sim.h (PROFILE_COUNT_FILLNOPS): Update.
-	(GETTWI,SETTWI,BRANCH_NEW_PC): Define.
-	* m32r.c (WANT_CPU,WANT_CPU_M32R): Define.
-	(m32r_{fetch,store}_register): New functions.
-	(model_mark_{get,set}_h_gr): Prefix with m32r_.
-	(m32r_model_mark_{busy,unbusy}_reg): Prefix with m32r_.
-	(h_cr_{get,set}): Prefix with m32r_.
-	(do_trap): Fetch state from current_cpu, not current_state.
-	Call sim_engine_halt instead of engine_halt.
-	* sim-if.c (alloc_cpu): New function.
-	(free_state): New function.
-	(sim_open): Call sim_state_alloc, and malloc space for selected cpu
-	type.  Call sim_analyze_program.
-	(sim_create_inferior): Handle selected cpu type when setting PC.
-start-sanitize-cygnus
-	(sim_resume): Handle m32rx.
-end-sanitize-cygnus
-	(sim_stop_reason): Deleted.
-	(print_m32r_misc_cpu): Update.
-start-sanitize-cygnus
-	(sim_{fetch,store}_register): Handle m32rx.
-end-sanitize-cygnus
-	(sim_{read,write}): Deleted.
-	(sim_engine_illegal_insn): New function.
-	* sim-main.h: Don't include arch-defs.h,sim-core.h,sim-events.h.
-	Include arch.h,cpuall.h.  Include cpu.h,decode.h if m32r.
-start-sanitize-cygnus
-	Include cpux.h,decodex.h if m32rx.
-end-sanitize-cygnus
-	(_sim_cpu): Include member appropriate cpu_data member for the cpu.
-	(M32R_MISC_PROFILE): Renamed from M32R_PROFILE.
-	(sim_state): Delete members core,events,halt_jmp_buf.
-	Change `cpu' member to be a pointer to the cpu's struct, rather than
-	record inside the state struct.
-	* tconfig.in (WITH_DEVICES): Define here.
-	(WITH_FAST,WITH_SEM_SWITCH_{FULL,FAST}): Define for the cpu.
-
-Fri Jan 16 12:16:56 1998  Nick Clifton  <nickc@cygnus.com>
-
-	* arch-defs.h (INSN_NAME): Fix typo.
-
-Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-	* config.in: Ditto.
-
-Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
-
-	* m32r-sim.h (MSPR_ADDR): New macro.
-	(m32r_mspr_device): Declare.
-	(struct _device): Define.
-	* m32r.c (m32r_mspr_device): New global.
-	(device_{io_{read,write}_buffer,error}): New functions.
-	* mem-ops.h (SETMEM*): Use sim_core_write_map, not read map.
-	* sim-if.c: Delete redundant inclusion of cpu-sim.h.
-	(sim_open): Attach device to handle MSPR register.
-	* sim-main.h (WITH_DEVICES): Define as 1.
-	Include cpu-sim.h.
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Wed Dec  3 18:08:44 1997  Doug Evans  <devans@canuck.cygnus.com>
-
-	* configure.in (SIM_AC_OPTION_ENVIRONMENT): Call.
-	* configure: Regenerated.
-
-Wed Nov 19 12:17:08 1997  Doug Evans  <devans@canuck.cygnus.com>
-
-	* mem-ops.h: Rename SIM_SIG{ACCESS,ALIGN} to SIM_SIG{SEGV,BUS}.
-	* sim-if.c (sim_open): Call sim_config.
-	(sim_stop_reason): Update call to sim_signal_to_host.
-
-Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
-
-	* Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
-
-Fri Oct 31 18:46:46 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* sim-if.c (sim_open): Delete dead call to sim_core_attach.
-
-Mon Oct 27 12:43:54 1997  Doug Evans  <devans@canuck.cygnus.com>
-
-	* sem-ops.h (U{DIV,MOD}[BHSD]I): Use unsigned division.
-
-Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* Makefile.in (SIM_ENDIAN, SIM_HOSTENDIAN, SIM_SCACHE,
- 	SIM_DEFAULT_MODEL): Delete, moved to common.
-	(SIM_EXTRA_CFLAGS): Update.
-	
-Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure.in (sim_link_links): Configure non-strict memory
- 	alignment.
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Wed Sep 17 17:44:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* sim-if.c (sim_open): Allocate memory under sim-memopt module
- 	using sim_do_commandf.
-	(sim_open): Set magic-number at the start.
-	(sim_do_command): Implement.
-
-	* sim-main.h (sim_engine_halt): Map onto engine_halt.
-
-Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Fri Sep  5 10:21:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* Makefile.in (SIM_OBJS): Add sim-memopt.o module.
-
-Thu Sep  4 10:30:02 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* sim-if.c (sim_open): Pass zero modulo arg to sim_core_attach.
-
-Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-	* config.in: Ditto.
-
-Tue Aug 26 10:39:42 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* sim-if.c (sim_kill): Delete.
-	(sim_create_inferior): Add ABFD argument.
-	(sim_load): Move setting of PC from here.
-	(sim_create_inferior): To here.
-	(sim_load): Delete, use sim-hload.c instead.
-
-	* Makefile.in (SIM_OBJS): Add sim-hload.o module.
-
-Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-	* config.in: Ditto.
-
-Mon Aug 25 15:54:08 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* sim-if.c (sim_open): Add ABFD argument.
-
-Tue Jul 22 10:16:16 1997  Doug Evans  <dje@canuck.cygnus.com>
-
-	* sim-main.h (M32R_DEFAULT_MEM_SIZE): New macro.
-	* sim-if.c (sim_open): Use it.
-
-Wed Jun  4 12:48:12 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* sim-main.h (WITH_ENGINE): Disable the common engine for now.
-
-Tue May 27 14:15:44 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* sim-if.c (sim_read): Pass NULL cpu to sim_core_read_buffer.
-	(sim_write): Ditto for write.
-
-	* m32r.c (do_trap): Ditto for read/write.
-
-Tue May 20 10:18:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* sim-if.c (sim_open): Add callback argument.
-	(sim_set_callbacks, sim_callback): Delete.
-	(sim_load): Set STATE_LOADED_P.
-
-Mon May 19 12:55:42 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* Makefile.in (SIM_OBJS): Link in sim-abort.o as a stub for
- 	sim_engine_abort.
-
-Mon May  5 12:45:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* sim-if.c (sim_open): Update to reflect changes to core in
- 	../common/.
-	* mem-ops.h (GETMEMQI, GETMEMHI, GETMEMSI, GETMEMDI, GETMEMUQI,
- 	GETMEMUHI, GETMEMUSI, GETMEMUDI, SETMEMQI, SETMEMHI, SETMEMSI,
- 	SETMEMDI, SETMEMUQI, SETMEMUHI, SETMEMUSI, SETMEMUDI): Ditto.
-
-Sat May  3 08:38:55 1997  Doug Evans  <dje@seba.cygnus.com>
-
-	* decode.c (decode): Add computed goto support.
-
-Fri May  2 16:30:26 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* mem-ops.h: Stub additional core read/write arguments.
-
-	* sim-main.h: Declare sim_cia - type SI.
-	(struct _sim_cpu): Move base type to end per common.
-	(struct _sim_state): Ditto.
-
-Thu May  1 11:15:34 1997  Doug Evans  <dje@canuck.cygnus.com>
-
-	Merge from branch into devo.  CGEN generic files moved to common
-	directory.  K&R C support is no longer provided.
-
-Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Sat Apr 12 12:57:33 1997  Felix Lee  <flee@yin.cygnus.com>
-
-	* Makefile.in, seman-cache.c: new file, for wingdb build.
-	* sim-alloca.h: fixed for wingdb.
-	
-Mon Apr  7 13:33:29 1997  Doug Evans  <dje@seba.cygnus.com>
-
-	* decode.c (*): m32r_cgen_insn_table renamed to ..._entries.
-	* mainloop.in: Use CGEN_INSN_INDEX instead of CGEN_INSN_TYPE.
-	* simdefs.h (INSN_NAME): m32r_cgen_insn_table renamed to ..._entries.
-
-Fri Apr  4 19:23:12 1997  Doug Evans  <dje@canuck.cygnus.com>
-
-	* cgen-utils.in (ex_illegal): Fill in abuf->length, abuf->addr.
-	(exc_illegal): Likewise.
-	* decode.c (decode_vars): Add decode_illegal.
-	* genmloop.sh: #include "cpu-opc.h".
-	* sem-switch.c (case_INSN_ILLEGAL): Declare.
-	(labels): Add case_INSN_ILLEGAL.
-	(SWITCH): Add INSN_ILLEGAL case.
-
-Wed Mar 26 12:34:00 1997  Doug Evans  <dje@canuck.cygnus.com>
-
-	* model.c (model_module): Use 0 not NULL.
-
-	* genmloop.sh (sim_main_loop): Handle k&r c.
-
-	* sem-switch.c: Regenerate to get k&r c support.
-	* semantics.c: Likewise.
-
-	* m32r.c (ADD_{OV,CA}_SI,SUB_{OV,CA}_SI): Renamed to {ADD,SUB}[OC]FSI.
-	(ADDCSI,SUBCSI): New functions.
-	* sem-switch.c (addv,addv3,addx,subv,subx): Fix carry bit handling.
-	* semantics.c (addv,addv3,addx,subv,subx): Fix carry bit handling.
-
-	* simcache.c (simcache_{install,init,uninstall}): Use
-	DECLARE_MODULE_INSTALL_HANDLER.
-	(simcache_option_handler): Use DECLARE_OPTION_HANDLER.
-
-	* utils.c: #include "semops.h".
-
-Tue Mar 11 14:30:26 1997  Doug Evans  <dje@seba.cygnus.com>
-
-	* profile.c (profile_print_simcache): Fix thinko in printf text.
-
-	* simdefs.h (struct argbuf): Add member to fmt_20 so it's not empty.
-
-Mon Mar 10 11:06:29 1997  Doug Evans  <dje@seba.cygnus.com>
-
-	* m32r.c (h_cr_get): Rewrite.
-	(h_cr_set): Rewrite.
-	* sem-switch.c (rte): bcarry renamed to bcond.
-	* semantics.c (rte): Likewise.
-	* simdefs.h (CPU_STATE): Likewise.
-
-	* config.in (HAVE_SYS_TIME_H): Add.
-	* configure.in: Check for sys/time.h.
-	* configure: Regenerated.
-	* utils.c: Include sys/time.h if present.
-
-	* common.c (sim_parse_args): Account for NULL terminating entry
-	in long_options table.
-
-	* genmloop.sh (RUN_FAST_P): Don't run fast if tracing.
-	Always use cache if configured in.
-	* mainloop.in (do_extract_insn{16,32}): New functions.
-	(normal,fast): Call them.  Handle starting in left slot.
-	* simcache.c (simcache_option_handler): Disallow -c0.
-	* sem-switch.c (TRACE_RESULT): Redefine so no tracing.
-
-	* profile.c (profile_print_simcache): Fix percentage calc.
-
-	* Makefile.in (INCLUDE_DEPS): Delete simcommon.h.
-
-Sun Mar  9 20:42:17 1997  Doug Evans  <dje@seba.cygnus.com>
-
-	* Makefile.in (COMMON_{PRE,POST}_CONFIG_FRAG): Add delimiters for.
-	(M32R_INCLUDE_DEPS): Use cpu-sim.h instead of m32r-sim.h.
-	Add mod-list.h.
-	(mrun.o): Don't depend on M32R_INCLUDE_DEPS.
-	(sim-if.o,m32r.o,utils.o): Likewise.
-	(common.o): Don't explicitly depend on mod-list.h.
-	(mainloop.c): Pass CPU to genmloop.sh.
-	(stamp-modules): Depend on configure.
-	(decode.o): Depend on decode,h, memops.h, semops.h, cpu-opc.h.
-	(extract.o): Depend on decode.h, memops.h, semops.h.
-	(semantics.o,seman-cache.o): Likewise.
-	(model.o,ops.o): Depend on memops.h.
-	(extr-cache.o): Disable building for the moment.
-
-	* simcommon.h: Delete, move contents into cgen-sim.h.
-	* cgen-sim.h: Don't include ansidecl.h,bfd.h,simfns.h.
-	(UINT,CGEN_CAT3): Define.
-	({extract,semantic}_fn_t): Renamed to {EXTRACT,SEMANTIC}_FN.
-	(decode_t): Renamed to DECODE.
-
-	* simfns.h: Delete, contents moved to memops.h,semops.h.
-	* memops.h: New file.
-	* semops.h: New file.
-	* decode.h: Renamed from semantics.h.
-
-	* sim-argv.h: New file.
-	* Makefile.in (memory.o,trace.o,profile.o,simcache.o,common): Add
-	dependency of sim-argv.h.
-
-	* sim-alloca.h: New file.
-	* common.c: Include it.
-	* Makefile.in (common.o): Add dependency.
-
-	* config.in (HAVE_TIME_H,HAVE_SYS_RESOURCE_H): Add.
-	(HAVE_GETRUSAGE,HAVE_TIME): Add.
-	* configure.in: sinclude ../common/aclocal.m4.
-	Check for headers time.h, sys/resource.h.
-	Check for functions time, getrusage.
-	(sim_link_{files,links}): Add link cpu-opc.h.
-	(sim_profile): Add simcache.
-	(SIM_AC_PROFILE): Add simcache, profile.o.
-	(simcache module): Delete extr-cache.o for now.
-	(--enable-sim-cache): Allow specification of default cache size.
-	* configure: Regenerated.
-
-	* decode.c: #include cgen-sim.h,memops.h,semops.h,decode.h,
-	cpu-sim.h,cpu-opc.h.  Don't include m32r-sim.h.
-	Regenerate.
-
-	* extract.c: #include cgen-sim.h,decode.h,cpu-sim.h.
-	Don't include m32r-sim.h.
-	(*): Define/Undef FLD macro.  Use it to reference ARGBUF.
-	Simplify profiling test with PROFILE_MODEL_P.
-	(mvfc,mvtc): Fix access of control registers.
-	* semantic.c: #include cgen-sim.h,memops.h,semops.h,decode.h,cpu-sim.h.
-	Don't include m32r-sim.h.
-	(*): Define/Undef FLD macro.  Use it to reference ARGBUF.
-	Simplify profiling test with PROFILE_MODEL_P.
-	(mvfc,mvtc): Fix access of control registers.
-
-	* sem-switch.c: New file, for GCC computed goto support.
-
-	* genmloop.sh: Add #include's of bfd.h,callback.h,cgen-sim.h,
-	memops.h,semops.h,trace.h,cpu-sim.h.
-	(RUN_FAST_P): Change default to run fast if cache size > 0
-	and not profiling.
-	(sim_main_loop): Record execution time.
-	Record instruction count even in fast mode.
-	(init): Allow cpu to provide init code in mainloop.in.
-	(FAST): Define as 0 or 1 depending on fast mode.
-	* mainloop.in (normal): Combine with fast case.
-	Add support for GCC computed gotos.  Count simcache hits/misses.
-	(init): Initialize "switch" labels if GNUC.
-
-	* cgen-utils.in: Don't include opcode/cgen.h.
-	Include cgen-sim.h, cpu-opc.h.
-	* common.c: Don't include simcommon.h,mod-list.h.  Include cgen-sim.h.
-	* m32r-sim.h: Don't include mod-list.h
-	(RUN_FAST_P): Delete.
-	* m32r.c: Don't include profile.h.  #include ansidecl.h,cgen-sim.h,
-	semops.h,memory.h,trace.h
-	(h_cr_get,h_cr_set): New functions.
-	* memory.c: #include cgen-sim.h,callback.h.
-	* ops.c: Don't include profile.h,m32r-sim.h.
-	Include cgen-sim.h,memops.h,cpu-sim.h.
-	(MEMOPS_DEFINE_INLINE): Renamed from SIMFNS_DEFINE_INLINE.
-	* trace.c: Include cgen-sim.h,cpu-opc.h.
-	* trace.h (trace_insn_{init,fini}): Declare.
-
-	* model.c: Don't include signal.h,stdlib.h,m32r-sim.h.
-	Include cgen-sim.h,cpu-sim.h,cpu-opc.h.
-	Regenerate to get new insn aliases.
-
-	* mrun.c: #include "ansidecl.h".
-	(STATE): Use struct sim_state instead.
-
-	* profile.c: Surround #include <stdlib.h> with HAVE_STDLIB_H.
-	Don't include simcommon.h.  Include cgen-sim.h,cpu-opc.h.
-	(PROFILE_{READ,WRITE}_MASK): Replace with PROFILE_MEMORY_MASK.
-	(profile_print_simcache): New function.
-	(profile_print): Call it.  Print simulator speed stats.
-	* profile.h (PROFILE_{READ,WRITE}_MASK): Replace with
-	PROFILE_MEMORY_MASK.
-	(MODULE_PROFILE_SIMCACHE_P): Define.
-	(PROFILE_SIMCACHE_MASK): Define.
-	(PROFILE_COUNT): New members total_insn_count,exec_time.
-	New members simcache_hits,simcache_misses.
-	(PROFILE_SIMCACHE_{HITS,MISSES}): Define.
-	(PROFILE_MODEL_P): New macro.
-	(PROFILE_COUNT_SIMCACHE_{HIT,MISS}): New macros.
-
-	* sim-if.c: Surround #include <stdlib.h> with HAVE_STDLIB_H.
-	Don't include simcommon.h,m32r-sim.h.  Include cgen-sim.h,cpu-sim.h.
-	(sim_resume): Use USING_SIMCACHE_P instead of RUN_FAST_P.
-	(sim_info): Pass verbose to profile_print.
-
-	* simcache.c: Include cgen-sim.h,callback.h.
-	(USING_SIMCACHE_P): Replace with SIMCACHE_P.
-	(simcache_option_handler): Ensure cache size at least 2.
-	Allow config time specification of default cache size.
-	* simcache.h (struct simcache): Support GCC computed gotos.
-	(SIMCACHE_DEFAULT_CACHE_SIZE): USe CONFIG_SIM_CACHE_SIZE if defined.
-	(USING_SIMCACHE_P): New macro.
-
-	* simdefs.h: Don't include m32r-opc.h.
-	(CGEN_MAX_SIM_INSNS): Define.
-	(CPU_STATE): Regenerate.
-	(ARGBUF): Regenerate.
-	(extract,semantic handler decls): Delete, moved to decode.h.
-
-	* tconfig.in: Don't include cgen-sim.h,m32r-sim.h.
-	(USE_SEM_SWITCH): Define.
-
-	* utils.c: Include bfd.h,time.h,sys/resource.h.
-	(sim_time_get,sim_time_elapsed): New functions.
-	* cgen-sim.h (SIM_TIME,sim_time_get,sim_time_elapsed): Declare.
-
-Fri Jan 31 20:25:06 1997  Doug Evans  <dje@canuck.cygnus.com>
-
-	* configure.in (AC_CHECK_HEADERS): Handle i386-windows.
-	* configure: Regenerated.
-	* model.c: #include <stdlib.h>.
-	* simcache.c: #include "libiberty.h".
-	* simcommon.h (alloca): Handle i386-windows.
-
-	* common.c: #include libiberty.h.
-	(sim_signal_to_host): Return 5 if wingdb.
-
-Mon Jan 27 15:22:49 1997  Doug Evans  <dje@seba.cygnus.com>
-
-	* configure.in (sim_cache): Enabled by default now, pass default
-	cache size to --enable-sim-cache.
-	* simcache.c (simcache_option_handler): Allow -c 0.
-
-	* simdefs.h,simfns.h: Regenerate
-	* decode.c,extract.c,model.c,ops.c,semantics.c: Regenerate.
-
-Tue Jan 21 16:21:01 1997  Doug Evans  <dje@seba.cygnus.com>
-
-	Add model profiling support.
-	* configure.in: Handle --enable-sim-model.
-	(sim_profile): Add model.
-	* Makefile.in (model.o): Add rule.
-	* cgen-sim.h (UNIT,INSN_TIMING,MACH,MODEL): New types.
-	* extract.c (*): Add model profiling support.
-	* m32r.c (model_mark_{get,set}_h_gr): New functions.
-	(model_mark_{busy,unbusy}_reg): New functions.
-	* profile.c (profile_option_handler): Recognize --profile model.
-	(profile_print_model): New function.
-	(profile_print): Call it.
-	* profile.h (MODULE_profile_model,MODULE_PROFILE_MODEL_P): Define.
-	(PROFILE_MODEL_MASK,PROFILE_LABEL_WIDTH): Define.
-	(PROFILE_COUNT): New members cycle_count,cti_stall_count,
-	load_stall_count,taken_count,untaken_count.
-	* semantics.c (*): Add model profiling support.
-	* simcommon.h (struct sim_state): New members mach,model.
-	* simdefs.h (CPU_PROFILE,MODEL_TYPE,UNIT_TYPE): New type.
-	(MAX_MODELS,MAX_UNITS): Define.
-	* tconfig.in (STATE_EXTRA_MEMBERS): Add cpu_profile.
-
-	* Makefile.in (INCLUDE_DEPS): Add $(SIM_MODULES_HDRS).
-	(stamp-modules): Depend on genmodlist.sh.
-	* common.c (standard_options): Add --max-insns.
-	(copy_argv): New function.
-	* tconfig.in (SIM_HAVE_MAX_INSNS): Define.
-	* genmloop.sh: Allow mainloop.in to contain support code.
-	* mainloop.in: Move do_insn16,do_insn32 here.
-	* m32r.c (do_trap): Handle SYS_argvlen,SYS_argv,SYS_read.
-	* sim-if.c (sim_open): Don't set max insn count.
-	(sim_create_inferior): Save argv,envp.
-	* simcommon.h (struct sim_state): New members argv,envp.
-	* simdefs.h ([GS]ETTWI,[GS]ETTUWI,[GS]ETTAI): Define.
-	([GS]ETMEMWI,[GS]ETMEMUWI,[GS]ETMEMAI): Define.
-	(ARGBUF): New members h_gr_get, h_gr_set.
-	* trace.c (trace_insn_init,trace_insn_fini): New functions.
-	(trace_printf): Print to buffer, output later by trace_insn_fini.
-	* trace.h (TRACE_INSN_{INIT,FINI}): Define.
-
-Thu Dec 19 16:01:59 1996  Doug Evans  <dje@canuck.cygnus.com>
-
-	* configure.in (AC_FUNC_ALLOCA): Call.
-	* configure: Regenerate.
-	* config.h (HAVE_ALLOCA_H): Add.
-	* simcommon.h: Add alloca support.
-	(DECLARE_MODULE_INSTALL_HANDLER): Define.
-	(DECLARE_OPTION_HANDLER): Define.
-	(MEM_FN): Declare using PARAMS.
-	(DECLARE_MEM_FN): Define.
-	* trace.c (trace_result): Tweak for !STDC.
-	* cgen-sim.h (UDI_FN_SUPPORT): Define if ! HAVE_LONGLONG.
-	* cgen-utils.in (disasm_sprintf): Fix va_arg call in !STDC case.
-	* common.c (sim_print_help_fn): Use PARAMS.
-	(standard_option_handler): Fix decl for !STDC systems.
-	* memory.c: #include <stdio.h>
-	(mem_flat_{install,init,uninstall}): Fix decl for !STDC systems.
-	(mem_flat_{read,write},mem_flat_option_handler): Likewise.
-	* profile.c (profile_install): Likewise.
-	(profile_option_handler): Likewise.
-
-Thu Dec 19 11:06:19 1996  Doug Evans  <dje@seba.cygnus.com>
-
-	* semantics.c (*): Don't suffix big unsigned numbers with "U".
-	Prefix them with 0x instead.
-
-	* cgen-sim.h (DI_FN_SUPPORT): Define if ! HAVE_LONGLONG.
-	(SLADI,SRADI,CONVSIDI,CONVDISI): Delete, moved to simfns.h.
-	* semantics.c (machi,maclo,macwhi,macwlo,mulhi,mullo): Implement.
-	(mulwhi,mulwlo,mvtachi,mvtaclo,rac,rach): Implement.
-	* simfns.h: Add decls for functional DI,UDI,SF,DF,XF,TF support.
-	Add support for boolean and/or.
-	* utils.c: Redo naming of DI functional support.
-	(ANDDI,ORDI,ADDDI,MULDI,GEDI,LEDI,CONVHIDI): New functions.
-
-Tue Dec 17 12:57:48 1996  Doug Evans  <dje@seba.cygnus.com>
-
-	* Directory created.
diff --git a/sim/m32r/Makefile.in b/sim/m32r/Makefile.in
deleted file mode 100644
index 75c2853..0000000
--- a/sim/m32r/Makefile.in
+++ /dev/null
@@ -1,159 +0,0 @@
-# Makefile template for Configure for the m32r simulator
-# Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
-# Contributed by Cygnus Support.
-#
-# This file is part of GDB, the GNU debugger.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License along
-# with this program; if not, write to the Free Software Foundation, Inc.,
-# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-## COMMON_PRE_CONFIG_FRAG
-
-M32R_OBJS = m32r.o cpu.o decode.o sem.o model.o mloop.o
-# start-sanitize-cygnus
-M32RX_OBJS = m32rx.o cpux.o decodex.o modelx.o mloopx.o
-# end-sanitize-cygnus
-
-CONFIG_DEVICES = dv-sockser.o
-CONFIG_DEVICES =
-
-SIM_OBJS = \
-	$(SIM_NEW_COMMON_OBJS) \
-	sim-cpu.o \
-	sim-hload.o \
-	sim-hrw.o \
-	sim-model.o \
-	sim-reg.o \
-	cgen-utils.o cgen-trace.o cgen-scache.o \
-	cgen-run.o sim-reason.o sim-engine.o sim-stop.o \
-	sim-if.o arch.o \
-	$(M32R_OBJS) \
-	$(start-sanitize-cygnus) \
-	$(M32RX_OBJS) \
-	$(end-sanitize-cygnus) \
-	traps.o devices.o \
-	$(CONFIG_DEVICES)
-
-# Extra headers included by sim-main.h.
-SIM_EXTRA_DEPS = \
-	$(CGEN_INCLUDE_DEPS) \
-	arch.h cpuall.h m32r-sim.h $(srcdir)/../../opcodes/m32r-desc.h
-
-SIM_EXTRA_CFLAGS =
-
-SIM_RUN_OBJS = nrun.o
-SIM_EXTRA_CLEAN = m32r-clean
-
-# This selects the m32r newlib/libgloss syscall definitions.
-NL_TARGET = -DNL_TARGET_m32r
-
-## COMMON_POST_CONFIG_FRAG
-
-arch = m32r
-
-sim-if.o: sim-if.c $(SIM_MAIN_DEPS) $(srcdir)/../common/sim-core.h
-
-arch.o: arch.c $(SIM_MAIN_DEPS)
-
-traps.o: traps.c targ-vals.h $(SIM_MAIN_DEPS)
-devices.o: devices.c $(SIM_MAIN_DEPS)
-
-# M32R objs
-
-M32RBF_INCLUDE_DEPS = \
-	$(CGEN_MAIN_CPU_DEPS) \
-	cpu.h decode.h eng.h
-
-m32r.o: m32r.c $(M32RBF_INCLUDE_DEPS)
-
-# FIXME: Use of `mono' is wip.
-mloop.c eng.h: stamp-mloop
-stamp-mloop: $(srcdir)/../common/genmloop.sh mloop.in Makefile
-	$(SHELL) $(srccom)/genmloop.sh \
-		-mono -fast -pbb -switch sem-switch.c \
-		-cpu m32rbf -infile $(srcdir)/mloop.in
-	$(SHELL) $(srcroot)/move-if-change eng.hin eng.h
-	$(SHELL) $(srcroot)/move-if-change mloop.cin mloop.c
-	touch stamp-mloop
-mloop.o: mloop.c sem-switch.c $(M32RBF_INCLUDE_DEPS)
-
-cpu.o: cpu.c $(M32RBF_INCLUDE_DEPS)
-decode.o: decode.c $(M32RBF_INCLUDE_DEPS)
-sem.o: sem.c $(M32RBF_INCLUDE_DEPS)
-model.o: model.c $(M32RBF_INCLUDE_DEPS)
-
-# start-sanitize-cygnus
-# M32RX objs
-
-M32RXF_INCLUDE_DEPS = \
-	$(CGEN_MAIN_CPU_DEPS) \
-	cpux.h decodex.h engx.h
-
-m32rx.o: m32rx.c $(M32RXF_INCLUDE_DEPS)
-
-# FIXME: Use of `mono' is wip.
-mloopx.c engx.h: stamp-xmloop
-stamp-xmloop: $(srcdir)/../common/genmloop.sh mloopx.in Makefile
-	$(SHELL) $(srccom)/genmloop.sh \
-		-mono -no-fast -pbb -parallel-write -switch semx-switch.c \
-		-cpu m32rxf -infile $(srcdir)/mloopx.in
-	$(SHELL) $(srcroot)/move-if-change eng.hin engx.h
-	$(SHELL) $(srcroot)/move-if-change mloop.cin mloopx.c
-	touch stamp-xmloop
-mloopx.o: mloopx.c semx-switch.c $(M32RXF_INCLUDE_DEPS)
-
-cpux.o: cpux.c $(M32RXF_INCLUDE_DEPS)
-decodex.o: decodex.c $(M32RXF_INCLUDE_DEPS)
-semx.o: semx.c $(M32RXF_INCLUDE_DEPS)
-modelx.o: modelx.c $(M32RXF_INCLUDE_DEPS)
-# end-sanitize-cygnus
-
-m32r-clean:
-	rm -f mloop.c eng.h stamp-arch stamp-cpu stamp-mloop
-# start-sanitize-cygnus
-	rm -f mloopx.c engx.h stamp-xcpu stamp-xmloop
-# end-sanitize-cygnus
-	rm -f tmp-*
-
-# start-sanitize-cygnus
-# cgen support, enable with --enable-cgen-maint
-CGEN_MAINT = ; @true
-# The following line is commented in or out depending upon --enable-cgen-maint.
-@CGEN_MAINT@CGEN_MAINT =
-
-stamp-arch: $(CGEN_MAIN_SCM) $(CGEN_ARCH_SCM) $(srccgen)/m32r.cpu
-	$(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) mach=all \
-	  FLAGS="with-scache with-profile=fn"
-	touch stamp-arch
-arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch
-	@true
-
-stamp-cpu: $(CGEN_MAIN_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(srccgen)/m32r.cpu
-	$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
-	  cpu=m32rbf mach=m32r SUFFIX= \
-	  FLAGS="with-scache with-profile=fn" \
-	  EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"
-	touch stamp-cpu
-cpu.h sem.c sem-switch.c model.c decode.c decode.h: $(CGEN_MAINT) stamp-cpu
-	@true
-# end-sanitize-cygnus
-
-# start-sanitize-cygnus
-stamp-xcpu: $(CGEN_MAIN_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(srccgen)/m32r.cpu
-	$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
-	  cpu=m32rxf mach=m32rx SUFFIX=x FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEMSW)"
-	touch stamp-xcpu
-cpux.h semx-switch.c modelx.c decodex.c decodex.h: $(CGEN_MAINT) stamp-xcpu
-	@true
-# end-sanitize-cygnus
diff --git a/sim/m32r/README b/sim/m32r/README
deleted file mode 100644
index a72ace5..0000000
--- a/sim/m32r/README
+++ /dev/null
@@ -1,2 +0,0 @@
-This is the m32r simulator directory.
-It is still work-in-progress.
diff --git a/sim/m32r/acconfig.h b/sim/m32r/acconfig.h
deleted file mode 100644
index f9b87a1..0000000
--- a/sim/m32r/acconfig.h
+++ /dev/null
@@ -1,15 +0,0 @@
-
-/* Define to 1 if NLS is requested.  */
-#undef ENABLE_NLS
-
-/* Define as 1 if you have catgets and don't want to use GNU gettext.  */
-#undef HAVE_CATGETS
-
-/* Define as 1 if you have gettext and don't want to use GNU gettext.  */
-#undef HAVE_GETTEXT
-
-/* Define as 1 if you have the stpcpy function.  */
-#undef HAVE_STPCPY
-
-/* Define if your locale.h file contains LC_MESSAGES.  */
-#undef HAVE_LC_MESSAGES
diff --git a/sim/m32r/arch.c b/sim/m32r/arch.c
deleted file mode 100644
index 39b9b96..0000000
--- a/sim/m32r/arch.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/* Simulator support for m32r.
-
-Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
-
-This file is part of the GNU Simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#include "sim-main.h"
-#include "cpu-sim.h"
-#include "cpu-opc.h"
-
-const MACH machs[] = {
-  { "m32r", 32, 32, & m32r_models[0], & m32r_imp_properties },
-/* start-sanitize-m32rx */
-  { "m32rx", 32, 32, & m32rx_models[0], & m32rx_imp_properties },
-/* end-sanitize-m32rx */
-  { 0 }
-};
-
diff --git a/sim/m32r/arch.h b/sim/m32r/arch.h
deleted file mode 100644
index 57a7db1..0000000
--- a/sim/m32r/arch.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/* Simulator header for m32r.
-
-This file is machine generated with CGEN.
-
-Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
-
-This file is part of the GNU Simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#ifndef M32R_ARCH_H
-#define M32R_ARCH_H
-
-#include "m32r-opc.h"
-
-#define TARGET_BIG_ENDIAN 1
-
-/* Shorthand macro for fetching registers.  */
-#define CPU(x) (CPU_CGEN_HW (current_cpu)->x)
-
-/* Enum declaration for mode types.  */
-typedef enum mode_type {
-  MODE_VM, MODE_BI, MODE_QI, MODE_HI
- , MODE_SI, MODE_DI, MODE_UBI, MODE_UQI
- , MODE_UHI, MODE_USI, MODE_UDI, MODE_SF
- , MODE_DF, MODE_XF, MODE_TF, MODE_MAX
-} MODE_TYPE;
-
-#define MAX_MODES ((int) MODE_MAX)
-
-/* Return name of instruction numbered INSN.  */
-#define INSN_NAME(insn) (m32r_cgen_insn_table_entries[insn].name)
-
-/* Enum declaration for model types.  */
-typedef enum model_type {
-  MODEL_M32R_D, MODEL_TEST, MODEL_M32RX, MODEL_MAX
-} MODEL_TYPE;
-
-#define MAX_MODELS ((int) MODEL_MAX)
-
-/* Enum declaration for unit types.  */
-typedef enum unit_type {
-  UNIT_NONE, UNIT_M32R_D_U_STORE, UNIT_M32R_D_U_LOAD, UNIT_M32R_D_U_EXEC
- , UNIT_TEST_U_EXEC, UNIT_M32RX_U_EXEC, UNIT_MAX
-} UNIT_TYPE;
-
-#define MAX_UNITS (1)
-
-#endif /* M32R_ARCH_H */
diff --git a/sim/m32r/configure b/sim/m32r/configure
deleted file mode 100755
index 20d6c7b..0000000
--- a/sim/m32r/configure
+++ /dev/null
@@ -1,4257 +0,0 @@
-#! /bin/sh
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-sim_inline="-DDEFAULT_INLINE=0"
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-# This file is derived from `gettext.m4'.  The difference is that the
-# included macros assume Cygnus-style source and build trees.
-
-# Macro to add for using GNU gettext.
-# Ulrich Drepper <drepper@cygnus.com>, 1995.
-#
-# This file file be copied and used freely without restrictions.  It can
-# be used in projects which are not available under the GNU Public License
-# but which still want to provide support for the GNU gettext functionality.
-# Please note that the actual code is *not* freely available.
-
-# serial 3
-
-
-
-
-
-# Search path for a program which passes the given test.
-# Ulrich Drepper <drepper@cygnus.com>, 1996.
-#
-# This file file be copied and used freely without restrictions.  It can
-# be used in projects which are not available under the GNU Public License
-# but which still want to provide support for the GNU gettext functionality.
-# Please note that the actual code is *not* freely available.
-
-# serial 1
-
-
-
-# Check whether LC_MESSAGES is available in <locale.h>.
-# Ulrich Drepper <drepper@cygnus.com>, 1995.
-#
-# This file file be copied and used freely without restrictions.  It can
-# be used in projects which are not available under the GNU Public License
-# but which still want to provide support for the GNU gettext functionality.
-# Please note that the actual code is *not* freely available.
-
-# serial 1
-
-
-
-# Check to see if we're running under Cygwin32, without using
-# AC_CANONICAL_*.  If so, set output variable CYGWIN32 to "yes".
-# Otherwise set it to "no".
-
-
-
-# Check to see if we're running under Win32, without using
-# AC_CANONICAL_*.  If so, set output variable EXEEXT to ".exe".
-# Otherwise set it to "".
-
-
-
-
-# Guess values for system-dependent variables and create Makefiles.
-# Generated automatically using autoconf version 2.12.2 
-# Copyright (C) 1992, 93, 94, 95, 96 Free Software Foundation, Inc.
-#
-# This configure script is free software; the Free Software Foundation
-# gives unlimited permission to copy, distribute and modify it.
-
-# Defaults:
-ac_help=
-ac_default_prefix=/usr/local
-# Any additions from configure.in:
-ac_help="$ac_help
-  --disable-nls           do not use Native Language Support"
-ac_help="$ac_help
-  --with-included-gettext use the GNU gettext library included here"
-ac_help="$ac_help
-  --enable-maintainer-mode		Enable developer functionality."
-ac_help="$ac_help
-  --enable-sim-bswap			Use Host specific BSWAP instruction."
-ac_help="$ac_help
-  --enable-sim-cflags=opts		Extra CFLAGS for use in building simulator"
-ac_help="$ac_help
-  --enable-sim-debug=opts		Enable debugging flags"
-ac_help="$ac_help
-  --enable-sim-stdio			Specify whether to use stdio for console input/output."
-ac_help="$ac_help
-  --enable-sim-trace=opts		Enable tracing flags"
-ac_help="$ac_help
-  --enable-sim-profile=opts		Enable profiling flags"
-ac_help="$ac_help
-  --enable-sim-endian=endian		Specify target byte endian orientation."
-ac_help="$ac_help
-  --enable-sim-alignment=align		Specify strict,  nonstrict or forced alignment of memory accesses."
-ac_help="$ac_help
-  --enable-sim-hostendian=end		Specify host byte endian orientation."
-ac_help="$ac_help
-  --enable-sim-scache=size		Specify simulator execution cache size."
-ac_help="$ac_help
-  --enable-sim-default-model=model	Specify default model to simulate."
-ac_help="$ac_help
-  --enable-sim-environment=environment	Specify mixed, user, virtual or operating environment."
-ac_help="$ac_help
-  --enable-sim-inline=inlines		Specify which functions should be inlined."
-ac_help="$ac_help
-  --enable-cgen-maint[=dir]    build cgen generated files"
-
-# Initialize some variables set by options.
-# The variables have the same names as the options, with
-# dashes changed to underlines.
-build=NONE
-cache_file=./config.cache
-exec_prefix=NONE
-host=NONE
-no_create=
-nonopt=NONE
-no_recursion=
-prefix=NONE
-program_prefix=NONE
-program_suffix=NONE
-program_transform_name=s,x,x,
-silent=
-site=
-srcdir=
-target=NONE
-verbose=
-x_includes=NONE
-x_libraries=NONE
-bindir='${exec_prefix}/bin'
-sbindir='${exec_prefix}/sbin'
-libexecdir='${exec_prefix}/libexec'
-datadir='${prefix}/share'
-sysconfdir='${prefix}/etc'
-sharedstatedir='${prefix}/com'
-localstatedir='${prefix}/var'
-libdir='${exec_prefix}/lib'
-includedir='${prefix}/include'
-oldincludedir='/usr/include'
-infodir='${prefix}/info'
-mandir='${prefix}/man'
-
-# Initialize some other variables.
-subdirs=
-MFLAGS= MAKEFLAGS=
-SHELL=${CONFIG_SHELL-/bin/sh}
-# Maximum number of lines to put in a shell here document.
-ac_max_here_lines=12
-
-ac_prev=
-for ac_option
-do
-
-  # If the previous option needs an argument, assign it.
-  if test -n "$ac_prev"; then
-    eval "$ac_prev=\$ac_option"
-    ac_prev=
-    continue
-  fi
-
-  case "$ac_option" in
-  -*=*) ac_optarg=`echo "$ac_option" | sed 's/[-_a-zA-Z0-9]*=//'` ;;
-  *) ac_optarg= ;;
-  esac
-
-  # Accept the important Cygnus configure options, so we can diagnose typos.
-
-  case "$ac_option" in
-
-  -bindir | --bindir | --bindi | --bind | --bin | --bi)
-    ac_prev=bindir ;;
-  -bindir=* | --bindir=* | --bindi=* | --bind=* | --bin=* | --bi=*)
-    bindir="$ac_optarg" ;;
-
-  -build | --build | --buil | --bui | --bu)
-    ac_prev=build ;;
-  -build=* | --build=* | --buil=* | --bui=* | --bu=*)
-    build="$ac_optarg" ;;
-
-  -cache-file | --cache-file | --cache-fil | --cache-fi \
-  | --cache-f | --cache- | --cache | --cach | --cac | --ca | --c)
-    ac_prev=cache_file ;;
-  -cache-file=* | --cache-file=* | --cache-fil=* | --cache-fi=* \
-  | --cache-f=* | --cache-=* | --cache=* | --cach=* | --cac=* | --ca=* | --c=*)
-    cache_file="$ac_optarg" ;;
-
-  -datadir | --datadir | --datadi | --datad | --data | --dat | --da)
-    ac_prev=datadir ;;
-  -datadir=* | --datadir=* | --datadi=* | --datad=* | --data=* | --dat=* \
-  | --da=*)
-    datadir="$ac_optarg" ;;
-
-  -disable-* | --disable-*)
-    ac_feature=`echo $ac_option|sed -e 's/-*disable-//'`
-    # Reject names that are not valid shell variable names.
-    if test -n "`echo $ac_feature| sed 's/[-a-zA-Z0-9_]//g'`"; then
-      { echo "configure: error: $ac_feature: invalid feature name" 1>&2; exit 1; }
-    fi
-    ac_feature=`echo $ac_feature| sed 's/-/_/g'`
-    eval "enable_${ac_feature}=no" ;;
-
-  -enable-* | --enable-*)
-    ac_feature=`echo $ac_option|sed -e 's/-*enable-//' -e 's/=.*//'`
-    # Reject names that are not valid shell variable names.
-    if test -n "`echo $ac_feature| sed 's/[-_a-zA-Z0-9]//g'`"; then
-      { echo "configure: error: $ac_feature: invalid feature name" 1>&2; exit 1; }
-    fi
-    ac_feature=`echo $ac_feature| sed 's/-/_/g'`
-    case "$ac_option" in
-      *=*) ;;
-      *) ac_optarg=yes ;;
-    esac
-    eval "enable_${ac_feature}='$ac_optarg'" ;;
-
-  -exec-prefix | --exec_prefix | --exec-prefix | --exec-prefi \
-  | --exec-pref | --exec-pre | --exec-pr | --exec-p | --exec- \
-  | --exec | --exe | --ex)
-    ac_prev=exec_prefix ;;
-  -exec-prefix=* | --exec_prefix=* | --exec-prefix=* | --exec-prefi=* \
-  | --exec-pref=* | --exec-pre=* | --exec-pr=* | --exec-p=* | --exec-=* \
-  | --exec=* | --exe=* | --ex=*)
-    exec_prefix="$ac_optarg" ;;
-
-  -gas | --gas | --ga | --g)
-    # Obsolete; use --with-gas.
-    with_gas=yes ;;
-
-  -help | --help | --hel | --he)
-    # Omit some internal or obsolete options to make the list less imposing.
-    # This message is too long to be a string in the A/UX 3.1 sh.
-    cat << EOF
-Usage: configure [options] [host]
-Options: [defaults in brackets after descriptions]
-Configuration:
-  --cache-file=FILE       cache test results in FILE
-  --help                  print this message
-  --no-create             do not create output files
-  --quiet, --silent       do not print \`checking...' messages
-  --version               print the version of autoconf that created configure
-Directory and file names:
-  --prefix=PREFIX         install architecture-independent files in PREFIX
-                          [$ac_default_prefix]
-  --exec-prefix=EPREFIX   install architecture-dependent files in EPREFIX
-                          [same as prefix]
-  --bindir=DIR            user executables in DIR [EPREFIX/bin]
-  --sbindir=DIR           system admin executables in DIR [EPREFIX/sbin]
-  --libexecdir=DIR        program executables in DIR [EPREFIX/libexec]
-  --datadir=DIR           read-only architecture-independent data in DIR
-                          [PREFIX/share]
-  --sysconfdir=DIR        read-only single-machine data in DIR [PREFIX/etc]
-  --sharedstatedir=DIR    modifiable architecture-independent data in DIR
-                          [PREFIX/com]
-  --localstatedir=DIR     modifiable single-machine data in DIR [PREFIX/var]
-  --libdir=DIR            object code libraries in DIR [EPREFIX/lib]
-  --includedir=DIR        C header files in DIR [PREFIX/include]
-  --oldincludedir=DIR     C header files for non-gcc in DIR [/usr/include]
-  --infodir=DIR           info documentation in DIR [PREFIX/info]
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-EOF
-if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
-  egrep "memchr" >/dev/null 2>&1; then
-  :
-else
-  rm -rf conftest*
-  ac_cv_header_stdc=no
-fi
-rm -f conftest*
-
-fi
-
-if test $ac_cv_header_stdc = yes; then
-  # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI.
-cat > conftest.$ac_ext <<EOF
-#line 869 "configure"
-#include "confdefs.h"
-#include <stdlib.h>
-EOF
-if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
-  egrep "free" >/dev/null 2>&1; then
-  :
-else
-  rm -rf conftest*
-  ac_cv_header_stdc=no
-fi
-rm -f conftest*
-
-fi
-
-if test $ac_cv_header_stdc = yes; then
-  # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi.
-if test "$cross_compiling" = yes; then
-  :
-else
-  cat > conftest.$ac_ext <<EOF
-#line 890 "configure"
-#include "confdefs.h"
-#include <ctype.h>
-#define ISLOWER(c) ('a' <= (c) && (c) <= 'z')
-#define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c))
-#define XOR(e, f) (((e) && !(f)) || (!(e) && (f)))
-int main () { int i; for (i = 0; i < 256; i++)
-if (XOR (islower (i), ISLOWER (i)) || toupper (i) != TOUPPER (i)) exit(2);
-exit (0); }
-
-EOF
-if { (eval echo configure:901: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
-then
-  :
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -fr conftest*
-  ac_cv_header_stdc=no
-fi
-rm -fr conftest*
-fi
-
-fi
-fi
-
-echo "$ac_t""$ac_cv_header_stdc" 1>&6
-if test $ac_cv_header_stdc = yes; then
-  cat >> confdefs.h <<\EOF
-#define STDC_HEADERS 1
-EOF
-
-fi
-
-echo $ac_n "checking for working const""... $ac_c" 1>&6
-echo "configure:925: checking for working const" >&5
-if eval "test \"`echo '$''{'ac_cv_c_const'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 930 "configure"
-#include "confdefs.h"
-
-int main() {
-
-/* Ultrix mips cc rejects this.  */
-typedef int charset[2]; const charset x;
-/* SunOS 4.1.1 cc rejects this.  */
-char const *const *ccp;
-char **p;
-/* NEC SVR4.0.2 mips cc rejects this.  */
-struct point {int x, y;};
-static struct point const zero = {0,0};
-/* AIX XL C 1.02.0.0 rejects this.
-   It does not let you subtract one const X* pointer from another in an arm
-   of an if-expression whose if-part is not a constant expression */
-const char *g = "string";
-ccp = &g + (g ? g-g : 0);
-/* HPUX 7.0 cc rejects these. */
-++ccp;
-p = (char**) ccp;
-ccp = (char const *const *) p;
-{ /* SCO 3.2v4 cc rejects this.  */
-  char *t;
-  char const *s = 0 ? (char *) 0 : (char const *) 0;
-
-  *t++ = 0;
-}
-{ /* Someone thinks the Sun supposedly-ANSI compiler will reject this.  */
-  int x[] = {25, 17};
-  const int *foo = &x[0];
-  ++foo;
-}
-{ /* Sun SC1.0 ANSI compiler rejects this -- but not the above. */
-  typedef const int *iptr;
-  iptr p = 0;
-  ++p;
-}
-{ /* AIX XL C 1.02.0.0 rejects this saying
-     "k.c", line 2.27: 1506-025 (S) Operand must be a modifiable lvalue. */
-  struct s { int j; const int *ap[3]; };
-  struct s *b; b->j = 5;
-}
-{ /* ULTRIX-32 V3.1 (Rev 9) vcc rejects this */
-  const int foo = 10;
-}
-
-; return 0; }
-EOF
-if { (eval echo configure:979: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
-  rm -rf conftest*
-  ac_cv_c_const=yes
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  ac_cv_c_const=no
-fi
-rm -f conftest*
-fi
-
-echo "$ac_t""$ac_cv_c_const" 1>&6
-if test $ac_cv_c_const = no; then
-  cat >> confdefs.h <<\EOF
-#define const 
-EOF
-
-fi
-
-echo $ac_n "checking for inline""... $ac_c" 1>&6
-echo "configure:1000: checking for inline" >&5
-if eval "test \"`echo '$''{'ac_cv_c_inline'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  ac_cv_c_inline=no
-for ac_kw in inline __inline__ __inline; do
-  cat > conftest.$ac_ext <<EOF
-#line 1007 "configure"
-#include "confdefs.h"
-
-int main() {
-} $ac_kw foo() {
-; return 0; }
-EOF
-if { (eval echo configure:1014: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
-  rm -rf conftest*
-  ac_cv_c_inline=$ac_kw; break
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-fi
-rm -f conftest*
-done
-
-fi
-
-echo "$ac_t""$ac_cv_c_inline" 1>&6
-case "$ac_cv_c_inline" in
-  inline | yes) ;;
-  no) cat >> confdefs.h <<\EOF
-#define inline 
-EOF
- ;;
-  *)  cat >> confdefs.h <<EOF
-#define inline $ac_cv_c_inline
-EOF
- ;;
-esac
-
-echo $ac_n "checking for off_t""... $ac_c" 1>&6
-echo "configure:1040: checking for off_t" >&5
-if eval "test \"`echo '$''{'ac_cv_type_off_t'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 1045 "configure"
-#include "confdefs.h"
-#include <sys/types.h>
-#if STDC_HEADERS
-#include <stdlib.h>
-#include <stddef.h>
-#endif
-EOF
-if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
-  egrep "off_t[^a-zA-Z_0-9]" >/dev/null 2>&1; then
-  rm -rf conftest*
-  ac_cv_type_off_t=yes
-else
-  rm -rf conftest*
-  ac_cv_type_off_t=no
-fi
-rm -f conftest*
-
-fi
-echo "$ac_t""$ac_cv_type_off_t" 1>&6
-if test $ac_cv_type_off_t = no; then
-  cat >> confdefs.h <<\EOF
-#define off_t long
-EOF
-
-fi
-
-echo $ac_n "checking for size_t""... $ac_c" 1>&6
-echo "configure:1073: checking for size_t" >&5
-if eval "test \"`echo '$''{'ac_cv_type_size_t'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 1078 "configure"
-#include "confdefs.h"
-#include <sys/types.h>
-#if STDC_HEADERS
-#include <stdlib.h>
-#include <stddef.h>
-#endif
-EOF
-if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
-  egrep "size_t[^a-zA-Z_0-9]" >/dev/null 2>&1; then
-  rm -rf conftest*
-  ac_cv_type_size_t=yes
-else
-  rm -rf conftest*
-  ac_cv_type_size_t=no
-fi
-rm -f conftest*
-
-fi
-echo "$ac_t""$ac_cv_type_size_t" 1>&6
-if test $ac_cv_type_size_t = no; then
-  cat >> confdefs.h <<\EOF
-#define size_t unsigned
-EOF
-
-fi
-
-# The Ultrix 4.2 mips builtin alloca declared by alloca.h only works
-# for constant arguments.  Useless!
-echo $ac_n "checking for working alloca.h""... $ac_c" 1>&6
-echo "configure:1108: checking for working alloca.h" >&5
-if eval "test \"`echo '$''{'ac_cv_header_alloca_h'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 1113 "configure"
-#include "confdefs.h"
-#include <alloca.h>
-int main() {
-char *p = alloca(2 * sizeof(int));
-; return 0; }
-EOF
-if { (eval echo configure:1120: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  rm -rf conftest*
-  ac_cv_header_alloca_h=yes
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  ac_cv_header_alloca_h=no
-fi
-rm -f conftest*
-fi
-
-echo "$ac_t""$ac_cv_header_alloca_h" 1>&6
-if test $ac_cv_header_alloca_h = yes; then
-  cat >> confdefs.h <<\EOF
-#define HAVE_ALLOCA_H 1
-EOF
-
-fi
-
-echo $ac_n "checking for alloca""... $ac_c" 1>&6
-echo "configure:1141: checking for alloca" >&5
-if eval "test \"`echo '$''{'ac_cv_func_alloca_works'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 1146 "configure"
-#include "confdefs.h"
-
-#ifdef __GNUC__
-# define alloca __builtin_alloca
-#else
-# ifdef _MSC_VER
-#  include <malloc.h>
-#  define alloca _alloca
-# else
-#  if HAVE_ALLOCA_H
-#   include <alloca.h>
-#  else
-#   ifdef _AIX
- #pragma alloca
-#   else
-#    ifndef alloca /* predefined by HP cc +Olibcalls */
-char *alloca ();
-#    endif
-#   endif
-#  endif
-# endif
-#endif
-
-int main() {
-char *p = (char *) alloca(1);
-; return 0; }
-EOF
-if { (eval echo configure:1174: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  rm -rf conftest*
-  ac_cv_func_alloca_works=yes
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  ac_cv_func_alloca_works=no
-fi
-rm -f conftest*
-fi
-
-echo "$ac_t""$ac_cv_func_alloca_works" 1>&6
-if test $ac_cv_func_alloca_works = yes; then
-  cat >> confdefs.h <<\EOF
-#define HAVE_ALLOCA 1
-EOF
-
-fi
-
-if test $ac_cv_func_alloca_works = no; then
-  # The SVR3 libPW and SVR4 libucb both contain incompatible functions
-  # that cause trouble.  Some versions do not even contain alloca or
-  # contain a buggy version.  If you still want to use their alloca,
-  # use ar to extract alloca.o from them instead of compiling alloca.c.
-  ALLOCA=alloca.${ac_objext}
-  cat >> confdefs.h <<\EOF
-#define C_ALLOCA 1
-EOF
-
-
-echo $ac_n "checking whether alloca needs Cray hooks""... $ac_c" 1>&6
-echo "configure:1206: checking whether alloca needs Cray hooks" >&5
-if eval "test \"`echo '$''{'ac_cv_os_cray'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 1211 "configure"
-#include "confdefs.h"
-#if defined(CRAY) && ! defined(CRAY2)
-webecray
-#else
-wenotbecray
-#endif
-
-EOF
-if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
-  egrep "webecray" >/dev/null 2>&1; then
-  rm -rf conftest*
-  ac_cv_os_cray=yes
-else
-  rm -rf conftest*
-  ac_cv_os_cray=no
-fi
-rm -f conftest*
-
-fi
-
-echo "$ac_t""$ac_cv_os_cray" 1>&6
-if test $ac_cv_os_cray = yes; then
-for ac_func in _getb67 GETB67 getb67; do
-  echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:1236: checking for $ac_func" >&5
-if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 1241 "configure"
-#include "confdefs.h"
-/* System header to define __stub macros and hopefully few prototypes,
-    which can conflict with char $ac_func(); below.  */
-#include <assert.h>
-/* Override any gcc2 internal prototype to avoid an error.  */
-/* We use char because int might match the return type of a gcc2
-    builtin and then its argument prototype would still apply.  */
-char $ac_func();
-
-int main() {
-
-/* The GNU C library defines this for functions which it implements
-    to always fail with ENOSYS.  Some functions are actually named
-    something starting with __ and the normal name is an alias.  */
-#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
-choke me
-#else
-$ac_func();
-#endif
-
-; return 0; }
-EOF
-if { (eval echo configure:1264: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  rm -rf conftest*
-  eval "ac_cv_func_$ac_func=yes"
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_func_$ac_func=no"
-fi
-rm -f conftest*
-fi
-
-if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-  cat >> confdefs.h <<EOF
-#define CRAY_STACKSEG_END $ac_func
-EOF
-
-  break
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-done
-fi
-
-echo $ac_n "checking stack direction for C alloca""... $ac_c" 1>&6
-echo "configure:1291: checking stack direction for C alloca" >&5
-if eval "test \"`echo '$''{'ac_cv_c_stack_direction'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  if test "$cross_compiling" = yes; then
-  ac_cv_c_stack_direction=0
-else
-  cat > conftest.$ac_ext <<EOF
-#line 1299 "configure"
-#include "confdefs.h"
-find_stack_direction ()
-{
-  static char *addr = 0;
-  auto char dummy;
-  if (addr == 0)
-    {
-      addr = &dummy;
-      return find_stack_direction ();
-    }
-  else
-    return (&dummy > addr) ? 1 : -1;
-}
-main ()
-{
-  exit (find_stack_direction() < 0);
-}
-EOF
-if { (eval echo configure:1318: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
-then
-  ac_cv_c_stack_direction=1
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -fr conftest*
-  ac_cv_c_stack_direction=-1
-fi
-rm -fr conftest*
-fi
-
-fi
-
-echo "$ac_t""$ac_cv_c_stack_direction" 1>&6
-cat >> confdefs.h <<EOF
-#define STACK_DIRECTION $ac_cv_c_stack_direction
-EOF
-
-fi
-
-for ac_hdr in unistd.h
-do
-ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
-echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
-echo "configure:1343: checking for $ac_hdr" >&5
-if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 1348 "configure"
-#include "confdefs.h"
-#include <$ac_hdr>
-EOF
-ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:1353: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
-ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
-if test -z "$ac_err"; then
-  rm -rf conftest*
-  eval "ac_cv_header_$ac_safe=yes"
-else
-  echo "$ac_err" >&5
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_header_$ac_safe=no"
-fi
-rm -f conftest*
-fi
-if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-    ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'`
-  cat >> confdefs.h <<EOF
-#define $ac_tr_hdr 1
-EOF
- 
-else
-  echo "$ac_t""no" 1>&6
-fi
-done
-
-for ac_func in getpagesize
-do
-echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:1382: checking for $ac_func" >&5
-if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 1387 "configure"
-#include "confdefs.h"
-/* System header to define __stub macros and hopefully few prototypes,
-    which can conflict with char $ac_func(); below.  */
-#include <assert.h>
-/* Override any gcc2 internal prototype to avoid an error.  */
-/* We use char because int might match the return type of a gcc2
-    builtin and then its argument prototype would still apply.  */
-char $ac_func();
-
-int main() {
-
-/* The GNU C library defines this for functions which it implements
-    to always fail with ENOSYS.  Some functions are actually named
-    something starting with __ and the normal name is an alias.  */
-#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
-choke me
-#else
-$ac_func();
-#endif
-
-; return 0; }
-EOF
-if { (eval echo configure:1410: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  rm -rf conftest*
-  eval "ac_cv_func_$ac_func=yes"
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_func_$ac_func=no"
-fi
-rm -f conftest*
-fi
-
-if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-    ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
-  cat >> confdefs.h <<EOF
-#define $ac_tr_func 1
-EOF
- 
-else
-  echo "$ac_t""no" 1>&6
-fi
-done
-
-echo $ac_n "checking for working mmap""... $ac_c" 1>&6
-echo "configure:1435: checking for working mmap" >&5
-if eval "test \"`echo '$''{'ac_cv_func_mmap_fixed_mapped'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  if test "$cross_compiling" = yes; then
-  ac_cv_func_mmap_fixed_mapped=no
-else
-  cat > conftest.$ac_ext <<EOF
-#line 1443 "configure"
-#include "confdefs.h"
-
-/* Thanks to Mike Haertel and Jim Avera for this test.
-   Here is a matrix of mmap possibilities:
-	mmap private not fixed
-	mmap private fixed at somewhere currently unmapped
-	mmap private fixed at somewhere already mapped
-	mmap shared not fixed
-	mmap shared fixed at somewhere currently unmapped
-	mmap shared fixed at somewhere already mapped
-   For private mappings, we should verify that changes cannot be read()
-   back from the file, nor mmap's back from the file at a different
-   address.  (There have been systems where private was not correctly
-   implemented like the infamous i386 svr4.0, and systems where the
-   VM page cache was not coherent with the filesystem buffer cache
-   like early versions of FreeBSD and possibly contemporary NetBSD.)
-   For shared mappings, we should conversely verify that changes get
-   propogated back to all the places they're supposed to be.
-
-   Grep wants private fixed already mapped.
-   The main things grep needs to know about mmap are:
-   * does it exist and is it safe to write into the mmap'd area
-   * how to use it (BSD variants)  */
-#include <sys/types.h>
-#include <fcntl.h>
-#include <sys/mman.h>
-
-/* This mess was copied from the GNU getpagesize.h.  */
-#ifndef HAVE_GETPAGESIZE
-# ifdef HAVE_UNISTD_H
-#  include <unistd.h>
-# endif
-
-/* Assume that all systems that can run configure have sys/param.h.  */
-# ifndef HAVE_SYS_PARAM_H
-#  define HAVE_SYS_PARAM_H 1
-# endif
-
-# ifdef _SC_PAGESIZE
-#  define getpagesize() sysconf(_SC_PAGESIZE)
-# else /* no _SC_PAGESIZE */
-#  ifdef HAVE_SYS_PARAM_H
-#   include <sys/param.h>
-#   ifdef EXEC_PAGESIZE
-#    define getpagesize() EXEC_PAGESIZE
-#   else /* no EXEC_PAGESIZE */
-#    ifdef NBPG
-#     define getpagesize() NBPG * CLSIZE
-#     ifndef CLSIZE
-#      define CLSIZE 1
-#     endif /* no CLSIZE */
-#    else /* no NBPG */
-#     ifdef NBPC
-#      define getpagesize() NBPC
-#     else /* no NBPC */
-#      ifdef PAGESIZE
-#       define getpagesize() PAGESIZE
-#      endif /* PAGESIZE */
-#     endif /* no NBPC */
-#    endif /* no NBPG */
-#   endif /* no EXEC_PAGESIZE */
-#  else /* no HAVE_SYS_PARAM_H */
-#   define getpagesize() 8192	/* punt totally */
-#  endif /* no HAVE_SYS_PARAM_H */
-# endif /* no _SC_PAGESIZE */
-
-#endif /* no HAVE_GETPAGESIZE */
-
-#ifdef __cplusplus
-extern "C" { void *malloc(unsigned); }
-#else
-char *malloc();
-#endif
-
-int
-main()
-{
-	char *data, *data2, *data3;
-	int i, pagesize;
-	int fd;
-
-	pagesize = getpagesize();
-
-	/*
-	 * First, make a file with some known garbage in it.
-	 */
-	data = malloc(pagesize);
-	if (!data)
-		exit(1);
-	for (i = 0; i < pagesize; ++i)
-		*(data + i) = rand();
-	umask(0);
-	fd = creat("conftestmmap", 0600);
-	if (fd < 0)
-		exit(1);
-	if (write(fd, data, pagesize) != pagesize)
-		exit(1);
-	close(fd);
-
-	/*
-	 * Next, try to mmap the file at a fixed address which
-	 * already has something else allocated at it.  If we can,
-	 * also make sure that we see the same garbage.
-	 */
-	fd = open("conftestmmap", O_RDWR);
-	if (fd < 0)
-		exit(1);
-	data2 = malloc(2 * pagesize);
-	if (!data2)
-		exit(1);
-	data2 += (pagesize - ((int) data2 & (pagesize - 1))) & (pagesize - 1);
-	if (data2 != mmap(data2, pagesize, PROT_READ | PROT_WRITE,
-	    MAP_PRIVATE | MAP_FIXED, fd, 0L))
-		exit(1);
-	for (i = 0; i < pagesize; ++i)
-		if (*(data + i) != *(data2 + i))
-			exit(1);
-
-	/*
-	 * Finally, make sure that changes to the mapped area
-	 * do not percolate back to the file as seen by read().
-	 * (This is a bug on some variants of i386 svr4.0.)
-	 */
-	for (i = 0; i < pagesize; ++i)
-		*(data2 + i) = *(data2 + i) + 1;
-	data3 = malloc(pagesize);
-	if (!data3)
-		exit(1);
-	if (read(fd, data3, pagesize) != pagesize)
-		exit(1);
-	for (i = 0; i < pagesize; ++i)
-		if (*(data + i) != *(data3 + i))
-			exit(1);
-	close(fd);
-	unlink("conftestmmap");
-	exit(0);
-}
-
-EOF
-if { (eval echo configure:1583: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
-then
-  ac_cv_func_mmap_fixed_mapped=yes
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -fr conftest*
-  ac_cv_func_mmap_fixed_mapped=no
-fi
-rm -fr conftest*
-fi
-
-fi
-
-echo "$ac_t""$ac_cv_func_mmap_fixed_mapped" 1>&6
-if test $ac_cv_func_mmap_fixed_mapped = yes; then
-  cat >> confdefs.h <<\EOF
-#define HAVE_MMAP 1
-EOF
-
-fi
-
-
-# autoconf.info says this should be called right after AC_INIT.
-
-
-ac_aux_dir=
-for ac_dir in `cd $srcdir;pwd`/../.. $srcdir/`cd $srcdir;pwd`/../..; do
-  if test -f $ac_dir/install-sh; then
-    ac_aux_dir=$ac_dir
-    ac_install_sh="$ac_aux_dir/install-sh -c"
-    break
-  elif test -f $ac_dir/install.sh; then
-    ac_aux_dir=$ac_dir
-    ac_install_sh="$ac_aux_dir/install.sh -c"
-    break
-  fi
-done
-if test -z "$ac_aux_dir"; then
-  { echo "configure: error: can not find install-sh or install.sh in `cd $srcdir;pwd`/../.. $srcdir/`cd $srcdir;pwd`/../.." 1>&2; exit 1; }
-fi
-ac_config_guess=$ac_aux_dir/config.guess
-ac_config_sub=$ac_aux_dir/config.sub
-ac_configure=$ac_aux_dir/configure # This should be Cygnus configure.
-
-
-# Do some error checking and defaulting for the host and target type.
-# The inputs are:
-#    configure --host=HOST --target=TARGET --build=BUILD NONOPT
-#
-# The rules are:
-# 1. You are not allowed to specify --host, --target, and nonopt at the
-#    same time.
-# 2. Host defaults to nonopt.
-# 3. If nonopt is not specified, then host defaults to the current host,
-#    as determined by config.guess.
-# 4. Target and build default to nonopt.
-# 5. If nonopt is not specified, then target and build default to host.
-
-# The aliases save the names the user supplied, while $host etc.
-# will get canonicalized.
-case $host---$target---$nonopt in
-NONE---*---* | *---NONE---* | *---*---NONE) ;;
-*) { echo "configure: error: can only configure for one host and one target at a time" 1>&2; exit 1; } ;;
-esac
-
-
-# Make sure we can run config.sub.
-if ${CONFIG_SHELL-/bin/sh} $ac_config_sub sun4 >/dev/null 2>&1; then :
-else { echo "configure: error: can not run $ac_config_sub" 1>&2; exit 1; }
-fi
-
-echo $ac_n "checking host system type""... $ac_c" 1>&6
-echo "configure:1656: checking host system type" >&5
-
-host_alias=$host
-case "$host_alias" in
-NONE)
-  case $nonopt in
-  NONE)
-    if host_alias=`${CONFIG_SHELL-/bin/sh} $ac_config_guess`; then :
-    else { echo "configure: error: can not guess host type; you must specify one" 1>&2; exit 1; }
-    fi ;;
-  *) host_alias=$nonopt ;;
-  esac ;;
-esac
-
-host=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $host_alias`
-host_cpu=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
-host_vendor=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
-host_os=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
-echo "$ac_t""$host" 1>&6
-
-echo $ac_n "checking target system type""... $ac_c" 1>&6
-echo "configure:1677: checking target system type" >&5
-
-target_alias=$target
-case "$target_alias" in
-NONE)
-  case $nonopt in
-  NONE) target_alias=$host_alias ;;
-  *) target_alias=$nonopt ;;
-  esac ;;
-esac
-
-target=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $target_alias`
-target_cpu=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
-target_vendor=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
-target_os=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
-echo "$ac_t""$target" 1>&6
-
-echo $ac_n "checking build system type""... $ac_c" 1>&6
-echo "configure:1695: checking build system type" >&5
-
-build_alias=$build
-case "$build_alias" in
-NONE)
-  case $nonopt in
-  NONE) build_alias=$host_alias ;;
-  *) build_alias=$nonopt ;;
-  esac ;;
-esac
-
-build=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $build_alias`
-build_cpu=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
-build_vendor=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
-build_os=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
-echo "$ac_t""$build" 1>&6
-
-test "$host_alias" != "$target_alias" &&
-  test "$program_prefix$program_suffix$program_transform_name" = \
-    NONENONEs,x,x, &&
-  program_prefix=${target_alias}-
-
-if test "$program_transform_name" = s,x,x,; then
-  program_transform_name=
-else
-  # Double any \ or $.  echo might interpret backslashes.
-  cat <<\EOF_SED > conftestsed
-s,\\,\\\\,g; s,\$,$$,g
-EOF_SED
-  program_transform_name="`echo $program_transform_name|sed -f conftestsed`"
-  rm -f conftestsed
-fi
-test "$program_prefix" != NONE &&
-  program_transform_name="s,^,${program_prefix},; $program_transform_name"
-# Use a double $ so make ignores it.
-test "$program_suffix" != NONE &&
-  program_transform_name="s,\$\$,${program_suffix},; $program_transform_name"
-
-# sed with no file args requires a program.
-test "$program_transform_name" = "" && program_transform_name="s,x,x,"
-
-# Extract the first word of "gcc", so it can be a program name with args.
-set dummy gcc; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1739: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  if test -n "$CC"; then
-  ac_cv_prog_CC="$CC" # Let the user override the test.
-else
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  for ac_dir in $PATH; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_prog_CC="gcc"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-fi
-fi
-CC="$ac_cv_prog_CC"
-if test -n "$CC"; then
-  echo "$ac_t""$CC" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-if test -z "$CC"; then
-  # Extract the first word of "cc", so it can be a program name with args.
-set dummy cc; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1768: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  if test -n "$CC"; then
-  ac_cv_prog_CC="$CC" # Let the user override the test.
-else
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  ac_prog_rejected=no
-  for ac_dir in $PATH; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      if test "$ac_dir/$ac_word" = "/usr/ucb/cc"; then
-        ac_prog_rejected=yes
-	continue
-      fi
-      ac_cv_prog_CC="cc"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-if test $ac_prog_rejected = yes; then
-  # We found a bogon in the path, so make sure we never use it.
-  set dummy $ac_cv_prog_CC
-  shift
-  if test $# -gt 0; then
-    # We chose a different compiler from the bogus one.
-    # However, it has the same basename, so the bogon will be chosen
-    # first if we set CC to just the basename; use the full file name.
-    shift
-    set dummy "$ac_dir/$ac_word" "$@"
-    shift
-    ac_cv_prog_CC="$@"
-  fi
-fi
-fi
-fi
-CC="$ac_cv_prog_CC"
-if test -n "$CC"; then
-  echo "$ac_t""$CC" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-  if test -z "$CC"; then
-    case "`uname -s`" in
-    *win32* | *WIN32*)
-      # Extract the first word of "cl", so it can be a program name with args.
-set dummy cl; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:1818: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  if test -n "$CC"; then
-  ac_cv_prog_CC="$CC" # Let the user override the test.
-else
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  for ac_dir in $PATH; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_prog_CC="cl"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-fi
-fi
-CC="$ac_cv_prog_CC"
-if test -n "$CC"; then
-  echo "$ac_t""$CC" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
- ;;
-    esac
-  fi
-  test -z "$CC" && { echo "configure: error: no acceptable cc found in \$PATH" 1>&2; exit 1; }
-fi
-
-echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6
-echo "configure:1849: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5
-
-ac_ext=c
-# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options.
-ac_cpp='$CPP $CPPFLAGS'
-ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5'
-ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5'
-cross_compiling=$ac_cv_prog_cc_cross
-
-cat > conftest.$ac_ext <<EOF
-#line 1859 "configure"
-#include "confdefs.h"
-main(){return(0);}
-EOF
-if { (eval echo configure:1863: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  ac_cv_prog_cc_works=yes
-  # If we can't run a trivial program, we are probably using a cross compiler.
-  if (./conftest; exit) 2>/dev/null; then
-    ac_cv_prog_cc_cross=no
-  else
-    ac_cv_prog_cc_cross=yes
-  fi
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  ac_cv_prog_cc_works=no
-fi
-rm -fr conftest*
-
-echo "$ac_t""$ac_cv_prog_cc_works" 1>&6
-if test $ac_cv_prog_cc_works = no; then
-  { echo "configure: error: installation or configuration problem: C compiler cannot create executables." 1>&2; exit 1; }
-fi
-echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6
-echo "configure:1883: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5
-echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6
-cross_compiling=$ac_cv_prog_cc_cross
-
-echo $ac_n "checking whether we are using GNU C""... $ac_c" 1>&6
-echo "configure:1888: checking whether we are using GNU C" >&5
-if eval "test \"`echo '$''{'ac_cv_prog_gcc'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.c <<EOF
-#ifdef __GNUC__
-  yes;
-#endif
-EOF
-if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:1897: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then
-  ac_cv_prog_gcc=yes
-else
-  ac_cv_prog_gcc=no
-fi
-fi
-
-echo "$ac_t""$ac_cv_prog_gcc" 1>&6
-
-if test $ac_cv_prog_gcc = yes; then
-  GCC=yes
-else
-  GCC=
-fi
-
-ac_test_CFLAGS="${CFLAGS+set}"
-ac_save_CFLAGS="$CFLAGS"
-CFLAGS=
-echo $ac_n "checking whether ${CC-cc} accepts -g""... $ac_c" 1>&6
-echo "configure:1916: checking whether ${CC-cc} accepts -g" >&5
-if eval "test \"`echo '$''{'ac_cv_prog_cc_g'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  echo 'void f(){}' > conftest.c
-if test -z "`${CC-cc} -g -c conftest.c 2>&1`"; then
-  ac_cv_prog_cc_g=yes
-else
-  ac_cv_prog_cc_g=no
-fi
-rm -f conftest*
-
-fi
-
-echo "$ac_t""$ac_cv_prog_cc_g" 1>&6
-if test "$ac_test_CFLAGS" = set; then
-  CFLAGS="$ac_save_CFLAGS"
-elif test $ac_cv_prog_cc_g = yes; then
-  if test "$GCC" = yes; then
-    CFLAGS="-g -O2"
-  else
-    CFLAGS="-g"
-  fi
-else
-  if test "$GCC" = yes; then
-    CFLAGS="-O2"
-  else
-    CFLAGS=
-  fi
-fi
-
-# Find a good install program.  We prefer a C program (faster),
-# so one script is as good as another.  But avoid the broken or
-# incompatible versions:
-# SysV /etc/install, /usr/sbin/install
-# SunOS /usr/etc/install
-# IRIX /sbin/install
-# AIX /bin/install
-# AIX 4 /usr/bin/installbsd, which doesn't work without a -g flag
-# AFS /usr/afsws/bin/install, which mishandles nonexistent args
-# SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff"
-# ./install, which can be erroneously created by make from ./install.sh.
-echo $ac_n "checking for a BSD compatible install""... $ac_c" 1>&6
-echo "configure:1959: checking for a BSD compatible install" >&5
-if test -z "$INSTALL"; then
-if eval "test \"`echo '$''{'ac_cv_path_install'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-    IFS="${IFS= 	}"; ac_save_IFS="$IFS"; IFS=":"
-  for ac_dir in $PATH; do
-    # Account for people who put trailing slashes in PATH elements.
-    case "$ac_dir/" in
-    /|./|.//|/etc/*|/usr/sbin/*|/usr/etc/*|/sbin/*|/usr/afsws/bin/*|/usr/ucb/*) ;;
-    *)
-      # OSF1 and SCO ODT 3.0 have their own names for install.
-      # Don't use installbsd from OSF since it installs stuff as root
-      # by default.
-      for ac_prog in ginstall scoinst install; do
-        if test -f $ac_dir/$ac_prog; then
-	  if test $ac_prog = install &&
-            grep dspmsg $ac_dir/$ac_prog >/dev/null 2>&1; then
-	    # AIX install.  It has an incompatible calling convention.
-	    :
-	  else
-	    ac_cv_path_install="$ac_dir/$ac_prog -c"
-	    break 2
-	  fi
-	fi
-      done
-      ;;
-    esac
-  done
-  IFS="$ac_save_IFS"
-
-fi
-  if test "${ac_cv_path_install+set}" = set; then
-    INSTALL="$ac_cv_path_install"
-  else
-    # As a last resort, use the slow shell script.  We don't cache a
-    # path for INSTALL within a source directory, because that will
-    # break other packages using the cache if that directory is
-    # removed, or if the path is relative.
-    INSTALL="$ac_install_sh"
-  fi
-fi
-echo "$ac_t""$INSTALL" 1>&6
-
-# Use test -z because SunOS4 sh mishandles braces in ${var-val}.
-# It thinks the first close brace ends the variable substitution.
-test -z "$INSTALL_PROGRAM" && INSTALL_PROGRAM='${INSTALL}'
-
-test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644'
-
-
-# Put a plausible default for CC_FOR_BUILD in Makefile.
-if test "x$cross_compiling" = "xno"; then
-  CC_FOR_BUILD='$(CC)'
-else
-  CC_FOR_BUILD=gcc
-fi
-
-
-
-
-AR=${AR-ar}
-
-# Extract the first word of "ranlib", so it can be a program name with args.
-set dummy ranlib; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:2025: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  if test -n "$RANLIB"; then
-  ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test.
-else
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  for ac_dir in $PATH; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_prog_RANLIB="ranlib"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  test -z "$ac_cv_prog_RANLIB" && ac_cv_prog_RANLIB=":"
-fi
-fi
-RANLIB="$ac_cv_prog_RANLIB"
-if test -n "$RANLIB"; then
-  echo "$ac_t""$RANLIB" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-
-ALL_LINGUAS=
-                              
-   for ac_hdr in argz.h limits.h locale.h nl_types.h malloc.h string.h \
-unistd.h values.h sys/param.h
-do
-ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
-echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
-echo "configure:2059: checking for $ac_hdr" >&5
-if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 2064 "configure"
-#include "confdefs.h"
-#include <$ac_hdr>
-EOF
-ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:2069: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
-ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
-if test -z "$ac_err"; then
-  rm -rf conftest*
-  eval "ac_cv_header_$ac_safe=yes"
-else
-  echo "$ac_err" >&5
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_header_$ac_safe=no"
-fi
-rm -f conftest*
-fi
-if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-    ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'`
-  cat >> confdefs.h <<EOF
-#define $ac_tr_hdr 1
-EOF
- 
-else
-  echo "$ac_t""no" 1>&6
-fi
-done
-
-   for ac_func in getcwd munmap putenv setenv setlocale strchr strcasecmp \
-__argz_count __argz_stringify __argz_next
-do
-echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:2099: checking for $ac_func" >&5
-if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 2104 "configure"
-#include "confdefs.h"
-/* System header to define __stub macros and hopefully few prototypes,
-    which can conflict with char $ac_func(); below.  */
-#include <assert.h>
-/* Override any gcc2 internal prototype to avoid an error.  */
-/* We use char because int might match the return type of a gcc2
-    builtin and then its argument prototype would still apply.  */
-char $ac_func();
-
-int main() {
-
-/* The GNU C library defines this for functions which it implements
-    to always fail with ENOSYS.  Some functions are actually named
-    something starting with __ and the normal name is an alias.  */
-#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
-choke me
-#else
-$ac_func();
-#endif
-
-; return 0; }
-EOF
-if { (eval echo configure:2127: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  rm -rf conftest*
-  eval "ac_cv_func_$ac_func=yes"
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_func_$ac_func=no"
-fi
-rm -f conftest*
-fi
-
-if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-    ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
-  cat >> confdefs.h <<EOF
-#define $ac_tr_func 1
-EOF
- 
-else
-  echo "$ac_t""no" 1>&6
-fi
-done
-
-
-   if test "${ac_cv_func_stpcpy+set}" != "set"; then
-     for ac_func in stpcpy
-do
-echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:2156: checking for $ac_func" >&5
-if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 2161 "configure"
-#include "confdefs.h"
-/* System header to define __stub macros and hopefully few prototypes,
-    which can conflict with char $ac_func(); below.  */
-#include <assert.h>
-/* Override any gcc2 internal prototype to avoid an error.  */
-/* We use char because int might match the return type of a gcc2
-    builtin and then its argument prototype would still apply.  */
-char $ac_func();
-
-int main() {
-
-/* The GNU C library defines this for functions which it implements
-    to always fail with ENOSYS.  Some functions are actually named
-    something starting with __ and the normal name is an alias.  */
-#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
-choke me
-#else
-$ac_func();
-#endif
-
-; return 0; }
-EOF
-if { (eval echo configure:2184: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  rm -rf conftest*
-  eval "ac_cv_func_$ac_func=yes"
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_func_$ac_func=no"
-fi
-rm -f conftest*
-fi
-
-if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-    ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
-  cat >> confdefs.h <<EOF
-#define $ac_tr_func 1
-EOF
- 
-else
-  echo "$ac_t""no" 1>&6
-fi
-done
-
-   fi
-   if test "${ac_cv_func_stpcpy}" = "yes"; then
-     cat >> confdefs.h <<\EOF
-#define HAVE_STPCPY 1
-EOF
-
-   fi
-
-   if test $ac_cv_header_locale_h = yes; then
-    echo $ac_n "checking for LC_MESSAGES""... $ac_c" 1>&6
-echo "configure:2218: checking for LC_MESSAGES" >&5
-if eval "test \"`echo '$''{'am_cv_val_LC_MESSAGES'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 2223 "configure"
-#include "confdefs.h"
-#include <locale.h>
-int main() {
-return LC_MESSAGES
-; return 0; }
-EOF
-if { (eval echo configure:2230: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  rm -rf conftest*
-  am_cv_val_LC_MESSAGES=yes
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  am_cv_val_LC_MESSAGES=no
-fi
-rm -f conftest*
-fi
-
-echo "$ac_t""$am_cv_val_LC_MESSAGES" 1>&6
-    if test $am_cv_val_LC_MESSAGES = yes; then
-      cat >> confdefs.h <<\EOF
-#define HAVE_LC_MESSAGES 1
-EOF
-
-    fi
-  fi
-   echo $ac_n "checking whether NLS is requested""... $ac_c" 1>&6
-echo "configure:2251: checking whether NLS is requested" >&5
-        # Check whether --enable-nls or --disable-nls was given.
-if test "${enable_nls+set}" = set; then
-  enableval="$enable_nls"
-  USE_NLS=$enableval
-else
-  USE_NLS=yes
-fi
-
-    echo "$ac_t""$USE_NLS" 1>&6
-    
-
-    USE_INCLUDED_LIBINTL=no
-
-        if test "$USE_NLS" = "yes"; then
-      cat >> confdefs.h <<\EOF
-#define ENABLE_NLS 1
-EOF
-
-      echo $ac_n "checking whether included gettext is requested""... $ac_c" 1>&6
-echo "configure:2271: checking whether included gettext is requested" >&5
-      # Check whether --with-included-gettext or --without-included-gettext was given.
-if test "${with_included_gettext+set}" = set; then
-  withval="$with_included_gettext"
-  nls_cv_force_use_gnu_gettext=$withval
-else
-  nls_cv_force_use_gnu_gettext=no
-fi
-
-      echo "$ac_t""$nls_cv_force_use_gnu_gettext" 1>&6
-
-      nls_cv_use_gnu_gettext="$nls_cv_force_use_gnu_gettext"
-      if test "$nls_cv_force_use_gnu_gettext" != "yes"; then
-                        		nls_cv_header_intl=
-	nls_cv_header_libgt=
-	CATOBJEXT=NONE
-
-	ac_safe=`echo "libintl.h" | sed 'y%./+-%__p_%'`
-echo $ac_n "checking for libintl.h""... $ac_c" 1>&6
-echo "configure:2290: checking for libintl.h" >&5
-if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 2295 "configure"
-#include "confdefs.h"
-#include <libintl.h>
-EOF
-ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:2300: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
-ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
-if test -z "$ac_err"; then
-  rm -rf conftest*
-  eval "ac_cv_header_$ac_safe=yes"
-else
-  echo "$ac_err" >&5
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_header_$ac_safe=no"
-fi
-rm -f conftest*
-fi
-if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-  echo $ac_n "checking for gettext in libc""... $ac_c" 1>&6
-echo "configure:2317: checking for gettext in libc" >&5
-if eval "test \"`echo '$''{'gt_cv_func_gettext_libc'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 2322 "configure"
-#include "confdefs.h"
-#include <libintl.h>
-int main() {
-return (int) gettext ("")
-; return 0; }
-EOF
-if { (eval echo configure:2329: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  rm -rf conftest*
-  gt_cv_func_gettext_libc=yes
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  gt_cv_func_gettext_libc=no
-fi
-rm -f conftest*
-fi
-
-echo "$ac_t""$gt_cv_func_gettext_libc" 1>&6
-
-	   if test "$gt_cv_func_gettext_libc" != "yes"; then
-	     echo $ac_n "checking for bindtextdomain in -lintl""... $ac_c" 1>&6
-echo "configure:2345: checking for bindtextdomain in -lintl" >&5
-ac_lib_var=`echo intl'_'bindtextdomain | sed 'y%./+-%__p_%'`
-if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  ac_save_LIBS="$LIBS"
-LIBS="-lintl  $LIBS"
-cat > conftest.$ac_ext <<EOF
-#line 2353 "configure"
-#include "confdefs.h"
-/* Override any gcc2 internal prototype to avoid an error.  */
-/* We use char because int might match the return type of a gcc2
-    builtin and then its argument prototype would still apply.  */
-char bindtextdomain();
-
-int main() {
-bindtextdomain()
-; return 0; }
-EOF
-if { (eval echo configure:2364: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  rm -rf conftest*
-  eval "ac_cv_lib_$ac_lib_var=yes"
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_lib_$ac_lib_var=no"
-fi
-rm -f conftest*
-LIBS="$ac_save_LIBS"
-
-fi
-if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-  echo $ac_n "checking for gettext in libintl""... $ac_c" 1>&6
-echo "configure:2380: checking for gettext in libintl" >&5
-if eval "test \"`echo '$''{'gt_cv_func_gettext_libintl'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 2385 "configure"
-#include "confdefs.h"
-
-int main() {
-return (int) gettext ("")
-; return 0; }
-EOF
-if { (eval echo configure:2392: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  rm -rf conftest*
-  gt_cv_func_gettext_libintl=yes
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  gt_cv_func_gettext_libintl=no
-fi
-rm -f conftest*
-fi
-
-echo "$ac_t""$gt_cv_func_gettext_libintl" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-	   fi
-
-	   if test "$gt_cv_func_gettext_libc" = "yes" \
-	      || test "$gt_cv_func_gettext_libintl" = "yes"; then
-	      cat >> confdefs.h <<\EOF
-#define HAVE_GETTEXT 1
-EOF
-
-	      # Extract the first word of "msgfmt", so it can be a program name with args.
-set dummy msgfmt; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:2420: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$MSGFMT" in
-  /*)
-  ac_cv_path_MSGFMT="$MSGFMT" # Let the user override the test with a path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:"
-  for ac_dir in $PATH; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      if test -z "`$ac_dir/$ac_word -h 2>&1 | grep 'dv '`"; then
-	ac_cv_path_MSGFMT="$ac_dir/$ac_word"
-	break
-      fi
-    fi
-  done
-  IFS="$ac_save_ifs"
-  test -z "$ac_cv_path_MSGFMT" && ac_cv_path_MSGFMT="no"
-  ;;
-esac
-fi
-MSGFMT="$ac_cv_path_MSGFMT"
-if test -n "$MSGFMT"; then
-  echo "$ac_t""$MSGFMT" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-	      if test "$MSGFMT" != "no"; then
-		for ac_func in dcgettext
-do
-echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:2454: checking for $ac_func" >&5
-if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 2459 "configure"
-#include "confdefs.h"
-/* System header to define __stub macros and hopefully few prototypes,
-    which can conflict with char $ac_func(); below.  */
-#include <assert.h>
-/* Override any gcc2 internal prototype to avoid an error.  */
-/* We use char because int might match the return type of a gcc2
-    builtin and then its argument prototype would still apply.  */
-char $ac_func();
-
-int main() {
-
-/* The GNU C library defines this for functions which it implements
-    to always fail with ENOSYS.  Some functions are actually named
-    something starting with __ and the normal name is an alias.  */
-#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
-choke me
-#else
-$ac_func();
-#endif
-
-; return 0; }
-EOF
-if { (eval echo configure:2482: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  rm -rf conftest*
-  eval "ac_cv_func_$ac_func=yes"
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_func_$ac_func=no"
-fi
-rm -f conftest*
-fi
-
-if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-    ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
-  cat >> confdefs.h <<EOF
-#define $ac_tr_func 1
-EOF
- 
-else
-  echo "$ac_t""no" 1>&6
-fi
-done
-
-		# Extract the first word of "gmsgfmt", so it can be a program name with args.
-set dummy gmsgfmt; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:2509: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$GMSGFMT" in
-  /*)
-  ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  for ac_dir in $PATH; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_GMSGFMT="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  test -z "$ac_cv_path_GMSGFMT" && ac_cv_path_GMSGFMT="$MSGFMT"
-  ;;
-esac
-fi
-GMSGFMT="$ac_cv_path_GMSGFMT"
-if test -n "$GMSGFMT"; then
-  echo "$ac_t""$GMSGFMT" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-		# Extract the first word of "xgettext", so it can be a program name with args.
-set dummy xgettext; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:2544: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$XGETTEXT" in
-  /*)
-  ac_cv_path_XGETTEXT="$XGETTEXT" # Let the user override the test with a path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:"
-  for ac_dir in $PATH; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      if test -z "`$ac_dir/$ac_word -h 2>&1 | grep '(HELP)'`"; then
-	ac_cv_path_XGETTEXT="$ac_dir/$ac_word"
-	break
-      fi
-    fi
-  done
-  IFS="$ac_save_ifs"
-  test -z "$ac_cv_path_XGETTEXT" && ac_cv_path_XGETTEXT=":"
-  ;;
-esac
-fi
-XGETTEXT="$ac_cv_path_XGETTEXT"
-if test -n "$XGETTEXT"; then
-  echo "$ac_t""$XGETTEXT" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-		cat > conftest.$ac_ext <<EOF
-#line 2576 "configure"
-#include "confdefs.h"
-
-int main() {
-extern int _nl_msg_cat_cntr;
-			       return _nl_msg_cat_cntr
-; return 0; }
-EOF
-if { (eval echo configure:2584: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  rm -rf conftest*
-  CATOBJEXT=.gmo
-		   DATADIRNAME=share
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  CATOBJEXT=.mo
-		   DATADIRNAME=lib
-fi
-rm -f conftest*
-		INSTOBJEXT=.mo
-	      fi
-	    fi
-	
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-
-	        
-        if test "$CATOBJEXT" = "NONE"; then
-	  	  	  nls_cv_use_gnu_gettext=yes
-        fi
-      fi
-
-      if test "$nls_cv_use_gnu_gettext" = "yes"; then
-                INTLOBJS="\$(GETTOBJS)"
-        # Extract the first word of "msgfmt", so it can be a program name with args.
-set dummy msgfmt; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:2616: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$MSGFMT" in
-  /*)
-  ac_cv_path_MSGFMT="$MSGFMT" # Let the user override the test with a path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:"
-  for ac_dir in $PATH; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      if test -z "`$ac_dir/$ac_word -h 2>&1 | grep 'dv '`"; then
-	ac_cv_path_MSGFMT="$ac_dir/$ac_word"
-	break
-      fi
-    fi
-  done
-  IFS="$ac_save_ifs"
-  test -z "$ac_cv_path_MSGFMT" && ac_cv_path_MSGFMT="msgfmt"
-  ;;
-esac
-fi
-MSGFMT="$ac_cv_path_MSGFMT"
-if test -n "$MSGFMT"; then
-  echo "$ac_t""$MSGFMT" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-        # Extract the first word of "gmsgfmt", so it can be a program name with args.
-set dummy gmsgfmt; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:2650: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$GMSGFMT" in
-  /*)
-  ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a path.
-  ;;
-  ?:/*)			 
-  ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a dos path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS=":"
-  for ac_dir in $PATH; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      ac_cv_path_GMSGFMT="$ac_dir/$ac_word"
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  test -z "$ac_cv_path_GMSGFMT" && ac_cv_path_GMSGFMT="$MSGFMT"
-  ;;
-esac
-fi
-GMSGFMT="$ac_cv_path_GMSGFMT"
-if test -n "$GMSGFMT"; then
-  echo "$ac_t""$GMSGFMT" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-        # Extract the first word of "xgettext", so it can be a program name with args.
-set dummy xgettext; ac_word=$2
-echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
-echo "configure:2685: checking for $ac_word" >&5
-if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  case "$XGETTEXT" in
-  /*)
-  ac_cv_path_XGETTEXT="$XGETTEXT" # Let the user override the test with a path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:"
-  for ac_dir in $PATH; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      if test -z "`$ac_dir/$ac_word -h 2>&1 | grep '(HELP)'`"; then
-	ac_cv_path_XGETTEXT="$ac_dir/$ac_word"
-	break
-      fi
-    fi
-  done
-  IFS="$ac_save_ifs"
-  test -z "$ac_cv_path_XGETTEXT" && ac_cv_path_XGETTEXT=":"
-  ;;
-esac
-fi
-XGETTEXT="$ac_cv_path_XGETTEXT"
-if test -n "$XGETTEXT"; then
-  echo "$ac_t""$XGETTEXT" 1>&6
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-        
-	USE_INCLUDED_LIBINTL=yes
-        CATOBJEXT=.gmo
-        INSTOBJEXT=.mo
-        DATADIRNAME=share
-	INTLDEPS='$(top_builddir)/../intl/libintl.a'
-	INTLLIBS=$INTLDEPS
-	LIBS=`echo $LIBS | sed -e 's/-lintl//'`
-        nls_cv_header_intl=libintl.h
-        nls_cv_header_libgt=libgettext.h
-      fi
-
-            if test "$XGETTEXT" != ":"; then
-			if $XGETTEXT --omit-header /dev/null 2> /dev/null; then
-	  : ;
-	else
-	  echo "$ac_t""found xgettext programs is not GNU xgettext; ignore it" 1>&6
-	  XGETTEXT=":"
-	fi
-      fi
-
-      # We need to process the po/ directory.
-      POSUB=po
-    else
-      DATADIRNAME=share
-      nls_cv_header_intl=libintl.h
-      nls_cv_header_libgt=libgettext.h
-    fi
-
-    # If this is used in GNU gettext we have to set USE_NLS to `yes'
-    # because some of the sources are only built for this goal.
-    if test "$PACKAGE" = gettext; then
-      USE_NLS=yes
-      USE_INCLUDED_LIBINTL=yes
-    fi
-
-                for lang in $ALL_LINGUAS; do
-      GMOFILES="$GMOFILES $lang.gmo"
-      POFILES="$POFILES $lang.po"
-    done
-
-        
-    
-    
-    
-    
-    
-    
-    
-    
-    
-    
-  
-
-   if test "x$CATOBJEXT" != "x"; then
-     if test "x$ALL_LINGUAS" = "x"; then
-       LINGUAS=
-     else
-       echo $ac_n "checking for catalogs to be installed""... $ac_c" 1>&6
-echo "configure:2775: checking for catalogs to be installed" >&5
-       NEW_LINGUAS=
-       for lang in ${LINGUAS=$ALL_LINGUAS}; do
-         case "$ALL_LINGUAS" in
-          *$lang*) NEW_LINGUAS="$NEW_LINGUAS $lang" ;;
-         esac
-       done
-       LINGUAS=$NEW_LINGUAS
-       echo "$ac_t""$LINGUAS" 1>&6
-     fi
-
-          if test -n "$LINGUAS"; then
-       for lang in $LINGUAS; do CATALOGS="$CATALOGS $lang$CATOBJEXT"; done
-     fi
-   fi
-
-            if test $ac_cv_header_locale_h = yes; then
-     INCLUDE_LOCALE_H="#include <locale.h>"
-   else
-     INCLUDE_LOCALE_H="\
-/* The system does not provide the header <locale.h>.  Take care yourself.  */"
-   fi
-   
-
-            if test -f $srcdir/po2tbl.sed.in; then
-      if test "$CATOBJEXT" = ".cat"; then
-	 ac_safe=`echo "linux/version.h" | sed 'y%./+-%__p_%'`
-echo $ac_n "checking for linux/version.h""... $ac_c" 1>&6
-echo "configure:2803: checking for linux/version.h" >&5
-if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 2808 "configure"
-#include "confdefs.h"
-#include <linux/version.h>
-EOF
-ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:2813: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
-ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
-if test -z "$ac_err"; then
-  rm -rf conftest*
-  eval "ac_cv_header_$ac_safe=yes"
-else
-  echo "$ac_err" >&5
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_header_$ac_safe=no"
-fi
-rm -f conftest*
-fi
-if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-  msgformat=linux
-else
-  echo "$ac_t""no" 1>&6
-msgformat=xopen
-fi
-
-
-	          	 sed -e '/^#/d' $srcdir/$msgformat-msg.sed > po2msg.sed
-      fi
-            sed -e '/^#.*[^\\]$/d' -e '/^#$/d' \
-	 $srcdir/po2tbl.sed.in > po2tbl.sed
-   fi
-
-            if test "$PACKAGE" = "gettext"; then
-     GT_NO="#NO#"
-     GT_YES=
-   else
-     GT_NO=
-     GT_YES="#YES#"
-   fi
-   
-   
-
-   MKINSTALLDIRS="\$(srcdir)/../../mkinstalldirs"
-   
-
-      l=
-   
-
-            if test -d $srcdir/po; then
-      test -d po || mkdir po
-      if test "x$srcdir" != "x."; then
-	 if test "x`echo $srcdir | sed 's@/.*@@'`" = "x"; then
-	    posrcprefix="$srcdir/"
-	 else
-	    posrcprefix="../$srcdir/"
-	 fi
-      else
-	 posrcprefix="../"
-      fi
-      rm -f po/POTFILES
-      sed -e "/^#/d" -e "/^\$/d" -e "s,.*,	$posrcprefix& \\\\," -e "\$s/\(.*\) \\\\/\1/" \
-	 < $srcdir/po/POTFILES.in > po/POTFILES
-   fi
-  
-
-# Check for common headers.
-# FIXME: Seems to me this can cause problems for i386-windows hosts.
-# At one point there were hardcoded AC_DEFINE's if ${host} = i386-*-windows*.
-for ac_hdr in stdlib.h string.h strings.h unistd.h time.h
-do
-ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
-echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
-echo "configure:2882: checking for $ac_hdr" >&5
-if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 2887 "configure"
-#include "confdefs.h"
-#include <$ac_hdr>
-EOF
-ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:2892: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
-ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
-if test -z "$ac_err"; then
-  rm -rf conftest*
-  eval "ac_cv_header_$ac_safe=yes"
-else
-  echo "$ac_err" >&5
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_header_$ac_safe=no"
-fi
-rm -f conftest*
-fi
-if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-    ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'`
-  cat >> confdefs.h <<EOF
-#define $ac_tr_hdr 1
-EOF
- 
-else
-  echo "$ac_t""no" 1>&6
-fi
-done
-
-for ac_hdr in sys/time.h sys/resource.h
-do
-ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
-echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
-echo "configure:2922: checking for $ac_hdr" >&5
-if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 2927 "configure"
-#include "confdefs.h"
-#include <$ac_hdr>
-EOF
-ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:2932: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
-ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
-if test -z "$ac_err"; then
-  rm -rf conftest*
-  eval "ac_cv_header_$ac_safe=yes"
-else
-  echo "$ac_err" >&5
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_header_$ac_safe=no"
-fi
-rm -f conftest*
-fi
-if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-    ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'`
-  cat >> confdefs.h <<EOF
-#define $ac_tr_hdr 1
-EOF
- 
-else
-  echo "$ac_t""no" 1>&6
-fi
-done
-
-for ac_hdr in fcntl.h fpu_control.h
-do
-ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
-echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
-echo "configure:2962: checking for $ac_hdr" >&5
-if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 2967 "configure"
-#include "confdefs.h"
-#include <$ac_hdr>
-EOF
-ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:2972: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
-ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
-if test -z "$ac_err"; then
-  rm -rf conftest*
-  eval "ac_cv_header_$ac_safe=yes"
-else
-  echo "$ac_err" >&5
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_header_$ac_safe=no"
-fi
-rm -f conftest*
-fi
-if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-    ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'`
-  cat >> confdefs.h <<EOF
-#define $ac_tr_hdr 1
-EOF
- 
-else
-  echo "$ac_t""no" 1>&6
-fi
-done
-
-for ac_hdr in dlfcn.h errno.h sys/stat.h
-do
-ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
-echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
-echo "configure:3002: checking for $ac_hdr" >&5
-if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 3007 "configure"
-#include "confdefs.h"
-#include <$ac_hdr>
-EOF
-ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:3012: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
-ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
-if test -z "$ac_err"; then
-  rm -rf conftest*
-  eval "ac_cv_header_$ac_safe=yes"
-else
-  echo "$ac_err" >&5
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_header_$ac_safe=no"
-fi
-rm -f conftest*
-fi
-if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-    ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'`
-  cat >> confdefs.h <<EOF
-#define $ac_tr_hdr 1
-EOF
- 
-else
-  echo "$ac_t""no" 1>&6
-fi
-done
-
-for ac_func in getrusage time sigaction __setfpucw
-do
-echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:3041: checking for $ac_func" >&5
-if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 3046 "configure"
-#include "confdefs.h"
-/* System header to define __stub macros and hopefully few prototypes,
-    which can conflict with char $ac_func(); below.  */
-#include <assert.h>
-/* Override any gcc2 internal prototype to avoid an error.  */
-/* We use char because int might match the return type of a gcc2
-    builtin and then its argument prototype would still apply.  */
-char $ac_func();
-
-int main() {
-
-/* The GNU C library defines this for functions which it implements
-    to always fail with ENOSYS.  Some functions are actually named
-    something starting with __ and the normal name is an alias.  */
-#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
-choke me
-#else
-$ac_func();
-#endif
-
-; return 0; }
-EOF
-if { (eval echo configure:3069: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  rm -rf conftest*
-  eval "ac_cv_func_$ac_func=yes"
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_func_$ac_func=no"
-fi
-rm -f conftest*
-fi
-
-if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-    ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
-  cat >> confdefs.h <<EOF
-#define $ac_tr_func 1
-EOF
- 
-else
-  echo "$ac_t""no" 1>&6
-fi
-done
-
-
-# Check for socket libraries
-echo $ac_n "checking for bind in -lsocket""... $ac_c" 1>&6
-echo "configure:3096: checking for bind in -lsocket" >&5
-ac_lib_var=`echo socket'_'bind | sed 'y%./+-%__p_%'`
-if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  ac_save_LIBS="$LIBS"
-LIBS="-lsocket  $LIBS"
-cat > conftest.$ac_ext <<EOF
-#line 3104 "configure"
-#include "confdefs.h"
-/* Override any gcc2 internal prototype to avoid an error.  */
-/* We use char because int might match the return type of a gcc2
-    builtin and then its argument prototype would still apply.  */
-char bind();
-
-int main() {
-bind()
-; return 0; }
-EOF
-if { (eval echo configure:3115: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  rm -rf conftest*
-  eval "ac_cv_lib_$ac_lib_var=yes"
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_lib_$ac_lib_var=no"
-fi
-rm -f conftest*
-LIBS="$ac_save_LIBS"
-
-fi
-if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-    ac_tr_lib=HAVE_LIB`echo socket | sed -e 's/[^a-zA-Z0-9_]/_/g' \
-    -e 'y/abcdefghijklmnopqrstuvwxyz/ABCDEFGHIJKLMNOPQRSTUVWXYZ/'`
-  cat >> confdefs.h <<EOF
-#define $ac_tr_lib 1
-EOF
-
-  LIBS="-lsocket $LIBS"
-
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-echo $ac_n "checking for gethostbyname in -lnsl""... $ac_c" 1>&6
-echo "configure:3143: checking for gethostbyname in -lnsl" >&5
-ac_lib_var=`echo nsl'_'gethostbyname | sed 'y%./+-%__p_%'`
-if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  ac_save_LIBS="$LIBS"
-LIBS="-lnsl  $LIBS"
-cat > conftest.$ac_ext <<EOF
-#line 3151 "configure"
-#include "confdefs.h"
-/* Override any gcc2 internal prototype to avoid an error.  */
-/* We use char because int might match the return type of a gcc2
-    builtin and then its argument prototype would still apply.  */
-char gethostbyname();
-
-int main() {
-gethostbyname()
-; return 0; }
-EOF
-if { (eval echo configure:3162: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
-  rm -rf conftest*
-  eval "ac_cv_lib_$ac_lib_var=yes"
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  eval "ac_cv_lib_$ac_lib_var=no"
-fi
-rm -f conftest*
-LIBS="$ac_save_LIBS"
-
-fi
-if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then
-  echo "$ac_t""yes" 1>&6
-    ac_tr_lib=HAVE_LIB`echo nsl | sed -e 's/[^a-zA-Z0-9_]/_/g' \
-    -e 'y/abcdefghijklmnopqrstuvwxyz/ABCDEFGHIJKLMNOPQRSTUVWXYZ/'`
-  cat >> confdefs.h <<EOF
-#define $ac_tr_lib 1
-EOF
-
-  LIBS="-lnsl $LIBS"
-
-else
-  echo "$ac_t""no" 1>&6
-fi
-
-
-. ${srcdir}/../../bfd/configure.host
-
-
-
-USE_MAINTAINER_MODE=no
-# Check whether --enable-maintainer-mode or --disable-maintainer-mode was given.
-if test "${enable_maintainer_mode+set}" = set; then
-  enableval="$enable_maintainer_mode"
-  case "${enableval}" in
-  yes)	MAINT="" USE_MAINTAINER_MODE=yes ;;
-  no)	MAINT="#" ;;
-  *)	{ echo "configure: error: "--enable-maintainer-mode does not take a value"" 1>&2; exit 1; }; MAINT="#" ;;
-esac
-if test x"$silent" != x"yes" && test x"$MAINT" = x""; then
-  echo "Setting maintainer mode" 6>&1
-fi
-else
-  MAINT="#"
-fi
-
-
-
-# Check whether --enable-sim-bswap or --disable-sim-bswap was given.
-if test "${enable_sim_bswap+set}" = set; then
-  enableval="$enable_sim_bswap"
-  case "${enableval}" in
-  yes)	sim_bswap="-DWITH_BSWAP=1 -DUSE_BSWAP=1";;
-  no)	sim_bswap="-DWITH_BSWAP=0";;
-  *)	{ echo "configure: error: "--enable-sim-bswap does not take a value"" 1>&2; exit 1; }; sim_bswap="";;
-esac
-if test x"$silent" != x"yes" && test x"$sim_bswap" != x""; then
-  echo "Setting bswap flags = $sim_bswap" 6>&1
-fi
-else
-  sim_bswap=""
-fi
-
-
-
-# Check whether --enable-sim-cflags or --disable-sim-cflags was given.
-if test "${enable_sim_cflags+set}" = set; then
-  enableval="$enable_sim_cflags"
-  case "${enableval}" in
-  yes)	 sim_cflags="-O2 -fomit-frame-pointer";;
-  trace) { echo "configure: error: "Please use --enable-sim-debug instead."" 1>&2; exit 1; }; sim_cflags="";;
-  no)	 sim_cflags="";;
-  *)	 sim_cflags=`echo "${enableval}" | sed -e "s/,/ /g"`;;
-esac
-if test x"$silent" != x"yes" && test x"$sim_cflags" != x""; then
-  echo "Setting sim cflags = $sim_cflags" 6>&1
-fi
-else
-  sim_cflags=""
-fi
-
-
-
-# Check whether --enable-sim-debug or --disable-sim-debug was given.
-if test "${enable_sim_debug+set}" = set; then
-  enableval="$enable_sim_debug"
-  case "${enableval}" in
-  yes) sim_debug="-DDEBUG=7 -DWITH_DEBUG=7";;
-  no)  sim_debug="-DDEBUG=0 -DWITH_DEBUG=0";;
-  *)   sim_debug="-DDEBUG='(${enableval})' -DWITH_DEBUG='(${enableval})'";;
-esac
-if test x"$silent" != x"yes" && test x"$sim_debug" != x""; then
-  echo "Setting sim debug = $sim_debug" 6>&1
-fi
-else
-  sim_debug=""
-fi
-
-
-
-# Check whether --enable-sim-stdio or --disable-sim-stdio was given.
-if test "${enable_sim_stdio+set}" = set; then
-  enableval="$enable_sim_stdio"
-  case "${enableval}" in
-  yes)	sim_stdio="-DWITH_STDIO=DO_USE_STDIO";;
-  no)	sim_stdio="-DWITH_STDIO=DONT_USE_STDIO";;
-  *)	{ echo "configure: error: "Unknown value $enableval passed to --enable-sim-stdio"" 1>&2; exit 1; }; sim_stdio="";;
-esac
-if test x"$silent" != x"yes" && test x"$sim_stdio" != x""; then
-  echo "Setting stdio flags = $sim_stdio" 6>&1
-fi
-else
-  sim_stdio=""
-fi
-
-
-
-# Check whether --enable-sim-trace or --disable-sim-trace was given.
-if test "${enable_sim_trace+set}" = set; then
-  enableval="$enable_sim_trace"
-  case "${enableval}" in
-  yes)	sim_trace="-DTRACE=1 -DWITH_TRACE=-1";;
-  no)	sim_trace="-DTRACE=0 -DWITH_TRACE=0";;
-  [-0-9]*)
-	sim_trace="-DTRACE='(${enableval})' -DWITH_TRACE='(${enableval})'";;
-  [a-z]*)
-	sim_trace=""
-	for x in `echo "$enableval" | sed -e "s/,/ /g"`; do
-	  if test x"$sim_trace" = x; then
-	    sim_trace="-DWITH_TRACE='(TRACE_$x"
-	  else
-	    sim_trace="${sim_trace}|TRACE_$x"
-	  fi
-	done
-	sim_trace="$sim_trace)'" ;;
-esac
-if test x"$silent" != x"yes" && test x"$sim_trace" != x""; then
-  echo "Setting sim trace = $sim_trace" 6>&1
-fi
-else
-  sim_trace=""
-fi
-
-
-
-# Check whether --enable-sim-profile or --disable-sim-profile was given.
-if test "${enable_sim_profile+set}" = set; then
-  enableval="$enable_sim_profile"
-  case "${enableval}" in
-  yes)	sim_profile="-DPROFILE=1 -DWITH_PROFILE=-1";;
-  no)	sim_profile="-DPROFILE=0 -DWITH_PROFILE=0";;
-  [-0-9]*)
-	sim_profile="-DPROFILE='(${enableval})' -DWITH_PROFILE='(${enableval})'";;
-  [a-z]*)
-	sim_profile=""
-	for x in `echo "$enableval" | sed -e "s/,/ /g"`; do
-	  if test x"$sim_profile" = x; then
-	    sim_profile="-DWITH_PROFILE='(PROFILE_$x"
-	  else
-	    sim_profile="${sim_profile}|PROFILE_$x"
-	  fi
-	done
-	sim_profile="$sim_profile)'" ;;
-esac
-if test x"$silent" != x"yes" && test x"$sim_profile" != x""; then
-  echo "Setting sim profile = $sim_profile" 6>&1
-fi
-else
-  sim_profile=""
-fi
-
-
-
-echo $ac_n "checking return type of signal handlers""... $ac_c" 1>&6
-echo "configure:3338: checking return type of signal handlers" >&5
-if eval "test \"`echo '$''{'ac_cv_type_signal'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  cat > conftest.$ac_ext <<EOF
-#line 3343 "configure"
-#include "confdefs.h"
-#include <sys/types.h>
-#include <signal.h>
-#ifdef signal
-#undef signal
-#endif
-#ifdef __cplusplus
-extern "C" void (*signal (int, void (*)(int)))(int);
-#else
-void (*signal ()) ();
-#endif
-
-int main() {
-int i;
-; return 0; }
-EOF
-if { (eval echo configure:3360: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
-  rm -rf conftest*
-  ac_cv_type_signal=void
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  ac_cv_type_signal=int
-fi
-rm -f conftest*
-fi
-
-echo "$ac_t""$ac_cv_type_signal" 1>&6
-cat >> confdefs.h <<EOF
-#define RETSIGTYPE $ac_cv_type_signal
-EOF
-
-
-
-echo $ac_n "checking for executable suffix""... $ac_c" 1>&6
-echo "configure:3380: checking for executable suffix" >&5
-if eval "test \"`echo '$''{'am_cv_exeext'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  if test "$CYGWIN32" = yes; then
-am_cv_exeext=.exe
-else
-cat > am_c_test.c << 'EOF'
-int main() {
-/* Nothing needed here */
-}
-EOF
-${CC-cc} -o am_c_test $CFLAGS $CPPFLAGS $LDFLAGS am_c_test.c $LIBS 1>&5
-am_cv_exeext=`ls am_c_test.* | grep -v am_c_test.c | sed -e s/am_c_test//`
-rm -f am_c_test*
-fi
-
-test x"${am_cv_exeext}" = x && am_cv_exeext=no
-fi
-EXEEXT=""
-test x"${am_cv_exeext}" != xno && EXEEXT=${am_cv_exeext}
-echo "$ac_t""${am_cv_exeext}" 1>&6
-
-
-sim_link_files=
-sim_link_links=
-
-sim_link_links=tconfig.h
-if test -f ${srcdir}/tconfig.in
-then
-  sim_link_files=tconfig.in
-else
-  sim_link_files=../common/tconfig.in
-fi
-
-# targ-vals.def points to the libc macro description file.
-case "${target}" in
-*-*-*) TARG_VALS_DEF=../common/nltvals.def ;;
-esac
-sim_link_files="${sim_link_files} ${TARG_VALS_DEF}"
-sim_link_links="${sim_link_links} targ-vals.def"
-
-
-
-sim_link_files="${sim_link_files} m32r-sim.h ../../opcodes/m32r-opc.h"
-sim_link_links="${sim_link_links} cpu-sim.h cpu-opc.h"
-
-
-wire_endian="BIG_ENDIAN"
-default_endian=""
-# Check whether --enable-sim-endian or --disable-sim-endian was given.
-if test "${enable_sim_endian+set}" = set; then
-  enableval="$enable_sim_endian"
-  case "${enableval}" in
-  b*|B*) sim_endian="-DWITH_TARGET_BYTE_ORDER=BIG_ENDIAN";;
-  l*|L*) sim_endian="-DWITH_TARGET_BYTE_ORDER=LITTLE_ENDIAN";;
-  yes)	 if test x"$wire_endian" != x; then
-	   sim_endian="-DWITH_TARGET_BYTE_ORDER=${wire_endian}"
-	 else
-           if test x"$default_endian" != x; then
-	     sim_endian="-DWITH_TARGET_BYTE_ORDER=${default_endian}"
-	   else
-	     echo "No hard-wired endian for target $target" 1>&6
-	     sim_endian="-DWITH_TARGET_BYTE_ORDER=0"
-	   fi
-	 fi;;
-  no)	 if test x"$default_endian" != x; then
-	   sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${default_endian}"
-	 else
-	   if test x"$wire_endian" != x; then
-	     sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${wire_endian}"
-	   else
-	     echo "No default endian for target $target" 1>&6
-	     sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=0"
-	   fi
-	 fi;;
-  *)	 { echo "configure: error: "Unknown value $enableval for --enable-sim-endian"" 1>&2; exit 1; }; sim_endian="";;
-esac
-if test x"$silent" != x"yes" && test x"$sim_endian" != x""; then
-  echo "Setting endian flags = $sim_endian" 6>&1
-fi
-else
-  if test x"$default_endian" != x; then
-  sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${default_endian}"
-else
-  if test x"$wire_endian" != x; then
-    sim_endian="-DWITH_TARGET_BYTE_ORDER=${wire_endian}"
-  else
-    sim_endian=
-  fi
-fi
-fi
-
-wire_alignment="NONSTRICT_ALIGNMENT"
-default_alignment=""
-
-# Check whether --enable-sim-alignment or --disable-sim-alignment was given.
-if test "${enable_sim_alignment+set}" = set; then
-  enableval="$enable_sim_alignment"
-  case "${enableval}" in
-  strict | STRICT)       sim_alignment="-DWITH_ALIGNMENT=STRICT_ALIGNMENT";;
-  nonstrict | NONSTRICT) sim_alignment="-DWITH_ALIGNMENT=NONSTRICT_ALIGNMENT";;
-  forced | FORCED)       sim_alignment="-DWITH_ALIGNMENT=FORCED_ALIGNMENT";;
-  yes) if test x"$wire_alignment" != x; then
-	 sim_alignment="-DWITH_ALIGNMENT=${wire_alignment}"
-       else
-         if test x"$default_alignment" != x; then
-           sim_alignment="-DWITH_ALIGNMENT=${default_alignment}"
-         else
-	   echo "No hard-wired alignment for target $target" 1>&6
-	   sim_alignment="-DWITH_ALIGNMENT=0"
-         fi
-       fi;;
-  no)  if test x"$default_alignment" != x; then
-	 sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${default_alignment}"
-       else
-         if test x"$wire_alignment" != x; then
-	   sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${wire_alignment}"
-         else
-           echo "No default alignment for target $target" 1>&6
-           sim_alignment="-DWITH_DEFAULT_ALIGNMENT=0"
-         fi
-       fi;;
-  *)   { echo "configure: error: "Unknown value $enableval passed to --enable-sim-alignment"" 1>&2; exit 1; }; sim_alignment="";;
-esac
-if test x"$silent" != x"yes" && test x"$sim_alignment" != x""; then
-  echo "Setting alignment flags = $sim_alignment" 6>&1
-fi
-else
-  if test x"$default_alignment" != x; then
-  sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${default_alignment}"
-else
-  if test x"$wire_alignment" != x; then
-    sim_alignment="-DWITH_ALIGNMENT=${wire_alignment}"
-  else
-    sim_alignment=
-  fi
-fi
-fi
-
-
-# Check whether --enable-sim-hostendian or --disable-sim-hostendian was given.
-if test "${enable_sim_hostendian+set}" = set; then
-  enableval="$enable_sim_hostendian"
-  case "${enableval}" in
-  no)	 sim_hostendian="-DWITH_HOST_BYTE_ORDER=0";;
-  b*|B*) sim_hostendian="-DWITH_HOST_BYTE_ORDER=BIG_ENDIAN";;
-  l*|L*) sim_hostendian="-DWITH_HOST_BYTE_ORDER=LITTLE_ENDIAN";;
-  *)	 { echo "configure: error: "Unknown value $enableval for --enable-sim-hostendian"" 1>&2; exit 1; }; sim_hostendian="";;
-esac
-if test x"$silent" != x"yes" && test x"$sim_hostendian" != x""; then
-  echo "Setting hostendian flags = $sim_hostendian" 6>&1
-fi
-else
-  
-if test "x$cross_compiling" = "xno"; then
-  echo $ac_n "checking whether byte ordering is bigendian""... $ac_c" 1>&6
-echo "configure:3537: checking whether byte ordering is bigendian" >&5
-if eval "test \"`echo '$''{'ac_cv_c_bigendian'+set}'`\" = set"; then
-  echo $ac_n "(cached) $ac_c" 1>&6
-else
-  ac_cv_c_bigendian=unknown
-# See if sys/param.h defines the BYTE_ORDER macro.
-cat > conftest.$ac_ext <<EOF
-#line 3544 "configure"
-#include "confdefs.h"
-#include <sys/types.h>
-#include <sys/param.h>
-int main() {
-
-#if !BYTE_ORDER || !BIG_ENDIAN || !LITTLE_ENDIAN
- bogus endian macros
-#endif
-; return 0; }
-EOF
-if { (eval echo configure:3555: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
-  rm -rf conftest*
-  # It does; now see whether it defined to BIG_ENDIAN or not.
-cat > conftest.$ac_ext <<EOF
-#line 3559 "configure"
-#include "confdefs.h"
-#include <sys/types.h>
-#include <sys/param.h>
-int main() {
-
-#if BYTE_ORDER != BIG_ENDIAN
- not big endian
-#endif
-; return 0; }
-EOF
-if { (eval echo configure:3570: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
-  rm -rf conftest*
-  ac_cv_c_bigendian=yes
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -rf conftest*
-  ac_cv_c_bigendian=no
-fi
-rm -f conftest*
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-fi
-rm -f conftest*
-if test $ac_cv_c_bigendian = unknown; then
-if test "$cross_compiling" = yes; then
-    { echo "configure: error: can not run test program while cross compiling" 1>&2; exit 1; }
-else
-  cat > conftest.$ac_ext <<EOF
-#line 3590 "configure"
-#include "confdefs.h"
-main () {
-  /* Are we little or big endian?  From Harbison&Steele.  */
-  union
-  {
-    long l;
-    char c[sizeof (long)];
-  } u;
-  u.l = 1;
-  exit (u.c[sizeof (long) - 1] == 1);
-}
-EOF
-if { (eval echo configure:3603: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
-then
-  ac_cv_c_bigendian=no
-else
-  echo "configure: failed program was:" >&5
-  cat conftest.$ac_ext >&5
-  rm -fr conftest*
-  ac_cv_c_bigendian=yes
-fi
-rm -fr conftest*
-fi
-
-fi
-fi
-
-echo "$ac_t""$ac_cv_c_bigendian" 1>&6
-if test $ac_cv_c_bigendian = yes; then
-  cat >> confdefs.h <<\EOF
-#define WORDS_BIGENDIAN 1
-EOF
-
-fi
-
-  if test $ac_cv_c_bigendian = yes; then
-    sim_hostendian="-DWITH_HOST_BYTE_ORDER=BIG_ENDIAN"
-  else
-    sim_hostendian="-DWITH_HOST_BYTE_ORDER=LITTLE_ENDIAN"
-  fi
-else
-  sim_hostendian="-DWITH_HOST_BYTE_ORDER=0"
-fi
-fi
-
-
-default_sim_scache="16384"
-# Check whether --enable-sim-scache or --disable-sim-scache was given.
-if test "${enable_sim_scache+set}" = set; then
-  enableval="$enable_sim_scache"
-  case "${enableval}" in
-  yes)	sim_scache="-DWITH_SCACHE=${default_sim_scache}";;
-  no)	sim_scache="-DWITH_SCACHE=0" ;;
-  [0-9]*) sim_cache=${enableval};;
-  *)	{ echo "configure: error: "Bad value $enableval passed to --enable-sim-scache"" 1>&2; exit 1; };
-	sim_scache="";;
-esac
-if test x"$silent" != x"yes" && test x"$sim_scache" != x""; then
-  echo "Setting scache size = $sim_scache" 6>&1
-fi
-else
-  sim_scache="-DWITH_SCACHE=${default_sim_scache}"
-fi
-
-
-
-default_sim_default_model="m32r/d"
-# Check whether --enable-sim-default-model or --disable-sim-default-model was given.
-if test "${enable_sim_default_model+set}" = set; then
-  enableval="$enable_sim_default_model"
-  case "${enableval}" in
-  yes|no) { echo "configure: error: "Missing argument to --enable-sim-default-model"" 1>&2; exit 1; };;
-  *)	sim_default_model="-DWITH_DEFAULT_MODEL='\"${enableval}\"'";;
-esac
-if test x"$silent" != x"yes" && test x"$sim_default_model" != x""; then
-  echo "Setting default model = $sim_default_model" 6>&1
-fi
-else
-  sim_default_model="-DWITH_DEFAULT_MODEL='\"${default_sim_default_model}\"'"
-fi
-
-
-
-# Check whether --enable-sim-environment or --disable-sim-environment was given.
-if test "${enable_sim_environment+set}" = set; then
-  enableval="$enable_sim_environment"
-  case "${enableval}" in
-  all | ALL)             sim_environment="-DWITH_ENVIRONMENT=ALL_ENVIRONMENT";;
-  user | USER)           sim_environment="-DWITH_ENVIRONMENT=USER_ENVIRONMENT";;
-  virtual | VIRTUAL)     sim_environment="-DWITH_ENVIRONMENT=VIRTUAL_ENVIRONMENT";;
-  operating | OPERATING) sim_environment="-DWITH_ENVIRONMENT=OPERATING_ENVIRONMENT";;
-  *)   { echo "configure: error: "Unknown value $enableval passed to --enable-sim-environment"" 1>&2; exit 1; };
-       sim_environment="";;
-esac
-if test x"$silent" != x"yes" && test x"$sim_environment" != x""; then
-  echo "Setting sim environment = $sim_environment" 6>&1
-fi
-else
-  sim_environment="-DWITH_ENVIRONMENT=ALL_ENVIRONMENT"
-fi
-
-
-default_sim_inline=""
-# Check whether --enable-sim-inline or --disable-sim-inline was given.
-if test "${enable_sim_inline+set}" = set; then
-  enableval="$enable_sim_inline"
-  sim_inline=""
-case "$enableval" in
-  no)		sim_inline="-DDEFAULT_INLINE=0";;
-  0)		sim_inline="-DDEFAULT_INLINE=0";;
-  yes | 2)	sim_inline="-DDEFAULT_INLINE=ALL_C_INLINE";;
-  1)		sim_inline="-DDEFAULT_INLINE=INLINE_LOCALS";;
-  *) for x in `echo "$enableval" | sed -e "s/,/ /g"`; do
-       new_flag=""
-       case "$x" in
-	 *_INLINE=*)	new_flag="-D$x";;
-	 *=*)		new_flag=`echo "$x" | sed -e "s/=/_INLINE=/" -e "s/^/-D/"`;;
-	 *_INLINE)	new_flag="-D$x=ALL_C_INLINE";;
-	 *)		new_flag="-D$x""_INLINE=ALL_C_INLINE";;
-       esac
-       if test x"$sim_inline" = x""; then
-	 sim_inline="$new_flag"
-       else
-	 sim_inline="$sim_inline $new_flag"
-       fi
-     done;;
-esac
-if test x"$silent" != x"yes" && test x"$sim_inline" != x""; then
-  echo "Setting inline flags = $sim_inline" 6>&1
-fi
-else
-  
-if test "x$cross_compiling" = "xno"; then
-  if test x"$GCC" != "x" -a x"${default_sim_inline}" != "x" ; then
-    sim_inline="${default_sim_inline}"
-    if test x"$silent" != x"yes"; then
-      echo "Setting inline flags = $sim_inline" 6>&1
-    fi
-  else
-    sim_inline=""
-  fi
-else
-  sim_inline="-DDEFAULT_INLINE=0"
-fi
-fi
-
-
-cgen_maint=no
-# Default is to use one in build tree.
-cgen=../../cgen/cgen
-cgendir='$(srcdir)/../../cgen'
-# Having --enable-maintainer-mode take arguments is another way to go.
-# ??? One can argue --with is more appropriate if one wants to specify
-# a directory name, but what we're doing here is an enable/disable kind
-# of thing and specifying both --enable and --with is klunky.
-# If you reeely want this to be --with, go ahead and change it.
-# Check whether --enable-cgen-maint or --disable-cgen-maint was given.
-if test "${enable_cgen_maint+set}" = set; then
-  enableval="$enable_cgen_maint"
-  case "${enableval}" in
-  yes)	cgen_maint=yes ;;
-  no)	cgen_maint=no ;;
-  *)
-	# argument is cgen install directory (not implemented yet).
-	# Having a `share' directory might be more appropriate for the .scm,
-	# .cpu, etc. files.
-	cgendir=${cgen_maint}/lib/cgen
-	cgen=${cgendir}/bin/cgen
-	;;
-esac
-fi
-if test x${cgen_maint} != xno ; then
-  CGEN_MAINT=''
-else
-  CGEN_MAINT='#'
-fi
-
-
-
-
-
-
-trap '' 1 2 15
-cat > confcache <<\EOF
-# This file is a shell script that caches the results of configure
-# tests run on this system so they can be shared between configure
-# scripts and configure runs.  It is not useful on other systems.
-# If it contains results you don't want to keep, you may remove or edit it.
-#
-# By default, configure uses ./config.cache as the cache file,
-# creating it if it does not exist already.  You can give configure
-# the --cache-file=FILE option to use a different cache file; that is
-# what configure does when it calls configure scripts in
-# subdirectories, so they share the cache.
-# Giving --cache-file=/dev/null disables caching, for debugging configure.
-# config.status only pays attention to the cache file if you give it the
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-#
-EOF
-# The following way of writing the cache mishandles newlines in values,
-# but we know of no workaround that is simple, portable, and efficient.
-# So, don't put newlines in cache variables' values.
-# Ultrix sh set writes to stderr and can't be redirected directly,
-# and sets the high bit in the cache file unless we assign to the vars.
-(set) 2>&1 |
-  case `(ac_space=' '; set) 2>&1 | grep ac_space` in
-  *ac_space=\ *)
-    # `set' does not quote correctly, so add quotes (double-quote substitution
-    # turns \\\\ into \\, and sed turns \\ into \).
-    sed -n \
-      -e "s/'/'\\\\''/g" \
-      -e "s/^\\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\\)=\\(.*\\)/\\1=\${\\1='\\2'}/p"
-    ;;
-  *)
-    # `set' quotes correctly as required by POSIX, so do not add quotes.
-    sed -n -e 's/^\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\)=\(.*\)/\1=${\1=\2}/p'
-    ;;
-  esac >> confcache
-if cmp -s $cache_file confcache; then
-  :
-else
-  if test -w $cache_file; then
-    echo "updating cache $cache_file"
-    cat confcache > $cache_file
-  else
-    echo "not updating unwritable cache $cache_file"
-  fi
-fi
-rm -f confcache
-
-trap 'rm -fr conftest* confdefs* core core.* *.core $ac_clean_files; exit 1' 1 2 15
-
-test "x$prefix" = xNONE && prefix=$ac_default_prefix
-# Let make expand exec_prefix.
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-
-# Any assignment to VPATH causes Sun make to only execute
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-if test "x$srcdir" = x.; then
-  ac_vpsub='/^[ 	]*VPATH[ 	]*=[^:]*$/d'
-fi
-
-trap 'rm -f $CONFIG_STATUS conftest*; exit 1' 1 2 15
-
-DEFS=-DHAVE_CONFIG_H
-
-# Without the "./", some shells look in PATH for config.status.
-: ${CONFIG_STATUS=./config.status}
-
-echo creating $CONFIG_STATUS
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-cat > $CONFIG_STATUS <<EOF
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-ac_cs_usage="Usage: $CONFIG_STATUS [--recheck] [--version] [--help]"
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-ac_given_srcdir=$srcdir
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-
-trap 'rm -fr `echo "Makefile.sim:Makefile.in Make-common.sim:../common/Make-common.in .gdbinit:../common/gdbinit.in config.h:config.in" | sed "s/:[^ ]*//g"` conftest*; exit 1' 1 2 15
-EOF
-cat >> $CONFIG_STATUS <<EOF
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-# Protect against being on the right side of a sed subst in config.status.
-sed 's/%@/@@/; s/@%/@@/; s/%g\$/@g/; /@g\$/s/[\\\\&%]/\\\\&/g;
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-$ac_vpsub
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-s%@sim_scache@%$sim_scache%g
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-s%@sim_regparm@%$sim_regparm%g
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-s%@exec_prefix@%$exec_prefix%g
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-s%@mandir@%$mandir%g
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-s%@target_alias@%$target_alias%g
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-s%@POFILES@%$POFILES%g
-s%@POSUB@%$POSUB%g
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-s%@l@%$l%g
-s%@MAINT@%$MAINT%g
-s%@sim_bswap@%$sim_bswap%g
-s%@sim_cflags@%$sim_cflags%g
-s%@sim_debug@%$sim_debug%g
-s%@sim_stdio@%$sim_stdio%g
-s%@sim_trace@%$sim_trace%g
-s%@sim_profile@%$sim_profile%g
-s%@EXEEXT@%$EXEEXT%g
-s%@CGEN_MAINT@%$CGEN_MAINT%g
-s%@cgendir@%$cgendir%g
-s%@cgen@%$cgen%g
-
-CEOF
-EOF
-
-cat >> $CONFIG_STATUS <<\EOF
-
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-ac_more_lines=:
-ac_sed_cmds=""
-while $ac_more_lines; do
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-  fi
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-
-cat >> $CONFIG_STATUS <<EOF
-
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-EOF
-cat >> $CONFIG_STATUS <<\EOF
-for ac_file in .. $CONFIG_FILES; do if test "x$ac_file" != x..; then
-  # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in".
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-       ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;;
-  *) ac_file_in="${ac_file}.in" ;;
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-    ac_dir_suffix="/`echo $ac_dir|sed 's%^\./%%'`"
-    # A "../" for each directory in $ac_dir_suffix.
-    ac_dots=`echo $ac_dir_suffix|sed 's%/[^/]*%../%g'`
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-    ac_dir_suffix= ac_dots=
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-  *) INSTALL="$ac_dots$ac_given_INSTALL" ;;
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-
-  echo creating "$ac_file"
-  rm -f "$ac_file"
-  configure_input="Generated automatically from `echo $ac_file_in|sed 's%.*/%%'` by configure."
-  case "$ac_file" in
-  *Makefile*) ac_comsub="1i\\
-# $configure_input" ;;
-  *) ac_comsub= ;;
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-
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-s%@top_srcdir@%$top_srcdir%g
-s%@INSTALL@%$INSTALL%g
-" $ac_file_inputs | (eval "$ac_sed_cmds") > $ac_file
-fi; done
-rm -f conftest.s*
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-# These sed commands are passed to sed as "A NAME B NAME C VALUE D", where
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-#
-# ac_d sets the value in "#define NAME VALUE" lines.
-ac_dA='s%^\([ 	]*\)#\([ 	]*define[ 	][ 	]*\)'
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-ac_dC='\3'
-ac_dD='%g'
-# ac_u turns "#undef NAME" with trailing blanks into "#define NAME VALUE".
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-ac_uB='\([ 	]\)%\1#\2define\3'
-ac_uC=' '
-ac_uD='\4%g'
-# ac_e turns "#undef NAME" without trailing blanks into "#define NAME VALUE".
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-ac_eB='$%\1#\2define\3'
-ac_eC=' '
-ac_eD='%g'
-
-if test "${CONFIG_HEADERS+set}" != set; then
-EOF
-cat >> $CONFIG_STATUS <<EOF
-  CONFIG_HEADERS="config.h:config.in"
-EOF
-cat >> $CONFIG_STATUS <<\EOF
-fi
-for ac_file in .. $CONFIG_HEADERS; do if test "x$ac_file" != x..; then
-  # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in".
-  case "$ac_file" in
-  *:*) ac_file_in=`echo "$ac_file"|sed 's%[^:]*:%%'`
-       ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;;
-  *) ac_file_in="${ac_file}.in" ;;
-  esac
-
-  echo creating $ac_file
-
-  rm -f conftest.frag conftest.in conftest.out
-  ac_file_inputs=`echo $ac_file_in|sed -e "s%^%$ac_given_srcdir/%" -e "s%:% $ac_given_srcdir/%g"`
-  cat $ac_file_inputs > conftest.in
-
-EOF
-
-# Transform confdefs.h into a sed script conftest.vals that substitutes
-# the proper values into config.h.in to produce config.h.  And first:
-# Protect against being on the right side of a sed subst in config.status.
-# Protect against being in an unquoted here document in config.status.
-rm -f conftest.vals
-cat > conftest.hdr <<\EOF
-s/[\\&%]/\\&/g
-s%[\\$`]%\\&%g
-s%#define \([A-Za-z_][A-Za-z0-9_]*\) *\(.*\)%${ac_dA}\1${ac_dB}\1${ac_dC}\2${ac_dD}%gp
-s%ac_d%ac_u%gp
-s%ac_u%ac_e%gp
-EOF
-sed -n -f conftest.hdr confdefs.h > conftest.vals
-rm -f conftest.hdr
-
-# This sed command replaces #undef with comments.  This is necessary, for
-# example, in the case of _POSIX_SOURCE, which is predefined and required
-# on some systems where configure will not decide to define it.
-cat >> conftest.vals <<\EOF
-s%^[ 	]*#[ 	]*undef[ 	][ 	]*[a-zA-Z_][a-zA-Z_0-9]*%/* & */%
-EOF
-
-# Break up conftest.vals because some shells have a limit on
-# the size of here documents, and old seds have small limits too.
-
-rm -f conftest.tail
-while :
-do
-  ac_lines=`grep -c . conftest.vals`
-  # grep -c gives empty output for an empty file on some AIX systems.
-  if test -z "$ac_lines" || test "$ac_lines" -eq 0; then break; fi
-  # Write a limited-size here document to conftest.frag.
-  echo '  cat > conftest.frag <<CEOF' >> $CONFIG_STATUS
-  sed ${ac_max_here_lines}q conftest.vals >> $CONFIG_STATUS
-  echo 'CEOF
-  sed -f conftest.frag conftest.in > conftest.out
-  rm -f conftest.in
-  mv conftest.out conftest.in
-' >> $CONFIG_STATUS
-  sed 1,${ac_max_here_lines}d conftest.vals > conftest.tail
-  rm -f conftest.vals
-  mv conftest.tail conftest.vals
-done
-rm -f conftest.vals
-
-cat >> $CONFIG_STATUS <<\EOF
-  rm -f conftest.frag conftest.h
-  echo "/* $ac_file.  Generated automatically by configure.  */" > conftest.h
-  cat conftest.in >> conftest.h
-  rm -f conftest.in
-  if cmp -s $ac_file conftest.h 2>/dev/null; then
-    echo "$ac_file is unchanged"
-    rm -f conftest.h
-  else
-    # Remove last slash and all that follows it.  Not all systems have dirname.
-      ac_dir=`echo $ac_file|sed 's%/[^/][^/]*$%%'`
-      if test "$ac_dir" != "$ac_file" && test "$ac_dir" != .; then
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-    fi
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-    mv conftest.h $ac_file
-  fi
-fi; done
-
-EOF
-
-cat >> $CONFIG_STATUS <<EOF
-ac_sources="$sim_link_files"
-ac_dests="$sim_link_links"
-EOF
-
-cat >> $CONFIG_STATUS <<\EOF
-srcdir=$ac_given_srcdir
-while test -n "$ac_sources"; do
-  set $ac_dests; ac_dest=$1; shift; ac_dests=$*
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-
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-    test ! -d "$ac_dest_dir" && mkdir "$ac_dest_dir"
-    ac_dest_dir_suffix="/`echo $ac_dest_dir|sed 's%^\./%%'`"
-    # A "../" for each directory in $ac_dest_dir_suffix.
-    ac_dots=`echo $ac_dest_dir_suffix|sed 's%/[^/]*%../%g'`
-  else
-    ac_dest_dir_suffix= ac_dots=
-  fi
-
-  case "$srcdir" in
-  [/$]*) ac_rel_source="$srcdir/$ac_source" ;;
-  *) ac_rel_source="$ac_dots$srcdir/$ac_source" ;;
-  esac
-
-  # Make a symlink if possible; otherwise try a hard link.
-  if ln -s $ac_rel_source $ac_dest 2>/dev/null ||
-    ln $srcdir/$ac_source $ac_dest; then :
-  else
-    { echo "configure: error: can not link $ac_dest to $srcdir/$ac_source" 1>&2; exit 1; }
-  fi
-done
-EOF
-cat >> $CONFIG_STATUS <<EOF
-
-EOF
-cat >> $CONFIG_STATUS <<\EOF
-case "x$CONFIG_FILES" in
- xMakefile*)
-   echo "Merging Makefile.sim+Make-common.sim into Makefile ..."
-   rm -f Makesim1.tmp Makesim2.tmp Makefile
-   sed -n -e '/^## COMMON_PRE_/,/^## End COMMON_PRE_/ p' <Make-common.sim >Makesim1.tmp
-   sed -n -e '/^## COMMON_POST_/,/^## End COMMON_POST_/ p' <Make-common.sim >Makesim2.tmp
-   sed -e '/^## COMMON_PRE_/ r Makesim1.tmp' \
-	-e '/^## COMMON_POST_/ r Makesim2.tmp' \
-	<Makefile.sim >Makefile
-   rm -f Makefile.sim Make-common.sim Makesim1.tmp Makesim2.tmp
-   ;;
- esac
- case "x$CONFIG_HEADERS" in xconfig.h:config.in) echo > stamp-h ;; esac
-
-exit 0
-EOF
-chmod +x $CONFIG_STATUS
-rm -fr confdefs* $ac_clean_files
-test "$no_create" = yes || ${CONFIG_SHELL-/bin/sh} $CONFIG_STATUS || exit 1
-
-
diff --git a/sim/m32r/configure.in b/sim/m32r/configure.in
deleted file mode 100644
index f598f29..0000000
--- a/sim/m32r/configure.in
+++ /dev/null
@@ -1,17 +0,0 @@
-dnl Process this file with autoconf to produce a configure script.
-sinclude(../common/aclocal.m4)
-AC_PREREQ(2.5)dnl
-AC_INIT(Makefile.in)
-
-SIM_AC_COMMON
-
-SIM_AC_OPTION_ENDIAN(BIG_ENDIAN)
-SIM_AC_OPTION_ALIGNMENT(STRICT_ALIGNMENT)
-SIM_AC_OPTION_HOSTENDIAN
-SIM_AC_OPTION_SCACHE(16384)
-SIM_AC_OPTION_DEFAULT_MODEL(m32r/d)
-SIM_AC_OPTION_ENVIRONMENT
-SIM_AC_OPTION_INLINE()
-SIM_AC_OPTION_CGEN_MAINT
-
-SIM_AC_OUTPUT
diff --git a/sim/m32r/cpu.c b/sim/m32r/cpu.c
deleted file mode 100644
index e138231..0000000
--- a/sim/m32r/cpu.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/* Misc. support for CPU family m32rbf.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
-
-This file is part of the GNU Simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#define WANT_CPU m32rbf
-#define WANT_CPU_M32RBF
-
-#include "sim-main.h"
-
-/* Get the value of h-pc.  */
-
-USI
-m32rbf_h_pc_get (SIM_CPU *current_cpu)
-{
-  return CPU (h_pc);
-}
-
-/* Set a value for h-pc.  */
-
-void
-m32rbf_h_pc_set (SIM_CPU *current_cpu, USI newval)
-{
-  CPU (h_pc) = newval;
-}
-
-/* Get the value of h-gr.  */
-
-SI
-m32rbf_h_gr_get (SIM_CPU *current_cpu, UINT regno)
-{
-  return CPU (h_gr[regno]);
-}
-
-/* Set a value for h-gr.  */
-
-void
-m32rbf_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
-{
-  CPU (h_gr[regno]) = newval;
-}
-
-/* Get the value of h-cr.  */
-
-USI
-m32rbf_h_cr_get (SIM_CPU *current_cpu, UINT regno)
-{
-  return GET_H_CR (regno);
-}
-
-/* Set a value for h-cr.  */
-
-void
-m32rbf_h_cr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
-{
-  SET_H_CR (regno, newval);
-}
-
-/* Get the value of h-accum.  */
-
-DI
-m32rbf_h_accum_get (SIM_CPU *current_cpu)
-{
-  return GET_H_ACCUM ();
-}
-
-/* Set a value for h-accum.  */
-
-void
-m32rbf_h_accum_set (SIM_CPU *current_cpu, DI newval)
-{
-  SET_H_ACCUM (newval);
-}
-
-/* Get the value of h-accums.  */
-
-DI
-m32rbf_h_accums_get (SIM_CPU *current_cpu, UINT regno)
-{
-  return GET_H_ACCUMS (regno);
-}
-
-/* Set a value for h-accums.  */
-
-void
-m32rbf_h_accums_set (SIM_CPU *current_cpu, UINT regno, DI newval)
-{
-  SET_H_ACCUMS (regno, newval);
-}
-
-/* Get the value of h-cond.  */
-
-BI
-m32rbf_h_cond_get (SIM_CPU *current_cpu)
-{
-  return CPU (h_cond);
-}
-
-/* Set a value for h-cond.  */
-
-void
-m32rbf_h_cond_set (SIM_CPU *current_cpu, BI newval)
-{
-  CPU (h_cond) = newval;
-}
-
-/* Get the value of h-psw.  */
-
-UQI
-m32rbf_h_psw_get (SIM_CPU *current_cpu)
-{
-  return GET_H_PSW ();
-}
-
-/* Set a value for h-psw.  */
-
-void
-m32rbf_h_psw_set (SIM_CPU *current_cpu, UQI newval)
-{
-  SET_H_PSW (newval);
-}
-
-/* Get the value of h-bpsw.  */
-
-UQI
-m32rbf_h_bpsw_get (SIM_CPU *current_cpu)
-{
-  return CPU (h_bpsw);
-}
-
-/* Set a value for h-bpsw.  */
-
-void
-m32rbf_h_bpsw_set (SIM_CPU *current_cpu, UQI newval)
-{
-  CPU (h_bpsw) = newval;
-}
-
-/* Get the value of h-bbpsw.  */
-
-UQI
-m32rbf_h_bbpsw_get (SIM_CPU *current_cpu)
-{
-  return CPU (h_bbpsw);
-}
-
-/* Set a value for h-bbpsw.  */
-
-void
-m32rbf_h_bbpsw_set (SIM_CPU *current_cpu, UQI newval)
-{
-  CPU (h_bbpsw) = newval;
-}
-
-/* Get the value of h-lock.  */
-
-BI
-m32rbf_h_lock_get (SIM_CPU *current_cpu)
-{
-  return CPU (h_lock);
-}
-
-/* Set a value for h-lock.  */
-
-void
-m32rbf_h_lock_set (SIM_CPU *current_cpu, BI newval)
-{
-  CPU (h_lock) = newval;
-}
-
-/* Record trace results for INSN.  */
-
-void
-m32rbf_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,
-			    int *indices, TRACE_RECORD *tr)
-{
-}
diff --git a/sim/m32r/cpu.h b/sim/m32r/cpu.h
deleted file mode 100644
index 42d2d56..0000000
--- a/sim/m32r/cpu.h
+++ /dev/null
@@ -1,860 +0,0 @@
-/* CPU family header for m32rbf.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
-
-This file is part of the GNU Simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#ifndef CPU_M32RBF_H
-#define CPU_M32RBF_H
-
-/* Maximum number of instructions that are fetched at a time.
-   This is for LIW type instructions sets (e.g. m32r).  */
-#define MAX_LIW_INSNS 2
-
-/* Maximum number of instructions that can be executed in parallel.  */
-#define MAX_PARALLEL_INSNS 1
-
-/* CPU state information.  */
-typedef struct {
-  /* Hardware elements.  */
-  struct {
-  /* program counter */
-  USI h_pc;
-#define GET_H_PC() CPU (h_pc)
-#define SET_H_PC(x) (CPU (h_pc) = (x))
-  /* general registers */
-  SI h_gr[16];
-#define GET_H_GR(a1) CPU (h_gr)[a1]
-#define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
-  /* control registers */
-  USI h_cr[16];
-/* GET_H_CR macro user-written */
-/* SET_H_CR macro user-written */
-  /* accumulator */
-  DI h_accum;
-/* GET_H_ACCUM macro user-written */
-/* SET_H_ACCUM macro user-written */
-/* start-sanitize-m32rx */
-  /* accumulators */
-  DI h_accums[2];
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
-/* GET_H_ACCUMS macro user-written */
-/* SET_H_ACCUMS macro user-written */
-/* end-sanitize-m32rx */
-  /* condition bit */
-  BI h_cond;
-#define GET_H_COND() CPU (h_cond)
-#define SET_H_COND(x) (CPU (h_cond) = (x))
-  /* psw part of psw */
-  UQI h_psw;
-/* GET_H_PSW macro user-written */
-/* SET_H_PSW macro user-written */
-  /* backup psw */
-  UQI h_bpsw;
-#define GET_H_BPSW() CPU (h_bpsw)
-#define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
-  /* backup bpsw */
-  UQI h_bbpsw;
-#define GET_H_BBPSW() CPU (h_bbpsw)
-#define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
-  /* lock */
-  BI h_lock;
-#define GET_H_LOCK() CPU (h_lock)
-#define SET_H_LOCK(x) (CPU (h_lock) = (x))
-  } hardware;
-#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
-} M32RBF_CPU_DATA;
-
-/* Cover fns for register access.  */
-USI m32rbf_h_pc_get (SIM_CPU *);
-void m32rbf_h_pc_set (SIM_CPU *, USI);
-SI m32rbf_h_gr_get (SIM_CPU *, UINT);
-void m32rbf_h_gr_set (SIM_CPU *, UINT, SI);
-USI m32rbf_h_cr_get (SIM_CPU *, UINT);
-void m32rbf_h_cr_set (SIM_CPU *, UINT, USI);
-DI m32rbf_h_accum_get (SIM_CPU *);
-void m32rbf_h_accum_set (SIM_CPU *, DI);
-DI m32rbf_h_accums_get (SIM_CPU *, UINT);
-void m32rbf_h_accums_set (SIM_CPU *, UINT, DI);
-BI m32rbf_h_cond_get (SIM_CPU *);
-void m32rbf_h_cond_set (SIM_CPU *, BI);
-UQI m32rbf_h_psw_get (SIM_CPU *);
-void m32rbf_h_psw_set (SIM_CPU *, UQI);
-UQI m32rbf_h_bpsw_get (SIM_CPU *);
-void m32rbf_h_bpsw_set (SIM_CPU *, UQI);
-UQI m32rbf_h_bbpsw_get (SIM_CPU *);
-void m32rbf_h_bbpsw_set (SIM_CPU *, UQI);
-BI m32rbf_h_lock_get (SIM_CPU *);
-void m32rbf_h_lock_set (SIM_CPU *, BI);
-
-/* These must be hand-written.  */
-extern CPUREG_FETCH_FN m32rbf_fetch_register;
-extern CPUREG_STORE_FN m32rbf_store_register;
-
-typedef struct {
-  UINT h_gr;
-} MODEL_M32R_D_DATA;
-
-typedef struct {
-  int empty;
-} MODEL_TEST_DATA;
-
-union sem_fields {
-    struct { /* empty sformat for unspecified field list */
-      int empty;
-    } fmt_empty;
-    struct { /* e.g. add $dr,$sr */
-      SI * i_dr;
-      SI * i_sr;
-      unsigned char in_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_add;
-    struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
-      INT f_simm16;
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_add3;
-    struct { /* e.g. and3 $dr,$sr,$uimm16 */
-      UINT f_uimm16;
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_and3;
-    struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
-      UINT f_uimm16;
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_or3;
-    struct { /* e.g. addi $dr,$simm8 */
-      INT f_simm8;
-      SI * i_dr;
-      unsigned char in_dr;
-      unsigned char out_dr;
-    } fmt_addi;
-    struct { /* e.g. addv $dr,$sr */
-      SI * i_dr;
-      SI * i_sr;
-      unsigned char in_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_addv;
-    struct { /* e.g. addv3 $dr,$sr,$simm16 */
-      INT f_simm16;
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_addv3;
-    struct { /* e.g. addx $dr,$sr */
-      SI * i_dr;
-      SI * i_sr;
-      unsigned char in_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_addx;
-    struct { /* e.g. cmp $src1,$src2 */
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_cmp;
-    struct { /* e.g. cmpi $src2,$simm16 */
-      INT f_simm16;
-      SI * i_src2;
-      unsigned char in_src2;
-    } fmt_cmpi;
-    struct { /* e.g. div $dr,$sr */
-      SI * i_dr;
-      SI * i_sr;
-      unsigned char in_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_div;
-    struct { /* e.g. ld $dr,@$sr */
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_ld;
-    struct { /* e.g. ld $dr,@($slo16,$sr) */
-      INT f_simm16;
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_ld_d;
-    struct { /* e.g. ldb $dr,@$sr */
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_ldb;
-    struct { /* e.g. ldb $dr,@($slo16,$sr) */
-      INT f_simm16;
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_ldb_d;
-    struct { /* e.g. ldh $dr,@$sr */
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_ldh;
-    struct { /* e.g. ldh $dr,@($slo16,$sr) */
-      INT f_simm16;
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_ldh_d;
-    struct { /* e.g. ld $dr,@$sr+ */
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-      unsigned char out_sr;
-    } fmt_ld_plus;
-    struct { /* e.g. ld24 $dr,$uimm24 */
-      ADDR i_uimm24;
-      SI * i_dr;
-      unsigned char out_dr;
-    } fmt_ld24;
-    struct { /* e.g. ldi8 $dr,$simm8 */
-      INT f_simm8;
-      SI * i_dr;
-      unsigned char out_dr;
-    } fmt_ldi8;
-    struct { /* e.g. ldi16 $dr,$hash$slo16 */
-      INT f_simm16;
-      SI * i_dr;
-      unsigned char out_dr;
-    } fmt_ldi16;
-    struct { /* e.g. lock $dr,@$sr */
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_lock;
-    struct { /* e.g. machi $src1,$src2 */
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_machi;
-    struct { /* e.g. mulhi $src1,$src2 */
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_mulhi;
-    struct { /* e.g. mv $dr,$sr */
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_mv;
-    struct { /* e.g. mvfachi $dr */
-      SI * i_dr;
-      unsigned char out_dr;
-    } fmt_mvfachi;
-    struct { /* e.g. mvfc $dr,$scr */
-      UINT f_r2;
-      SI * i_dr;
-      unsigned char out_dr;
-    } fmt_mvfc;
-    struct { /* e.g. mvtachi $src1 */
-      SI * i_src1;
-      unsigned char in_src1;
-    } fmt_mvtachi;
-    struct { /* e.g. mvtc $sr,$dcr */
-      UINT f_r1;
-      SI * i_sr;
-      unsigned char in_sr;
-    } fmt_mvtc;
-    struct { /* e.g. nop */
-      int empty;
-    } fmt_nop;
-    struct { /* e.g. rac */
-      int empty;
-    } fmt_rac;
-    struct { /* e.g. seth $dr,$hash$hi16 */
-      UINT f_hi16;
-      SI * i_dr;
-      unsigned char out_dr;
-    } fmt_seth;
-    struct { /* e.g. sll3 $dr,$sr,$simm16 */
-      INT f_simm16;
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_sll3;
-    struct { /* e.g. slli $dr,$uimm5 */
-      UINT f_uimm5;
-      SI * i_dr;
-      unsigned char in_dr;
-      unsigned char out_dr;
-    } fmt_slli;
-    struct { /* e.g. st $src1,@$src2 */
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_st;
-    struct { /* e.g. st $src1,@($slo16,$src2) */
-      INT f_simm16;
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_st_d;
-    struct { /* e.g. stb $src1,@$src2 */
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_stb;
-    struct { /* e.g. stb $src1,@($slo16,$src2) */
-      INT f_simm16;
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_stb_d;
-    struct { /* e.g. sth $src1,@$src2 */
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_sth;
-    struct { /* e.g. sth $src1,@($slo16,$src2) */
-      INT f_simm16;
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_sth_d;
-    struct { /* e.g. st $src1,@+$src2 */
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-      unsigned char out_src2;
-    } fmt_st_plus;
-    struct { /* e.g. unlock $src1,@$src2 */
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_unlock;
-  /* cti insns, kept separately so addr_cache is in fixed place */
-  struct {
-    union {
-    struct { /* e.g. bc.s $disp8 */
-      IADDR i_disp8;
-    } fmt_bc8;
-    struct { /* e.g. bc.l $disp24 */
-      IADDR i_disp24;
-    } fmt_bc24;
-    struct { /* e.g. beq $src1,$src2,$disp16 */
-      IADDR i_disp16;
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_beq;
-    struct { /* e.g. beqz $src2,$disp16 */
-      IADDR i_disp16;
-      SI * i_src2;
-      unsigned char in_src2;
-    } fmt_beqz;
-    struct { /* e.g. bl.s $disp8 */
-      IADDR i_disp8;
-      unsigned char out_h_gr_14;
-    } fmt_bl8;
-    struct { /* e.g. bl.l $disp24 */
-      IADDR i_disp24;
-      unsigned char out_h_gr_14;
-    } fmt_bl24;
-    struct { /* e.g. bra.s $disp8 */
-      IADDR i_disp8;
-    } fmt_bra8;
-    struct { /* e.g. bra.l $disp24 */
-      IADDR i_disp24;
-    } fmt_bra24;
-    struct { /* e.g. jl $sr */
-      SI * i_sr;
-      unsigned char in_sr;
-      unsigned char out_h_gr_14;
-    } fmt_jl;
-    struct { /* e.g. jmp $sr */
-      SI * i_sr;
-      unsigned char in_sr;
-    } fmt_jmp;
-    struct { /* e.g. rte */
-      int empty;
-    } fmt_rte;
-    struct { /* e.g. trap $uimm4 */
-      UINT f_uimm4;
-    } fmt_trap;
-    } fields;
-#if WITH_SCACHE_PBB
-    SEM_PC addr_cache;
-#endif
-  } cti;
-#if WITH_SCACHE_PBB
-  /* Writeback handler.  */
-  struct {
-    /* Pointer to argbuf entry for insn whose results need writing back.  */
-    const struct argbuf *abuf;
-  } write;
-  /* x-before handler */
-  struct {
-    /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
-    int first_p;
-  } before;
-  /* x-after handler */
-  struct {
-    int empty;
-  } after;
-  /* This entry is used to terminate each pbb.  */
-  struct {
-    /* Number of insns in pbb.  */
-    int insn_count;
-    /* Next pbb to execute.  */
-    SCACHE *next;
-  } chain;
-#endif
-};
-
-/* The ARGBUF struct.  */
-struct argbuf {
-  /* These are the baseclass definitions.  */
-  IADDR addr;
-  const IDESC *idesc;
-  char trace_p;
-  char profile_p;
-  /* cpu specific data follows */
-  union sem semantic;
-  int written;
-  union sem_fields fields;
-};
-
-/* A cached insn.
-
-   ??? SCACHE used to contain more than just argbuf.  We could delete the
-   type entirely and always just use ARGBUF, but for future concerns and as
-   a level of abstraction it is left in.  */
-
-struct scache {
-  struct argbuf argbuf;
-};
-
-/* Macros to simplify extraction, reading and semantic code.
-   These define and assign the local vars that contain the insn's fields.  */
-
-#define EXTRACT_IFMT_EMPTY_VARS \
-  /* Instruction fields.  */ \
-  unsigned int length;
-#define EXTRACT_IFMT_EMPTY_CODE \
-  length = 0; \
-
-#define EXTRACT_IFMT_ADD_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_ADD_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_ADD3_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  INT f_simm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_ADD3_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_AND3_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  UINT f_uimm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_AND3_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_OR3_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  UINT f_uimm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_OR3_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_ADDI_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  INT f_simm8; \
-  unsigned int length;
-#define EXTRACT_IFMT_ADDI_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \
-
-#define EXTRACT_IFMT_ADDV3_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  INT f_simm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_ADDV3_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_BC8_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  SI f_disp8; \
-  unsigned int length;
-#define EXTRACT_IFMT_BC8_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
-
-#define EXTRACT_IFMT_BC24_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  SI f_disp24; \
-  unsigned int length;
-#define EXTRACT_IFMT_BC24_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
-
-#define EXTRACT_IFMT_BEQ_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  SI f_disp16; \
-  unsigned int length;
-#define EXTRACT_IFMT_BEQ_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
-
-#define EXTRACT_IFMT_BEQZ_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  SI f_disp16; \
-  unsigned int length;
-#define EXTRACT_IFMT_BEQZ_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
-
-#define EXTRACT_IFMT_CMP_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_CMP_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_CMPI_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  INT f_simm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_CMPI_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_DIV_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  INT f_simm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_DIV_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_JL_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_JL_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_LD24_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_uimm24; \
-  unsigned int length;
-#define EXTRACT_IFMT_LD24_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_uimm24 = EXTRACT_UINT (insn, 32, 8, 24); \
-
-#define EXTRACT_IFMT_LDI16_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  INT f_simm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_LDI16_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_MVFACHI_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_MVFACHI_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_MVFC_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_MVFC_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_MVTACHI_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_MVTACHI_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_MVTC_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_MVTC_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_NOP_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_NOP_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_SETH_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  UINT f_hi16; \
-  unsigned int length;
-#define EXTRACT_IFMT_SETH_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_hi16 = EXTRACT_UINT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_SLLI_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_shift_op2; \
-  UINT f_uimm5; \
-  unsigned int length;
-#define EXTRACT_IFMT_SLLI_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_shift_op2 = EXTRACT_UINT (insn, 16, 8, 3); \
-  f_uimm5 = EXTRACT_UINT (insn, 16, 11, 5); \
-
-#define EXTRACT_IFMT_ST_D_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  INT f_simm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_ST_D_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_TRAP_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_uimm4; \
-  unsigned int length;
-#define EXTRACT_IFMT_TRAP_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
-  f_uimm4 = EXTRACT_UINT (insn, 16, 12, 4); \
-
-/* Collection of various things for the trace handler to use.  */
-
-typedef struct trace_record {
-  IADDR pc;
-  /* FIXME:wip */
-} TRACE_RECORD;
-
-#endif /* CPU_M32RBF_H */
diff --git a/sim/m32r/cpuall.h b/sim/m32r/cpuall.h
deleted file mode 100644
index 75ee8fa..0000000
--- a/sim/m32r/cpuall.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/* Simulator CPU header for m32r.
-
-Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
-
-This file is part of the GNU Simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#ifndef M32R_CPUALL_H
-#define M32R_CPUALL_H
-
-extern const IMP_PROPERTIES m32r_imp_properties;
-
-extern const MODEL m32r_models[];
-
-#ifndef WANT_CPU
-/* The ARGBUF struct.  */
-struct argbuf {
-  /* These are the baseclass definitions.  */
-  unsigned int length;
-  PCADDR addr;
-  const struct cgen_insn *opcode;
-  /* unsigned long insn; - no longer needed */
-  /* cpu specific data follows */
-};
-#endif
-
-#ifndef WANT_CPU
-/* A cached insn.
-   This is also used in the non-scache case.  In this situation we assume
-   the cache size is 1, and do a few things a little differently.  */
-
-struct scache {
-  IADDR next;
-  union {
-#if ! WITH_SEM_SWITCH_FULL
-    SEMANTIC_FN *sem_fn;
-#endif
-#if ! WITH_SEM_SWITCH_FAST
-#if WITH_SCACHE
-    SEMANTIC_CACHE_FN *sem_fast_fn;
-#else
-    SEMANTIC_FN *sem_fast_fn;
-#endif
-#endif
-#if WITH_SEM_SWITCH_FULL || WITH_SEM_SWITCH_FAST
-#ifdef __GNUC__
-    void *sem_case;
-#else
-    int sem_case;
-#endif
-#endif
-  } semantic;
-  struct argbuf argbuf;
-};
-#endif
-
-#endif /* M32R_CPUALL_H */
diff --git a/sim/m32r/cpux.c b/sim/m32r/cpux.c
deleted file mode 100644
index e28c072..0000000
--- a/sim/m32r/cpux.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/* Misc. support for CPU family m32rxf.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
-
-This file is part of the GNU Simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#define WANT_CPU m32rxf
-#define WANT_CPU_M32RXF
-
-#include "sim-main.h"
-
-/* Get the value of h-pc.  */
-
-USI
-m32rxf_h_pc_get (SIM_CPU *current_cpu)
-{
-  return CPU (h_pc);
-}
-
-/* Set a value for h-pc.  */
-
-void
-m32rxf_h_pc_set (SIM_CPU *current_cpu, USI newval)
-{
-  CPU (h_pc) = newval;
-}
-
-/* Get the value of h-gr.  */
-
-SI
-m32rxf_h_gr_get (SIM_CPU *current_cpu, UINT regno)
-{
-  return CPU (h_gr[regno]);
-}
-
-/* Set a value for h-gr.  */
-
-void
-m32rxf_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
-{
-  CPU (h_gr[regno]) = newval;
-}
-
-/* Get the value of h-cr.  */
-
-USI
-m32rxf_h_cr_get (SIM_CPU *current_cpu, UINT regno)
-{
-  return GET_H_CR (regno);
-}
-
-/* Set a value for h-cr.  */
-
-void
-m32rxf_h_cr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
-{
-  SET_H_CR (regno, newval);
-}
-
-/* Get the value of h-accum.  */
-
-DI
-m32rxf_h_accum_get (SIM_CPU *current_cpu)
-{
-  return GET_H_ACCUM ();
-}
-
-/* Set a value for h-accum.  */
-
-void
-m32rxf_h_accum_set (SIM_CPU *current_cpu, DI newval)
-{
-  SET_H_ACCUM (newval);
-}
-
-/* Get the value of h-accums.  */
-
-DI
-m32rxf_h_accums_get (SIM_CPU *current_cpu, UINT regno)
-{
-  return GET_H_ACCUMS (regno);
-}
-
-/* Set a value for h-accums.  */
-
-void
-m32rxf_h_accums_set (SIM_CPU *current_cpu, UINT regno, DI newval)
-{
-  SET_H_ACCUMS (regno, newval);
-}
-
-/* Get the value of h-cond.  */
-
-BI
-m32rxf_h_cond_get (SIM_CPU *current_cpu)
-{
-  return CPU (h_cond);
-}
-
-/* Set a value for h-cond.  */
-
-void
-m32rxf_h_cond_set (SIM_CPU *current_cpu, BI newval)
-{
-  CPU (h_cond) = newval;
-}
-
-/* Get the value of h-psw.  */
-
-UQI
-m32rxf_h_psw_get (SIM_CPU *current_cpu)
-{
-  return GET_H_PSW ();
-}
-
-/* Set a value for h-psw.  */
-
-void
-m32rxf_h_psw_set (SIM_CPU *current_cpu, UQI newval)
-{
-  SET_H_PSW (newval);
-}
-
-/* Get the value of h-bpsw.  */
-
-UQI
-m32rxf_h_bpsw_get (SIM_CPU *current_cpu)
-{
-  return CPU (h_bpsw);
-}
-
-/* Set a value for h-bpsw.  */
-
-void
-m32rxf_h_bpsw_set (SIM_CPU *current_cpu, UQI newval)
-{
-  CPU (h_bpsw) = newval;
-}
-
-/* Get the value of h-bbpsw.  */
-
-UQI
-m32rxf_h_bbpsw_get (SIM_CPU *current_cpu)
-{
-  return CPU (h_bbpsw);
-}
-
-/* Set a value for h-bbpsw.  */
-
-void
-m32rxf_h_bbpsw_set (SIM_CPU *current_cpu, UQI newval)
-{
-  CPU (h_bbpsw) = newval;
-}
-
-/* Get the value of h-lock.  */
-
-BI
-m32rxf_h_lock_get (SIM_CPU *current_cpu)
-{
-  return CPU (h_lock);
-}
-
-/* Set a value for h-lock.  */
-
-void
-m32rxf_h_lock_set (SIM_CPU *current_cpu, BI newval)
-{
-  CPU (h_lock) = newval;
-}
-
-/* Record trace results for INSN.  */
-
-void
-m32rxf_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,
-			    int *indices, TRACE_RECORD *tr)
-{
-}
diff --git a/sim/m32r/cpux.h b/sim/m32r/cpux.h
deleted file mode 100644
index c8894df..0000000
--- a/sim/m32r/cpux.h
+++ /dev/null
@@ -1,1219 +0,0 @@
-/* CPU family header for m32rxf.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
-
-This file is part of the GNU Simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#ifndef CPU_M32RXF_H
-#define CPU_M32RXF_H
-
-/* Maximum number of instructions that are fetched at a time.
-   This is for LIW type instructions sets (e.g. m32r).  */
-#define MAX_LIW_INSNS 2
-
-/* Maximum number of instructions that can be executed in parallel.  */
-#define MAX_PARALLEL_INSNS 2
-
-/* CPU state information.  */
-typedef struct {
-  /* Hardware elements.  */
-  struct {
-  /* program counter */
-  USI h_pc;
-#define GET_H_PC() CPU (h_pc)
-#define SET_H_PC(x) (CPU (h_pc) = (x))
-  /* general registers */
-  SI h_gr[16];
-#define GET_H_GR(a1) CPU (h_gr)[a1]
-#define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
-  /* control registers */
-  USI h_cr[16];
-/* GET_H_CR macro user-written */
-/* SET_H_CR macro user-written */
-  /* accumulator */
-  DI h_accum;
-/* GET_H_ACCUM macro user-written */
-/* SET_H_ACCUM macro user-written */
-/* start-sanitize-m32rx */
-  /* accumulators */
-  DI h_accums[2];
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
-/* GET_H_ACCUMS macro user-written */
-/* SET_H_ACCUMS macro user-written */
-/* end-sanitize-m32rx */
-  /* condition bit */
-  BI h_cond;
-#define GET_H_COND() CPU (h_cond)
-#define SET_H_COND(x) (CPU (h_cond) = (x))
-  /* psw part of psw */
-  UQI h_psw;
-/* GET_H_PSW macro user-written */
-/* SET_H_PSW macro user-written */
-  /* backup psw */
-  UQI h_bpsw;
-#define GET_H_BPSW() CPU (h_bpsw)
-#define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
-  /* backup bpsw */
-  UQI h_bbpsw;
-#define GET_H_BBPSW() CPU (h_bbpsw)
-#define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
-  /* lock */
-  BI h_lock;
-#define GET_H_LOCK() CPU (h_lock)
-#define SET_H_LOCK(x) (CPU (h_lock) = (x))
-  } hardware;
-#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
-} M32RXF_CPU_DATA;
-
-/* Cover fns for register access.  */
-USI m32rxf_h_pc_get (SIM_CPU *);
-void m32rxf_h_pc_set (SIM_CPU *, USI);
-SI m32rxf_h_gr_get (SIM_CPU *, UINT);
-void m32rxf_h_gr_set (SIM_CPU *, UINT, SI);
-USI m32rxf_h_cr_get (SIM_CPU *, UINT);
-void m32rxf_h_cr_set (SIM_CPU *, UINT, USI);
-DI m32rxf_h_accum_get (SIM_CPU *);
-void m32rxf_h_accum_set (SIM_CPU *, DI);
-DI m32rxf_h_accums_get (SIM_CPU *, UINT);
-void m32rxf_h_accums_set (SIM_CPU *, UINT, DI);
-BI m32rxf_h_cond_get (SIM_CPU *);
-void m32rxf_h_cond_set (SIM_CPU *, BI);
-UQI m32rxf_h_psw_get (SIM_CPU *);
-void m32rxf_h_psw_set (SIM_CPU *, UQI);
-UQI m32rxf_h_bpsw_get (SIM_CPU *);
-void m32rxf_h_bpsw_set (SIM_CPU *, UQI);
-UQI m32rxf_h_bbpsw_get (SIM_CPU *);
-void m32rxf_h_bbpsw_set (SIM_CPU *, UQI);
-BI m32rxf_h_lock_get (SIM_CPU *);
-void m32rxf_h_lock_set (SIM_CPU *, BI);
-
-/* These must be hand-written.  */
-extern CPUREG_FETCH_FN m32rxf_fetch_register;
-extern CPUREG_STORE_FN m32rxf_store_register;
-
-typedef struct {
-  int empty;
-} MODEL_M32RX_DATA;
-
-union sem_fields {
-    struct { /* empty sformat for unspecified field list */
-      int empty;
-    } fmt_empty;
-    struct { /* e.g. add $dr,$sr */
-      SI * i_dr;
-      SI * i_sr;
-      unsigned char in_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_add;
-    struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
-      INT f_simm16;
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_add3;
-    struct { /* e.g. and3 $dr,$sr,$uimm16 */
-      UINT f_uimm16;
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_and3;
-    struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
-      UINT f_uimm16;
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_or3;
-    struct { /* e.g. addi $dr,$simm8 */
-      INT f_simm8;
-      SI * i_dr;
-      unsigned char in_dr;
-      unsigned char out_dr;
-    } fmt_addi;
-    struct { /* e.g. addv $dr,$sr */
-      SI * i_dr;
-      SI * i_sr;
-      unsigned char in_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_addv;
-    struct { /* e.g. addv3 $dr,$sr,$simm16 */
-      INT f_simm16;
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_addv3;
-    struct { /* e.g. addx $dr,$sr */
-      SI * i_dr;
-      SI * i_sr;
-      unsigned char in_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_addx;
-    struct { /* e.g. cmp $src1,$src2 */
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_cmp;
-    struct { /* e.g. cmpi $src2,$simm16 */
-      INT f_simm16;
-      SI * i_src2;
-      unsigned char in_src2;
-    } fmt_cmpi;
-    struct { /* e.g. cmpz $src2 */
-      SI * i_src2;
-      unsigned char in_src2;
-    } fmt_cmpz;
-    struct { /* e.g. div $dr,$sr */
-      SI * i_dr;
-      SI * i_sr;
-      unsigned char in_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_div;
-    struct { /* e.g. ld $dr,@$sr */
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_ld;
-    struct { /* e.g. ld $dr,@($slo16,$sr) */
-      INT f_simm16;
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_ld_d;
-    struct { /* e.g. ldb $dr,@$sr */
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_ldb;
-    struct { /* e.g. ldb $dr,@($slo16,$sr) */
-      INT f_simm16;
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_ldb_d;
-    struct { /* e.g. ldh $dr,@$sr */
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_ldh;
-    struct { /* e.g. ldh $dr,@($slo16,$sr) */
-      INT f_simm16;
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_ldh_d;
-    struct { /* e.g. ld $dr,@$sr+ */
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-      unsigned char out_sr;
-    } fmt_ld_plus;
-    struct { /* e.g. ld24 $dr,$uimm24 */
-      ADDR i_uimm24;
-      SI * i_dr;
-      unsigned char out_dr;
-    } fmt_ld24;
-    struct { /* e.g. ldi8 $dr,$simm8 */
-      INT f_simm8;
-      SI * i_dr;
-      unsigned char out_dr;
-    } fmt_ldi8;
-    struct { /* e.g. ldi16 $dr,$hash$slo16 */
-      INT f_simm16;
-      SI * i_dr;
-      unsigned char out_dr;
-    } fmt_ldi16;
-    struct { /* e.g. lock $dr,@$sr */
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_lock;
-    struct { /* e.g. machi $src1,$src2,$acc */
-      UINT f_acc;
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_machi_a;
-    struct { /* e.g. mulhi $src1,$src2,$acc */
-      UINT f_acc;
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_mulhi_a;
-    struct { /* e.g. mv $dr,$sr */
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_mv;
-    struct { /* e.g. mvfachi $dr,$accs */
-      UINT f_accs;
-      SI * i_dr;
-      unsigned char out_dr;
-    } fmt_mvfachi_a;
-    struct { /* e.g. mvfc $dr,$scr */
-      UINT f_r2;
-      SI * i_dr;
-      unsigned char out_dr;
-    } fmt_mvfc;
-    struct { /* e.g. mvtachi $src1,$accs */
-      UINT f_accs;
-      SI * i_src1;
-      unsigned char in_src1;
-    } fmt_mvtachi_a;
-    struct { /* e.g. mvtc $sr,$dcr */
-      UINT f_r1;
-      SI * i_sr;
-      unsigned char in_sr;
-    } fmt_mvtc;
-    struct { /* e.g. nop */
-      int empty;
-    } fmt_nop;
-    struct { /* e.g. rac $accd,$accs,$imm1 */
-      UINT f_accs;
-      SI f_imm1;
-      UINT f_accd;
-    } fmt_rac_dsi;
-    struct { /* e.g. seth $dr,$hash$hi16 */
-      UINT f_hi16;
-      SI * i_dr;
-      unsigned char out_dr;
-    } fmt_seth;
-    struct { /* e.g. sll3 $dr,$sr,$simm16 */
-      INT f_simm16;
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_sll3;
-    struct { /* e.g. slli $dr,$uimm5 */
-      UINT f_uimm5;
-      SI * i_dr;
-      unsigned char in_dr;
-      unsigned char out_dr;
-    } fmt_slli;
-    struct { /* e.g. st $src1,@$src2 */
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_st;
-    struct { /* e.g. st $src1,@($slo16,$src2) */
-      INT f_simm16;
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_st_d;
-    struct { /* e.g. stb $src1,@$src2 */
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_stb;
-    struct { /* e.g. stb $src1,@($slo16,$src2) */
-      INT f_simm16;
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_stb_d;
-    struct { /* e.g. sth $src1,@$src2 */
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_sth;
-    struct { /* e.g. sth $src1,@($slo16,$src2) */
-      INT f_simm16;
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_sth_d;
-    struct { /* e.g. st $src1,@+$src2 */
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-      unsigned char out_src2;
-    } fmt_st_plus;
-    struct { /* e.g. unlock $src1,@$src2 */
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_unlock;
-    struct { /* e.g. satb $dr,$sr */
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_satb;
-    struct { /* e.g. sat $dr,$sr */
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_sat;
-    struct { /* e.g. sadd */
-      int empty;
-    } fmt_sadd;
-    struct { /* e.g. macwu1 $src1,$src2 */
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_macwu1;
-    struct { /* e.g. msblo $src1,$src2 */
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_msblo;
-    struct { /* e.g. mulwu1 $src1,$src2 */
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_mulwu1;
-  /* cti insns, kept separately so addr_cache is in fixed place */
-  struct {
-    union {
-    struct { /* e.g. bc.s $disp8 */
-      IADDR i_disp8;
-    } fmt_bc8;
-    struct { /* e.g. bc.l $disp24 */
-      IADDR i_disp24;
-    } fmt_bc24;
-    struct { /* e.g. beq $src1,$src2,$disp16 */
-      IADDR i_disp16;
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_beq;
-    struct { /* e.g. beqz $src2,$disp16 */
-      IADDR i_disp16;
-      SI * i_src2;
-      unsigned char in_src2;
-    } fmt_beqz;
-    struct { /* e.g. bl.s $disp8 */
-      IADDR i_disp8;
-      unsigned char out_h_gr_14;
-    } fmt_bl8;
-    struct { /* e.g. bl.l $disp24 */
-      IADDR i_disp24;
-      unsigned char out_h_gr_14;
-    } fmt_bl24;
-    struct { /* e.g. bcl.s $disp8 */
-      IADDR i_disp8;
-      unsigned char out_h_gr_14;
-    } fmt_bcl8;
-    struct { /* e.g. bcl.l $disp24 */
-      IADDR i_disp24;
-      unsigned char out_h_gr_14;
-    } fmt_bcl24;
-    struct { /* e.g. bra.s $disp8 */
-      IADDR i_disp8;
-    } fmt_bra8;
-    struct { /* e.g. bra.l $disp24 */
-      IADDR i_disp24;
-    } fmt_bra24;
-    struct { /* e.g. jc $sr */
-      SI * i_sr;
-      unsigned char in_sr;
-    } fmt_jc;
-    struct { /* e.g. jl $sr */
-      SI * i_sr;
-      unsigned char in_sr;
-      unsigned char out_h_gr_14;
-    } fmt_jl;
-    struct { /* e.g. jmp $sr */
-      SI * i_sr;
-      unsigned char in_sr;
-    } fmt_jmp;
-    struct { /* e.g. rte */
-      int empty;
-    } fmt_rte;
-    struct { /* e.g. trap $uimm4 */
-      UINT f_uimm4;
-    } fmt_trap;
-    struct { /* e.g. sc */
-      int empty;
-    } fmt_sc;
-    } fields;
-#if WITH_SCACHE_PBB
-    SEM_PC addr_cache;
-#endif
-  } cti;
-#if WITH_SCACHE_PBB
-  /* Writeback handler.  */
-  struct {
-    /* Pointer to argbuf entry for insn whose results need writing back.  */
-    const struct argbuf *abuf;
-  } write;
-  /* x-before handler */
-  struct {
-    /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
-    int first_p;
-  } before;
-  /* x-after handler */
-  struct {
-    int empty;
-  } after;
-  /* This entry is used to terminate each pbb.  */
-  struct {
-    /* Number of insns in pbb.  */
-    int insn_count;
-    /* Next pbb to execute.  */
-    SCACHE *next;
-  } chain;
-#endif
-};
-
-/* The ARGBUF struct.  */
-struct argbuf {
-  /* These are the baseclass definitions.  */
-  IADDR addr;
-  const IDESC *idesc;
-  char trace_p;
-  char profile_p;
-  /* cpu specific data follows */
-  union sem semantic;
-  int written;
-  union sem_fields fields;
-};
-
-/* A cached insn.
-
-   ??? SCACHE used to contain more than just argbuf.  We could delete the
-   type entirely and always just use ARGBUF, but for future concerns and as
-   a level of abstraction it is left in.  */
-
-struct scache {
-  struct argbuf argbuf;
-};
-
-/* Macros to simplify extraction, reading and semantic code.
-   These define and assign the local vars that contain the insn's fields.  */
-
-#define EXTRACT_IFMT_EMPTY_VARS \
-  /* Instruction fields.  */ \
-  unsigned int length;
-#define EXTRACT_IFMT_EMPTY_CODE \
-  length = 0; \
-
-#define EXTRACT_IFMT_ADD_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_ADD_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_ADD3_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  INT f_simm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_ADD3_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_AND3_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  UINT f_uimm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_AND3_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_OR3_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  UINT f_uimm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_OR3_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_ADDI_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  INT f_simm8; \
-  unsigned int length;
-#define EXTRACT_IFMT_ADDI_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \
-
-#define EXTRACT_IFMT_ADDV3_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  INT f_simm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_ADDV3_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_BC8_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  SI f_disp8; \
-  unsigned int length;
-#define EXTRACT_IFMT_BC8_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
-
-#define EXTRACT_IFMT_BC24_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  SI f_disp24; \
-  unsigned int length;
-#define EXTRACT_IFMT_BC24_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
-
-#define EXTRACT_IFMT_BEQ_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  SI f_disp16; \
-  unsigned int length;
-#define EXTRACT_IFMT_BEQ_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
-
-#define EXTRACT_IFMT_BEQZ_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  SI f_disp16; \
-  unsigned int length;
-#define EXTRACT_IFMT_BEQZ_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
-
-#define EXTRACT_IFMT_CMP_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_CMP_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_CMPI_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  INT f_simm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_CMPI_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_CMPZ_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_CMPZ_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_DIV_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  INT f_simm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_DIV_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_JC_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_JC_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_LD24_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_uimm24; \
-  unsigned int length;
-#define EXTRACT_IFMT_LD24_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_uimm24 = EXTRACT_UINT (insn, 32, 8, 24); \
-
-#define EXTRACT_IFMT_LDI16_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  INT f_simm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_LDI16_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_MACHI_A_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_acc; \
-  UINT f_op23; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_MACHI_A_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_acc = EXTRACT_UINT (insn, 16, 8, 1); \
-  f_op23 = EXTRACT_UINT (insn, 16, 9, 3); \
-  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_MVFACHI_A_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_accs; \
-  UINT f_op3; \
-  unsigned int length;
-#define EXTRACT_IFMT_MVFACHI_A_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
-  f_accs = EXTRACT_UINT (insn, 16, 12, 2); \
-  f_op3 = EXTRACT_UINT (insn, 16, 14, 2); \
-
-#define EXTRACT_IFMT_MVFC_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_MVFC_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_MVTACHI_A_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_accs; \
-  UINT f_op3; \
-  unsigned int length;
-#define EXTRACT_IFMT_MVTACHI_A_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
-  f_accs = EXTRACT_UINT (insn, 16, 12, 2); \
-  f_op3 = EXTRACT_UINT (insn, 16, 14, 2); \
-
-#define EXTRACT_IFMT_MVTC_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_MVTC_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_NOP_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_NOP_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_RAC_DSI_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_accd; \
-  UINT f_bits67; \
-  UINT f_op2; \
-  UINT f_accs; \
-  UINT f_bit14; \
-  SI f_imm1; \
-  unsigned int length;
-#define EXTRACT_IFMT_RAC_DSI_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_accd = EXTRACT_UINT (insn, 16, 4, 2); \
-  f_bits67 = EXTRACT_UINT (insn, 16, 6, 2); \
-  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
-  f_accs = EXTRACT_UINT (insn, 16, 12, 2); \
-  f_bit14 = EXTRACT_UINT (insn, 16, 14, 1); \
-  f_imm1 = ((EXTRACT_UINT (insn, 16, 15, 1)) + (1)); \
-
-#define EXTRACT_IFMT_SETH_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  UINT f_hi16; \
-  unsigned int length;
-#define EXTRACT_IFMT_SETH_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_hi16 = EXTRACT_UINT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_SLLI_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_shift_op2; \
-  UINT f_uimm5; \
-  unsigned int length;
-#define EXTRACT_IFMT_SLLI_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_shift_op2 = EXTRACT_UINT (insn, 16, 8, 3); \
-  f_uimm5 = EXTRACT_UINT (insn, 16, 11, 5); \
-
-#define EXTRACT_IFMT_ST_D_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  INT f_simm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_ST_D_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_TRAP_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_uimm4; \
-  unsigned int length;
-#define EXTRACT_IFMT_TRAP_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
-  f_uimm4 = EXTRACT_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_SATB_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  UINT f_uimm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_SATB_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
-
-/* Queued output values of an instruction.  */
-
-struct parexec {
-  union {
-    struct { /* empty sformat for unspecified field list */
-      int empty;
-    } fmt_empty;
-    struct { /* e.g. add $dr,$sr */
-      SI dr;
-    } fmt_add;
-    struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
-      SI dr;
-    } fmt_add3;
-    struct { /* e.g. and3 $dr,$sr,$uimm16 */
-      SI dr;
-    } fmt_and3;
-    struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
-      SI dr;
-    } fmt_or3;
-    struct { /* e.g. addi $dr,$simm8 */
-      SI dr;
-    } fmt_addi;
-    struct { /* e.g. addv $dr,$sr */
-      BI condbit;
-      SI dr;
-    } fmt_addv;
-    struct { /* e.g. addv3 $dr,$sr,$simm16 */
-      BI condbit;
-      SI dr;
-    } fmt_addv3;
-    struct { /* e.g. addx $dr,$sr */
-      BI condbit;
-      SI dr;
-    } fmt_addx;
-    struct { /* e.g. bc.s $disp8 */
-      USI pc;
-    } fmt_bc8;
-    struct { /* e.g. bc.l $disp24 */
-      USI pc;
-    } fmt_bc24;
-    struct { /* e.g. beq $src1,$src2,$disp16 */
-      USI pc;
-    } fmt_beq;
-    struct { /* e.g. beqz $src2,$disp16 */
-      USI pc;
-    } fmt_beqz;
-    struct { /* e.g. bl.s $disp8 */
-      SI h_gr_14;
-      USI pc;
-    } fmt_bl8;
-    struct { /* e.g. bl.l $disp24 */
-      SI h_gr_14;
-      USI pc;
-    } fmt_bl24;
-    struct { /* e.g. bcl.s $disp8 */
-      SI h_gr_14;
-      USI pc;
-    } fmt_bcl8;
-    struct { /* e.g. bcl.l $disp24 */
-      SI h_gr_14;
-      USI pc;
-    } fmt_bcl24;
-    struct { /* e.g. bra.s $disp8 */
-      USI pc;
-    } fmt_bra8;
-    struct { /* e.g. bra.l $disp24 */
-      USI pc;
-    } fmt_bra24;
-    struct { /* e.g. cmp $src1,$src2 */
-      BI condbit;
-    } fmt_cmp;
-    struct { /* e.g. cmpi $src2,$simm16 */
-      BI condbit;
-    } fmt_cmpi;
-    struct { /* e.g. cmpz $src2 */
-      BI condbit;
-    } fmt_cmpz;
-    struct { /* e.g. div $dr,$sr */
-      SI dr;
-    } fmt_div;
-    struct { /* e.g. jc $sr */
-      USI pc;
-    } fmt_jc;
-    struct { /* e.g. jl $sr */
-      SI h_gr_14;
-      USI pc;
-    } fmt_jl;
-    struct { /* e.g. jmp $sr */
-      USI pc;
-    } fmt_jmp;
-    struct { /* e.g. ld $dr,@$sr */
-      SI dr;
-    } fmt_ld;
-    struct { /* e.g. ld $dr,@($slo16,$sr) */
-      SI dr;
-    } fmt_ld_d;
-    struct { /* e.g. ldb $dr,@$sr */
-      SI dr;
-    } fmt_ldb;
-    struct { /* e.g. ldb $dr,@($slo16,$sr) */
-      SI dr;
-    } fmt_ldb_d;
-    struct { /* e.g. ldh $dr,@$sr */
-      SI dr;
-    } fmt_ldh;
-    struct { /* e.g. ldh $dr,@($slo16,$sr) */
-      SI dr;
-    } fmt_ldh_d;
-    struct { /* e.g. ld $dr,@$sr+ */
-      SI dr;
-      SI sr;
-    } fmt_ld_plus;
-    struct { /* e.g. ld24 $dr,$uimm24 */
-      SI dr;
-    } fmt_ld24;
-    struct { /* e.g. ldi8 $dr,$simm8 */
-      SI dr;
-    } fmt_ldi8;
-    struct { /* e.g. ldi16 $dr,$hash$slo16 */
-      SI dr;
-    } fmt_ldi16;
-    struct { /* e.g. lock $dr,@$sr */
-      SI dr;
-      BI h_lock_0;
-    } fmt_lock;
-    struct { /* e.g. machi $src1,$src2,$acc */
-      DI acc;
-    } fmt_machi_a;
-    struct { /* e.g. mulhi $src1,$src2,$acc */
-      DI acc;
-    } fmt_mulhi_a;
-    struct { /* e.g. mv $dr,$sr */
-      SI dr;
-    } fmt_mv;
-    struct { /* e.g. mvfachi $dr,$accs */
-      SI dr;
-    } fmt_mvfachi_a;
-    struct { /* e.g. mvfc $dr,$scr */
-      SI dr;
-    } fmt_mvfc;
-    struct { /* e.g. mvtachi $src1,$accs */
-      DI accs;
-    } fmt_mvtachi_a;
-    struct { /* e.g. mvtc $sr,$dcr */
-      USI dcr;
-    } fmt_mvtc;
-    struct { /* e.g. nop */
-      int empty;
-    } fmt_nop;
-    struct { /* e.g. rac $accd,$accs,$imm1 */
-      DI accd;
-    } fmt_rac_dsi;
-    struct { /* e.g. rte */
-      UQI h_bpsw_0;
-      USI h_cr_6;
-      UQI h_psw_0;
-      USI pc;
-    } fmt_rte;
-    struct { /* e.g. seth $dr,$hash$hi16 */
-      SI dr;
-    } fmt_seth;
-    struct { /* e.g. sll3 $dr,$sr,$simm16 */
-      SI dr;
-    } fmt_sll3;
-    struct { /* e.g. slli $dr,$uimm5 */
-      SI dr;
-    } fmt_slli;
-    struct { /* e.g. st $src1,@$src2 */
-      SI h_memory_src2;
-      USI h_memory_src2_idx;
-    } fmt_st;
-    struct { /* e.g. st $src1,@($slo16,$src2) */
-      SI h_memory_add__VM_src2_slo16;
-      USI h_memory_add__VM_src2_slo16_idx;
-    } fmt_st_d;
-    struct { /* e.g. stb $src1,@$src2 */
-      QI h_memory_src2;
-      USI h_memory_src2_idx;
-    } fmt_stb;
-    struct { /* e.g. stb $src1,@($slo16,$src2) */
-      QI h_memory_add__VM_src2_slo16;
-      USI h_memory_add__VM_src2_slo16_idx;
-    } fmt_stb_d;
-    struct { /* e.g. sth $src1,@$src2 */
-      HI h_memory_src2;
-      USI h_memory_src2_idx;
-    } fmt_sth;
-    struct { /* e.g. sth $src1,@($slo16,$src2) */
-      HI h_memory_add__VM_src2_slo16;
-      USI h_memory_add__VM_src2_slo16_idx;
-    } fmt_sth_d;
-    struct { /* e.g. st $src1,@+$src2 */
-      SI h_memory_new_src2;
-      USI h_memory_new_src2_idx;
-      SI src2;
-    } fmt_st_plus;
-    struct { /* e.g. trap $uimm4 */
-      UQI h_bbpsw_0;
-      UQI h_bpsw_0;
-      USI h_cr_14;
-      USI h_cr_6;
-      UQI h_psw_0;
-      SI pc;
-    } fmt_trap;
-    struct { /* e.g. unlock $src1,@$src2 */
-      BI h_lock_0;
-      SI h_memory_src2;
-      USI h_memory_src2_idx;
-    } fmt_unlock;
-    struct { /* e.g. satb $dr,$sr */
-      SI dr;
-    } fmt_satb;
-    struct { /* e.g. sat $dr,$sr */
-      SI dr;
-    } fmt_sat;
-    struct { /* e.g. sadd */
-      DI h_accums_0;
-    } fmt_sadd;
-    struct { /* e.g. macwu1 $src1,$src2 */
-      DI h_accums_1;
-    } fmt_macwu1;
-    struct { /* e.g. msblo $src1,$src2 */
-      DI accum;
-    } fmt_msblo;
-    struct { /* e.g. mulwu1 $src1,$src2 */
-      DI h_accums_1;
-    } fmt_mulwu1;
-    struct { /* e.g. sc */
-      int empty;
-    } fmt_sc;
-  } operands;
-  /* For conditionally written operands, bitmask of which ones were.  */
-  int written;
-};
-
-/* Collection of various things for the trace handler to use.  */
-
-typedef struct trace_record {
-  IADDR pc;
-  /* FIXME:wip */
-} TRACE_RECORD;
-
-#endif /* CPU_M32RXF_H */
diff --git a/sim/m32r/decode.c b/sim/m32r/decode.c
deleted file mode 100644
index 3bcb057..0000000
--- a/sim/m32r/decode.c
+++ /dev/null
@@ -1,2015 +0,0 @@
-/* Simulator instruction decoder for m32rbf.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
-
-This file is part of the GNU Simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#define WANT_CPU m32rbf
-#define WANT_CPU_M32RBF
-
-#include "sim-main.h"
-#include "sim-assert.h"
-
-/* FIXME: Need to review choices for the following.  */
-
-#if WITH_SEM_SWITCH_FULL
-#define FULL(fn)
-#else
-#define FULL(fn) CONCAT3 (m32rbf,_sem_,fn) ,
-#endif
-
-#if WITH_FAST
-#if WITH_SEM_SWITCH_FAST
-#define FAST(fn)
-#else
-#define FAST(fn) CONCAT3 (m32rbf,_semf_,fn) , /* f for fast */
-#endif
-#else
-#define FAST(fn)
-#endif
-
-/* The instruction descriptor array.
-   This is computed at runtime.  Space for it is not malloc'd to save a
-   teensy bit of cpu in the decoder.  Moving it to malloc space is trivial
-   but won't be done until necessary (we don't currently support the runtime
-   addition of instructions nor an SMP machine with different cpus).  */
-static IDESC m32rbf_insn_data[M32RBF_INSN_MAX];
-
-/* Instruction semantic handlers and support.
-   This struct defines the part of an IDESC that can be computed at
-   compile time.  */
-
-struct insn_sem {
-  /* The instruction type (a number that identifies each insn over the
-     entire architecture).  */
-  CGEN_INSN_TYPE type;
-
-  /* Index in IDESC table.  */
-  int index;
-
-  /* Routines to execute the insn.
-     The full version has all features (profiling,tracing) compiled in.
-     The fast version has none of that.  */
-#if ! WITH_SEM_SWITCH_FULL
-  SEMANTIC_FN *sem_full;
-#endif
-#if WITH_FAST && ! WITH_SEM_SWITCH_FAST
-  SEMANTIC_FN *sem_fast;
-#endif
-
-};
-/* The INSN_ prefix is not here and is instead part of the `insn' argument
-   to avoid collisions with header files (e.g. `AND' in ansidecl.h).  */
-#define IDX(insn) CONCAT2 (M32RBF_,insn)
-#define TYPE(insn) CONCAT2 (M32R_,insn)
-
-/* Commas between elements are contained in the macros.
-   Some of these are conditionally compiled out.  */
-
-static const struct insn_sem m32rbf_insn_sem[] =
-{
-  { VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), FULL (x_invalid) FAST (x_invalid) },
-  { VIRTUAL_INSN_X_AFTER, IDX (INSN_X_AFTER), FULL (x_after) FAST (x_after) },
-  { VIRTUAL_INSN_X_BEFORE, IDX (INSN_X_BEFORE), FULL (x_before) FAST (x_before) },
-  { VIRTUAL_INSN_X_CTI_CHAIN, IDX (INSN_X_CTI_CHAIN), FULL (x_cti_chain) FAST (x_cti_chain) },
-  { VIRTUAL_INSN_X_CHAIN, IDX (INSN_X_CHAIN), FULL (x_chain) FAST (x_chain) },
-  { VIRTUAL_INSN_X_BEGIN, IDX (INSN_X_BEGIN), FULL (x_begin) FAST (x_begin) },
-  { TYPE (INSN_ADD), IDX (INSN_ADD), FULL (add) FAST (add) },
-  { TYPE (INSN_ADD3), IDX (INSN_ADD3), FULL (add3) FAST (add3) },
-  { TYPE (INSN_AND), IDX (INSN_AND), FULL (and) FAST (and) },
-  { TYPE (INSN_AND3), IDX (INSN_AND3), FULL (and3) FAST (and3) },
-  { TYPE (INSN_OR), IDX (INSN_OR), FULL (or) FAST (or) },
-  { TYPE (INSN_OR3), IDX (INSN_OR3), FULL (or3) FAST (or3) },
-  { TYPE (INSN_XOR), IDX (INSN_XOR), FULL (xor) FAST (xor) },
-  { TYPE (INSN_XOR3), IDX (INSN_XOR3), FULL (xor3) FAST (xor3) },
-  { TYPE (INSN_ADDI), IDX (INSN_ADDI), FULL (addi) FAST (addi) },
-  { TYPE (INSN_ADDV), IDX (INSN_ADDV), FULL (addv) FAST (addv) },
-  { TYPE (INSN_ADDV3), IDX (INSN_ADDV3), FULL (addv3) FAST (addv3) },
-  { TYPE (INSN_ADDX), IDX (INSN_ADDX), FULL (addx) FAST (addx) },
-  { TYPE (INSN_BC8), IDX (INSN_BC8), FULL (bc8) FAST (bc8) },
-  { TYPE (INSN_BC24), IDX (INSN_BC24), FULL (bc24) FAST (bc24) },
-  { TYPE (INSN_BEQ), IDX (INSN_BEQ), FULL (beq) FAST (beq) },
-  { TYPE (INSN_BEQZ), IDX (INSN_BEQZ), FULL (beqz) FAST (beqz) },
-  { TYPE (INSN_BGEZ), IDX (INSN_BGEZ), FULL (bgez) FAST (bgez) },
-  { TYPE (INSN_BGTZ), IDX (INSN_BGTZ), FULL (bgtz) FAST (bgtz) },
-  { TYPE (INSN_BLEZ), IDX (INSN_BLEZ), FULL (blez) FAST (blez) },
-  { TYPE (INSN_BLTZ), IDX (INSN_BLTZ), FULL (bltz) FAST (bltz) },
-  { TYPE (INSN_BNEZ), IDX (INSN_BNEZ), FULL (bnez) FAST (bnez) },
-  { TYPE (INSN_BL8), IDX (INSN_BL8), FULL (bl8) FAST (bl8) },
-  { TYPE (INSN_BL24), IDX (INSN_BL24), FULL (bl24) FAST (bl24) },
-  { TYPE (INSN_BNC8), IDX (INSN_BNC8), FULL (bnc8) FAST (bnc8) },
-  { TYPE (INSN_BNC24), IDX (INSN_BNC24), FULL (bnc24) FAST (bnc24) },
-  { TYPE (INSN_BNE), IDX (INSN_BNE), FULL (bne) FAST (bne) },
-  { TYPE (INSN_BRA8), IDX (INSN_BRA8), FULL (bra8) FAST (bra8) },
-  { TYPE (INSN_BRA24), IDX (INSN_BRA24), FULL (bra24) FAST (bra24) },
-  { TYPE (INSN_CMP), IDX (INSN_CMP), FULL (cmp) FAST (cmp) },
-  { TYPE (INSN_CMPI), IDX (INSN_CMPI), FULL (cmpi) FAST (cmpi) },
-  { TYPE (INSN_CMPU), IDX (INSN_CMPU), FULL (cmpu) FAST (cmpu) },
-  { TYPE (INSN_CMPUI), IDX (INSN_CMPUI), FULL (cmpui) FAST (cmpui) },
-  { TYPE (INSN_DIV), IDX (INSN_DIV), FULL (div) FAST (div) },
-  { TYPE (INSN_DIVU), IDX (INSN_DIVU), FULL (divu) FAST (divu) },
-  { TYPE (INSN_REM), IDX (INSN_REM), FULL (rem) FAST (rem) },
-  { TYPE (INSN_REMU), IDX (INSN_REMU), FULL (remu) FAST (remu) },
-  { TYPE (INSN_JL), IDX (INSN_JL), FULL (jl) FAST (jl) },
-  { TYPE (INSN_JMP), IDX (INSN_JMP), FULL (jmp) FAST (jmp) },
-  { TYPE (INSN_LD), IDX (INSN_LD), FULL (ld) FAST (ld) },
-  { TYPE (INSN_LD_D), IDX (INSN_LD_D), FULL (ld_d) FAST (ld_d) },
-  { TYPE (INSN_LDB), IDX (INSN_LDB), FULL (ldb) FAST (ldb) },
-  { TYPE (INSN_LDB_D), IDX (INSN_LDB_D), FULL (ldb_d) FAST (ldb_d) },
-  { TYPE (INSN_LDH), IDX (INSN_LDH), FULL (ldh) FAST (ldh) },
-  { TYPE (INSN_LDH_D), IDX (INSN_LDH_D), FULL (ldh_d) FAST (ldh_d) },
-  { TYPE (INSN_LDUB), IDX (INSN_LDUB), FULL (ldub) FAST (ldub) },
-  { TYPE (INSN_LDUB_D), IDX (INSN_LDUB_D), FULL (ldub_d) FAST (ldub_d) },
-  { TYPE (INSN_LDUH), IDX (INSN_LDUH), FULL (lduh) FAST (lduh) },
-  { TYPE (INSN_LDUH_D), IDX (INSN_LDUH_D), FULL (lduh_d) FAST (lduh_d) },
-  { TYPE (INSN_LD_PLUS), IDX (INSN_LD_PLUS), FULL (ld_plus) FAST (ld_plus) },
-  { TYPE (INSN_LD24), IDX (INSN_LD24), FULL (ld24) FAST (ld24) },
-  { TYPE (INSN_LDI8), IDX (INSN_LDI8), FULL (ldi8) FAST (ldi8) },
-  { TYPE (INSN_LDI16), IDX (INSN_LDI16), FULL (ldi16) FAST (ldi16) },
-  { TYPE (INSN_LOCK), IDX (INSN_LOCK), FULL (lock) FAST (lock) },
-  { TYPE (INSN_MACHI), IDX (INSN_MACHI), FULL (machi) FAST (machi) },
-  { TYPE (INSN_MACLO), IDX (INSN_MACLO), FULL (maclo) FAST (maclo) },
-  { TYPE (INSN_MACWHI), IDX (INSN_MACWHI), FULL (macwhi) FAST (macwhi) },
-  { TYPE (INSN_MACWLO), IDX (INSN_MACWLO), FULL (macwlo) FAST (macwlo) },
-  { TYPE (INSN_MUL), IDX (INSN_MUL), FULL (mul) FAST (mul) },
-  { TYPE (INSN_MULHI), IDX (INSN_MULHI), FULL (mulhi) FAST (mulhi) },
-  { TYPE (INSN_MULLO), IDX (INSN_MULLO), FULL (mullo) FAST (mullo) },
-  { TYPE (INSN_MULWHI), IDX (INSN_MULWHI), FULL (mulwhi) FAST (mulwhi) },
-  { TYPE (INSN_MULWLO), IDX (INSN_MULWLO), FULL (mulwlo) FAST (mulwlo) },
-  { TYPE (INSN_MV), IDX (INSN_MV), FULL (mv) FAST (mv) },
-  { TYPE (INSN_MVFACHI), IDX (INSN_MVFACHI), FULL (mvfachi) FAST (mvfachi) },
-  { TYPE (INSN_MVFACLO), IDX (INSN_MVFACLO), FULL (mvfaclo) FAST (mvfaclo) },
-  { TYPE (INSN_MVFACMI), IDX (INSN_MVFACMI), FULL (mvfacmi) FAST (mvfacmi) },
-  { TYPE (INSN_MVFC), IDX (INSN_MVFC), FULL (mvfc) FAST (mvfc) },
-  { TYPE (INSN_MVTACHI), IDX (INSN_MVTACHI), FULL (mvtachi) FAST (mvtachi) },
-  { TYPE (INSN_MVTACLO), IDX (INSN_MVTACLO), FULL (mvtaclo) FAST (mvtaclo) },
-  { TYPE (INSN_MVTC), IDX (INSN_MVTC), FULL (mvtc) FAST (mvtc) },
-  { TYPE (INSN_NEG), IDX (INSN_NEG), FULL (neg) FAST (neg) },
-  { TYPE (INSN_NOP), IDX (INSN_NOP), FULL (nop) FAST (nop) },
-  { TYPE (INSN_NOT), IDX (INSN_NOT), FULL (not) FAST (not) },
-  { TYPE (INSN_RAC), IDX (INSN_RAC), FULL (rac) FAST (rac) },
-  { TYPE (INSN_RACH), IDX (INSN_RACH), FULL (rach) FAST (rach) },
-  { TYPE (INSN_RTE), IDX (INSN_RTE), FULL (rte) FAST (rte) },
-  { TYPE (INSN_SETH), IDX (INSN_SETH), FULL (seth) FAST (seth) },
-  { TYPE (INSN_SLL), IDX (INSN_SLL), FULL (sll) FAST (sll) },
-  { TYPE (INSN_SLL3), IDX (INSN_SLL3), FULL (sll3) FAST (sll3) },
-  { TYPE (INSN_SLLI), IDX (INSN_SLLI), FULL (slli) FAST (slli) },
-  { TYPE (INSN_SRA), IDX (INSN_SRA), FULL (sra) FAST (sra) },
-  { TYPE (INSN_SRA3), IDX (INSN_SRA3), FULL (sra3) FAST (sra3) },
-  { TYPE (INSN_SRAI), IDX (INSN_SRAI), FULL (srai) FAST (srai) },
-  { TYPE (INSN_SRL), IDX (INSN_SRL), FULL (srl) FAST (srl) },
-  { TYPE (INSN_SRL3), IDX (INSN_SRL3), FULL (srl3) FAST (srl3) },
-  { TYPE (INSN_SRLI), IDX (INSN_SRLI), FULL (srli) FAST (srli) },
-  { TYPE (INSN_ST), IDX (INSN_ST), FULL (st) FAST (st) },
-  { TYPE (INSN_ST_D), IDX (INSN_ST_D), FULL (st_d) FAST (st_d) },
-  { TYPE (INSN_STB), IDX (INSN_STB), FULL (stb) FAST (stb) },
-  { TYPE (INSN_STB_D), IDX (INSN_STB_D), FULL (stb_d) FAST (stb_d) },
-  { TYPE (INSN_STH), IDX (INSN_STH), FULL (sth) FAST (sth) },
-  { TYPE (INSN_STH_D), IDX (INSN_STH_D), FULL (sth_d) FAST (sth_d) },
-  { TYPE (INSN_ST_PLUS), IDX (INSN_ST_PLUS), FULL (st_plus) FAST (st_plus) },
-  { TYPE (INSN_ST_MINUS), IDX (INSN_ST_MINUS), FULL (st_minus) FAST (st_minus) },
-  { TYPE (INSN_SUB), IDX (INSN_SUB), FULL (sub) FAST (sub) },
-  { TYPE (INSN_SUBV), IDX (INSN_SUBV), FULL (subv) FAST (subv) },
-  { TYPE (INSN_SUBX), IDX (INSN_SUBX), FULL (subx) FAST (subx) },
-  { TYPE (INSN_TRAP), IDX (INSN_TRAP), FULL (trap) FAST (trap) },
-  { TYPE (INSN_UNLOCK), IDX (INSN_UNLOCK), FULL (unlock) FAST (unlock) },
-};
-
-static const struct insn_sem m32rbf_insn_sem_invalid =
-{
-  VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), FULL (x_invalid) FAST (x_invalid)
-};
-
-#undef IDX
-#undef TYPE
-
-/* Initialize an IDESC from the compile-time computable parts.  */
-
-static INLINE void
-init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
-{
-  const CGEN_INSN *opcode_table = m32r_cgen_insn_table_entries;
-
-  id->num = t->index;
-  if ((int) t->type <= 0)
-    id->opcode = & cgen_virtual_opcode_table[- t->type];
-  else
-    id->opcode = & opcode_table[t->type];
-#if ! WITH_SEM_SWITCH_FULL
-  id->sem_full = t->sem_full;
-#endif
-#if WITH_FAST && ! WITH_SEM_SWITCH_FAST
-  id->sem_fast = t->sem_fast;
-#endif
-#if WITH_PROFILE_MODEL_P
-  id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];
-  {
-    SIM_DESC sd = CPU_STATE (cpu);
-    SIM_ASSERT (t->index == id->timing->num);
-  }
-#endif
-}
-
-/* Initialize the instruction descriptor table.  */
-
-void
-m32rbf_init_idesc_table (SIM_CPU *cpu)
-{
-  IDESC *id,*tabend;
-  const struct insn_sem *t,*tend;
-  int tabsize = M32RBF_INSN_MAX;
-  IDESC *table = m32rbf_insn_data;
-
-  memset (table, 0, tabsize * sizeof (IDESC));
-
-  /* First set all entries to the `invalid insn'.  */
-  t = & m32rbf_insn_sem_invalid;
-  for (id = table, tabend = table + tabsize; id < tabend; ++id)
-    init_idesc (cpu, id, t);
-
-  /* Now fill in the values for the chosen cpu.  */
-  for (t = m32rbf_insn_sem, tend = t + sizeof (m32rbf_insn_sem) / sizeof (*t);
-       t != tend; ++t)
-    {
-      init_idesc (cpu, & table[t->index], t);
-    }
-
-  /* Link the IDESC table into the cpu.  */
-  CPU_IDESC (cpu) = table;
-}
-
-/* Enum declaration for all instruction formats.  */
-typedef enum ifmt {
-  FMT_EMPTY, FMT_ADD, FMT_ADD3, FMT_AND3
- , FMT_OR3, FMT_ADDI, FMT_ADDV, FMT_ADDV3
- , FMT_ADDX, FMT_BC8, FMT_BC24, FMT_BEQ
- , FMT_BEQZ, FMT_BL8, FMT_BL24, FMT_BRA8
- , FMT_BRA24, FMT_CMP, FMT_CMPI, FMT_DIV
- , FMT_JL, FMT_JMP, FMT_LD, FMT_LD_D
- , FMT_LDB, FMT_LDB_D, FMT_LDH, FMT_LDH_D
- , FMT_LD_PLUS, FMT_LD24, FMT_LDI8, FMT_LDI16
- , FMT_LOCK, FMT_MACHI, FMT_MULHI, FMT_MV
- , FMT_MVFACHI, FMT_MVFC, FMT_MVTACHI, FMT_MVTC
- , FMT_NOP, FMT_RAC, FMT_RTE, FMT_SETH
- , FMT_SLL3, FMT_SLLI, FMT_ST, FMT_ST_D
- , FMT_STB, FMT_STB_D, FMT_STH, FMT_STH_D
- , FMT_ST_PLUS, FMT_TRAP, FMT_UNLOCK
-} IFMT;
-
-/* The decoder uses this to record insns and direct extraction handling.  */
-
-typedef struct {
-  const IDESC *idesc;
-#ifdef __GNUC__
-  void *ifmt;
-#else
-  enum ifmt ifmt;
-#endif
-} DECODE_DESC;
-
-/* Macro to go from decode phase to extraction phase.  */
-
-#ifdef __GNUC__
-#define GOTO_EXTRACT(id) goto *(id)->ifmt
-#else
-#define GOTO_EXTRACT(id) goto extract
-#endif
-
-/* The decoder needs a slightly different computed goto switch control.  */
-#ifdef __GNUC__
-#define DECODE_SWITCH(N, X) goto *labels_##N[X];
-#else
-#define DECODE_SWITCH(N, X) switch (X)
-#endif
-
-/* Given an instruction, return a pointer to its IDESC entry.  */
-
-const IDESC *
-m32rbf_decode (SIM_CPU *current_cpu, PCADDR pc,
-              CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn,
-              ARGBUF *abuf)
-{
-  /* Result of decoder, used by extractor.  */
-  const DECODE_DESC *idecode;
-
-  /* First decode the instruction.  */
-
-  {
-#define I(insn) & m32rbf_insn_data[CONCAT2 (M32RBF_,insn)]
-#ifdef __GNUC__
-#define E(fmt) && case_ex_##fmt
-#else
-#define E(fmt) fmt
-#endif
-    CGEN_INSN_INT insn = base_insn;
-    static const DECODE_DESC idecode_invalid = { I (INSN_X_INVALID), E (FMT_EMPTY) };
-    {
-#ifdef __GNUC__
-      static const void *labels_0[256] = {
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && case_0_28, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && case_0_87, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && case_0_95, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && case_0_112, && case_0_113, && case_0_114, && case_0_115, 
-        && case_0_116, && case_0_117, && case_0_118, && case_0_119, 
-        && case_0_120, && case_0_121, && case_0_122, && case_0_123, 
-        && case_0_124, && case_0_125, && case_0_126, && case_0_127, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && case_0_240, && case_0_241, && case_0_242, && case_0_243, 
-        && case_0_244, && case_0_245, && case_0_246, && case_0_247, 
-        && case_0_248, && case_0_249, && case_0_250, && case_0_251, 
-        && case_0_252, && case_0_253, && case_0_254, && case_0_255, 
-      };
-#endif
-      static const DECODE_DESC insns[256] = {
-        { I (INSN_SUBV), E (FMT_ADDV) }, { I (INSN_SUBX), E (FMT_ADDX) }, 
-        { I (INSN_SUB), E (FMT_ADD) }, { I (INSN_NEG), E (FMT_MV) }, 
-        { I (INSN_CMP), E (FMT_CMP) }, { I (INSN_CMPU), E (FMT_CMP) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_ADDV), E (FMT_ADDV) }, { I (INSN_ADDX), E (FMT_ADDX) }, 
-        { I (INSN_ADD), E (FMT_ADD) }, { I (INSN_NOT), E (FMT_MV) }, 
-        { I (INSN_AND), E (FMT_ADD) }, { I (INSN_XOR), E (FMT_ADD) }, 
-        { I (INSN_OR), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_SRL), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_SRA), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_SLL), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_MUL), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_MV), E (FMT_MV) }, { I (INSN_MVFC), E (FMT_MVFC) }, 
-        { I (INSN_MVTC), E (FMT_MVTC) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { 0 }, { I (INSN_RTE), E (FMT_RTE) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_TRAP), E (FMT_TRAP) }, 
-        { I (INSN_STB), E (FMT_STB) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_STH), E (FMT_STH) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_ST), E (FMT_ST) }, { I (INSN_UNLOCK), E (FMT_UNLOCK) }, 
-        { I (INSN_ST_PLUS), E (FMT_ST_PLUS) }, { I (INSN_ST_MINUS), E (FMT_ST_PLUS) }, 
-        { I (INSN_LDB), E (FMT_LDB) }, { I (INSN_LDUB), E (FMT_LDB) }, 
-        { I (INSN_LDH), E (FMT_LDH) }, { I (INSN_LDUH), E (FMT_LDH) }, 
-        { I (INSN_LD), E (FMT_LD) }, { I (INSN_LOCK), E (FMT_LOCK) }, 
-        { I (INSN_LD_PLUS), E (FMT_LD_PLUS) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_MULHI), E (FMT_MULHI) }, { I (INSN_MULLO), E (FMT_MULHI) }, 
-        { I (INSN_MULWHI), E (FMT_MULHI) }, { I (INSN_MULWLO), E (FMT_MULHI) }, 
-        { I (INSN_MACHI), E (FMT_MACHI) }, { I (INSN_MACLO), E (FMT_MACHI) }, 
-        { I (INSN_MACWHI), E (FMT_MACHI) }, { I (INSN_MACWLO), E (FMT_MACHI) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, 
-        { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, 
-        { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, 
-        { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, 
-        { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, 
-        { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, 
-        { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, 
-        { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, 
-        { I (INSN_SRLI), E (FMT_SLLI) }, { I (INSN_SRLI), E (FMT_SLLI) }, 
-        { I (INSN_SRAI), E (FMT_SLLI) }, { I (INSN_SRAI), E (FMT_SLLI) }, 
-        { I (INSN_SLLI), E (FMT_SLLI) }, { I (INSN_SLLI), E (FMT_SLLI) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { 0 }, 
-        { I (INSN_RACH), E (FMT_RAC) }, { I (INSN_RAC), E (FMT_RAC) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { 0 }, 
-        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
-        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
-        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
-        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
-        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
-        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
-        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
-        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_CMPI), E (FMT_CMPI) }, { I (INSN_CMPUI), E (FMT_CMPI) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_ADDV3), E (FMT_ADDV3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_ADD3), E (FMT_ADD3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_AND3), E (FMT_AND3) }, { I (INSN_XOR3), E (FMT_AND3) }, 
-        { I (INSN_OR3), E (FMT_OR3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_DIV), E (FMT_DIV) }, { I (INSN_DIVU), E (FMT_DIV) }, 
-        { I (INSN_REM), E (FMT_DIV) }, { I (INSN_REMU), E (FMT_DIV) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_SRL3), E (FMT_SLL3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_SRA3), E (FMT_SLL3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_SLL3), E (FMT_SLL3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LDI16), E (FMT_LDI16) }, 
-        { I (INSN_STB_D), E (FMT_STB_D) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_STH_D), E (FMT_STH_D) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_ST_D), E (FMT_ST_D) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_LDB_D), E (FMT_LDB_D) }, { I (INSN_LDUB_D), E (FMT_LDB_D) }, 
-        { I (INSN_LDH_D), E (FMT_LDH_D) }, { I (INSN_LDUH_D), E (FMT_LDH_D) }, 
-        { I (INSN_LD_D), E (FMT_LD_D) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_BEQ), E (FMT_BEQ) }, { I (INSN_BNE), E (FMT_BEQ) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_BEQZ), E (FMT_BEQZ) }, { I (INSN_BNEZ), E (FMT_BEQZ) }, 
-        { I (INSN_BLTZ), E (FMT_BEQZ) }, { I (INSN_BGEZ), E (FMT_BEQZ) }, 
-        { I (INSN_BLEZ), E (FMT_BEQZ) }, { I (INSN_BGTZ), E (FMT_BEQZ) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_SETH), E (FMT_SETH) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, 
-        { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, 
-        { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, 
-        { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, 
-        { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, 
-        { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, 
-        { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, 
-        { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-      };
-      unsigned int val;
-      val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
-      DECODE_SWITCH (0, val)
-        {
-        CASE (0, 28) :
-          {
-            static const DECODE_DESC insns[16] = {
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_JL), E (FMT_JL) }, { I (INSN_JMP), E (FMT_JMP) }, 
-            };
-            unsigned int val = (((insn >> 8) & (15 << 0)));
-            idecode = &insns[val];
-            GOTO_EXTRACT (idecode);
-          }
-        CASE (0, 87) :
-          {
-            static const DECODE_DESC insns[16] = {
-              { I (INSN_MVTACHI), E (FMT_MVTACHI) }, { I (INSN_MVTACLO), E (FMT_MVTACHI) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-            };
-            unsigned int val = (((insn >> 0) & (15 << 0)));
-            idecode = &insns[val];
-            GOTO_EXTRACT (idecode);
-          }
-        CASE (0, 95) :
-          {
-            static const DECODE_DESC insns[16] = {
-              { I (INSN_MVFACHI), E (FMT_MVFACHI) }, { I (INSN_MVFACLO), E (FMT_MVFACHI) }, 
-              { I (INSN_MVFACMI), E (FMT_MVFACHI) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-            };
-            unsigned int val = (((insn >> 0) & (15 << 0)));
-            idecode = &insns[val];
-            GOTO_EXTRACT (idecode);
-          }
-        CASE (0, 112) :
-          {
-            static const DECODE_DESC insns[16] = {
-              { I (INSN_NOP), E (FMT_NOP) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_BC8), E (FMT_BC8) }, { I (INSN_BNC8), E (FMT_BC8) }, 
-              { I (INSN_BL8), E (FMT_BL8) }, { I (INSN_BRA8), E (FMT_BRA8) }, 
-            };
-            unsigned int val = (((insn >> 8) & (15 << 0)));
-            idecode = &insns[val];
-            GOTO_EXTRACT (idecode);
-          }
-        CASE (0, 113) : /* fall through */
-        CASE (0, 114) : /* fall through */
-        CASE (0, 115) : /* fall through */
-        CASE (0, 116) : /* fall through */
-        CASE (0, 117) : /* fall through */
-        CASE (0, 118) : /* fall through */
-        CASE (0, 119) : /* fall through */
-        CASE (0, 120) : /* fall through */
-        CASE (0, 121) : /* fall through */
-        CASE (0, 122) : /* fall through */
-        CASE (0, 123) : /* fall through */
-        CASE (0, 124) : /* fall through */
-        CASE (0, 125) : /* fall through */
-        CASE (0, 126) : /* fall through */
-        CASE (0, 127) :
-          {
-            static const DECODE_DESC insns[16] = {
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_BC8), E (FMT_BC8) }, { I (INSN_BNC8), E (FMT_BC8) }, 
-              { I (INSN_BL8), E (FMT_BL8) }, { I (INSN_BRA8), E (FMT_BRA8) }, 
-            };
-            unsigned int val = (((insn >> 8) & (15 << 0)));
-            idecode = &insns[val];
-            GOTO_EXTRACT (idecode);
-          }
-        CASE (0, 240) : /* fall through */
-        CASE (0, 241) : /* fall through */
-        CASE (0, 242) : /* fall through */
-        CASE (0, 243) : /* fall through */
-        CASE (0, 244) : /* fall through */
-        CASE (0, 245) : /* fall through */
-        CASE (0, 246) : /* fall through */
-        CASE (0, 247) : /* fall through */
-        CASE (0, 248) : /* fall through */
-        CASE (0, 249) : /* fall through */
-        CASE (0, 250) : /* fall through */
-        CASE (0, 251) : /* fall through */
-        CASE (0, 252) : /* fall through */
-        CASE (0, 253) : /* fall through */
-        CASE (0, 254) : /* fall through */
-        CASE (0, 255) :
-          {
-            static const DECODE_DESC insns[16] = {
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_BC24), E (FMT_BC24) }, { I (INSN_BNC24), E (FMT_BC24) }, 
-              { I (INSN_BL24), E (FMT_BL24) }, { I (INSN_BRA24), E (FMT_BRA24) }, 
-            };
-            unsigned int val = (((insn >> 8) & (15 << 0)));
-            idecode = &insns[val];
-            GOTO_EXTRACT (idecode);
-          }
-        DEFAULT (0) :
-          idecode = &insns[val];
-          GOTO_EXTRACT (idecode);
-        }
-      ENDSWITCH (0)
-    }
-#undef I
-#undef E
-  }
-
-  /* The instruction has been decoded, now extract the fields.  */
-
- extract:
-  {
-#ifndef __GNUC__
-    switch (idecode->ifmt)
-#endif
-      {
-
-  CASE (ex, FMT_EMPTY) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_empty.f
-  EXTRACT_FMT_EMPTY_VARS /* */
-
-  EXTRACT_FMT_EMPTY_CODE
-
-  /* Record the fields for the semantic handler.  */
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_empty", (char *) 0));
-
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_ADD) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_add.f
-  EXTRACT_FMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_FMT_ADD_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_add", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_dr) = f_r1;
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_ADD3) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_add3.f
-  EXTRACT_FMT_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
-
-  EXTRACT_FMT_ADD3_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_add3", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_AND3) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_and3.f
-  EXTRACT_FMT_AND3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
-
-  EXTRACT_FMT_AND3_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_uimm16) = f_uimm16;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_and3", "f_uimm16 0x%x", 'x', f_uimm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_OR3) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_or3.f
-  EXTRACT_FMT_OR3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
-
-  EXTRACT_FMT_OR3_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_uimm16) = f_uimm16;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_or3", "f_uimm16 0x%x", 'x', f_uimm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_ADDI) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_addi.f
-  EXTRACT_FMT_ADDI_VARS /* f-op1 f-r1 f-simm8 */
-
-  EXTRACT_FMT_ADDI_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm8) = f_simm8;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addi", "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_dr) = f_r1;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_ADDV) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_addv.f
-  EXTRACT_FMT_ADDV_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_FMT_ADDV_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addv", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_dr) = f_r1;
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_ADDV3) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_addv3.f
-  EXTRACT_FMT_ADDV3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
-
-  EXTRACT_FMT_ADDV3_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addv3", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_ADDX) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_addx.f
-  EXTRACT_FMT_ADDX_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_FMT_ADDX_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addx", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_dr) = f_r1;
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_BC8) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
-  EXTRACT_FMT_BC8_VARS /* f-op1 f-r1 f-disp8 */
-
-  EXTRACT_FMT_BC8_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_disp8) = f_disp8;
-  SEM_BRANCH_INIT_EXTRACT (abuf);
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_BC24) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
-  EXTRACT_FMT_BC24_VARS /* f-op1 f-r1 f-disp24 */
-
-  EXTRACT_FMT_BC24_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_disp24) = f_disp24;
-  SEM_BRANCH_INIT_EXTRACT (abuf);
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_BEQ) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.cti.fields.fmt_beq.f
-  EXTRACT_FMT_BEQ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
-
-  EXTRACT_FMT_BEQ_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  FLD (i_disp16) = f_disp16;
-  SEM_BRANCH_INIT_EXTRACT (abuf);
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_beq", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_BEQZ) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
-  EXTRACT_FMT_BEQZ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
-
-  EXTRACT_FMT_BEQZ_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  FLD (i_disp16) = f_disp16;
-  SEM_BRANCH_INIT_EXTRACT (abuf);
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_beqz", "src2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_BL8) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.cti.fields.fmt_bl8.f
-  EXTRACT_FMT_BL8_VARS /* f-op1 f-r1 f-disp8 */
-
-  EXTRACT_FMT_BL8_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_disp8) = f_disp8;
-  SEM_BRANCH_INIT_EXTRACT (abuf);
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_h_gr_14) = 14;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_BL24) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.cti.fields.fmt_bl24.f
-  EXTRACT_FMT_BL24_VARS /* f-op1 f-r1 f-disp24 */
-
-  EXTRACT_FMT_BL24_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_disp24) = f_disp24;
-  SEM_BRANCH_INIT_EXTRACT (abuf);
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_h_gr_14) = 14;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_BRA8) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.cti.fields.fmt_bra8.f
-  EXTRACT_FMT_BRA8_VARS /* f-op1 f-r1 f-disp8 */
-
-  EXTRACT_FMT_BRA8_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_disp8) = f_disp8;
-  SEM_BRANCH_INIT_EXTRACT (abuf);
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_BRA24) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.cti.fields.fmt_bra24.f
-  EXTRACT_FMT_BRA24_VARS /* f-op1 f-r1 f-disp24 */
-
-  EXTRACT_FMT_BRA24_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_disp24) = f_disp24;
-  SEM_BRANCH_INIT_EXTRACT (abuf);
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_CMP) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_cmp.f
-  EXTRACT_FMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_FMT_CMP_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmp", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_CMPI) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_cmpi.f
-  EXTRACT_FMT_CMPI_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
-
-  EXTRACT_FMT_CMPI_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpi", "f_simm16 0x%x", 'x', f_simm16, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_DIV) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_div.f
-  EXTRACT_FMT_DIV_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
-
-  EXTRACT_FMT_DIV_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_div", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (in_dr) = f_r1;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_JL) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.cti.fields.fmt_jl.f
-  EXTRACT_FMT_JL_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_FMT_JL_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  SEM_BRANCH_INIT_EXTRACT (abuf);
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_jl", "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_h_gr_14) = 14;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_JMP) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
-  EXTRACT_FMT_JMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_FMT_JMP_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  SEM_BRANCH_INIT_EXTRACT (abuf);
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_jmp", "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_LD) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_ld.f
-  EXTRACT_FMT_LD_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_FMT_LD_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_LD_D) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_ld_d.f
-  EXTRACT_FMT_LD_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
-
-  EXTRACT_FMT_LD_D_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_d", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_LDB) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_ldb.f
-  EXTRACT_FMT_LDB_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_FMT_LDB_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldb", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_LDB_D) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_ldb_d.f
-  EXTRACT_FMT_LDB_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
-
-  EXTRACT_FMT_LDB_D_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldb_d", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_LDH) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_ldh.f
-  EXTRACT_FMT_LDH_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_FMT_LDH_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldh", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_LDH_D) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_ldh_d.f
-  EXTRACT_FMT_LDH_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
-
-  EXTRACT_FMT_LDH_D_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldh_d", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_LD_PLUS) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_ld_plus.f
-  EXTRACT_FMT_LD_PLUS_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_FMT_LD_PLUS_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_plus", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-      FLD (out_sr) = f_r2;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_LD24) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_ld24.f
-  EXTRACT_FMT_LD24_VARS /* f-op1 f-r1 f-uimm24 */
-
-  EXTRACT_FMT_LD24_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_uimm24) = f_uimm24;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld24", "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_LDI8) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_ldi8.f
-  EXTRACT_FMT_LDI8_VARS /* f-op1 f-r1 f-simm8 */
-
-  EXTRACT_FMT_LDI8_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm8) = f_simm8;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldi8", "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_LDI16) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_ldi16.f
-  EXTRACT_FMT_LDI16_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
-
-  EXTRACT_FMT_LDI16_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldi16", "f_simm16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_LOCK) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_lock.f
-  EXTRACT_FMT_LOCK_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_FMT_LOCK_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_lock", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_MACHI) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_machi.f
-  EXTRACT_FMT_MACHI_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_FMT_MACHI_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_machi", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_MULHI) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_mulhi.f
-  EXTRACT_FMT_MULHI_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_FMT_MULHI_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mulhi", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_MV) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_mv.f
-  EXTRACT_FMT_MV_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_FMT_MV_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mv", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_MVFACHI) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_mvfachi.f
-  EXTRACT_FMT_MVFACHI_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_FMT_MVFACHI_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mvfachi", "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_MVFC) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_mvfc.f
-  EXTRACT_FMT_MVFC_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_FMT_MVFC_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mvfc", "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_MVTACHI) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_mvtachi.f
-  EXTRACT_FMT_MVTACHI_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_FMT_MVTACHI_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mvtachi", "src1 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_MVTC) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_mvtc.f
-  EXTRACT_FMT_MVTC_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_FMT_MVTC_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mvtc", "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_NOP) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_nop.f
-  EXTRACT_FMT_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_FMT_NOP_CODE
-
-  /* Record the fields for the semantic handler.  */
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_nop", (char *) 0));
-
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_RAC) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_rac.f
-  EXTRACT_FMT_RAC_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_FMT_RAC_CODE
-
-  /* Record the fields for the semantic handler.  */
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_rac", (char *) 0));
-
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_RTE) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.cti.fields.fmt_rte.f
-  EXTRACT_FMT_RTE_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_FMT_RTE_CODE
-
-  /* Record the fields for the semantic handler.  */
-  SEM_BRANCH_INIT_EXTRACT (abuf);
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_rte", (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_SETH) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_seth.f
-  EXTRACT_FMT_SETH_VARS /* f-op1 f-r1 f-op2 f-r2 f-hi16 */
-
-  EXTRACT_FMT_SETH_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_hi16) = f_hi16;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_seth", "f_hi16 0x%x", 'x', f_hi16, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_SLL3) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_sll3.f
-  EXTRACT_FMT_SLL3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
-
-  EXTRACT_FMT_SLL3_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_sll3", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_SLLI) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_slli.f
-  EXTRACT_FMT_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */
-
-  EXTRACT_FMT_SLLI_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_uimm5) = f_uimm5;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_slli", "f_uimm5 0x%x", 'x', f_uimm5, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_dr) = f_r1;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_ST) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_st.f
-  EXTRACT_FMT_ST_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_FMT_ST_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st", "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src2) = f_r2;
-      FLD (in_src1) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_ST_D) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_st_d.f
-  EXTRACT_FMT_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
-
-  EXTRACT_FMT_ST_D_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_d", "f_simm16 0x%x", 'x', f_simm16, "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src2) = f_r2;
-      FLD (in_src1) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_STB) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_stb.f
-  EXTRACT_FMT_STB_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_FMT_STB_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stb", "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src2) = f_r2;
-      FLD (in_src1) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_STB_D) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_stb_d.f
-  EXTRACT_FMT_STB_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
-
-  EXTRACT_FMT_STB_D_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stb_d", "f_simm16 0x%x", 'x', f_simm16, "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src2) = f_r2;
-      FLD (in_src1) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_STH) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_sth.f
-  EXTRACT_FMT_STH_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_FMT_STH_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_sth", "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src2) = f_r2;
-      FLD (in_src1) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_STH_D) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_sth_d.f
-  EXTRACT_FMT_STH_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
-
-  EXTRACT_FMT_STH_D_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_sth_d", "f_simm16 0x%x", 'x', f_simm16, "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src2) = f_r2;
-      FLD (in_src1) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_ST_PLUS) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_st_plus.f
-  EXTRACT_FMT_ST_PLUS_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_FMT_ST_PLUS_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_plus", "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src2) = f_r2;
-      FLD (in_src1) = f_r1;
-      FLD (out_src2) = f_r2;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_TRAP) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.cti.fields.fmt_trap.f
-  EXTRACT_FMT_TRAP_VARS /* f-op1 f-r1 f-op2 f-uimm4 */
-
-  EXTRACT_FMT_TRAP_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_uimm4) = f_uimm4;
-  SEM_BRANCH_INIT_EXTRACT (abuf);
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_trap", "f_uimm4 0x%x", 'x', f_uimm4, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_UNLOCK) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_unlock.f
-  EXTRACT_FMT_UNLOCK_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_FMT_UNLOCK_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_unlock", "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src2) = f_r2;
-      FLD (in_src1) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-
-      }
-    ENDSWITCH (ex)
-
-  }
-
-  return idecode->idesc;
-}
diff --git a/sim/m32r/decode.h b/sim/m32r/decode.h
deleted file mode 100644
index 206adb2..0000000
--- a/sim/m32r/decode.h
+++ /dev/null
@@ -1,237 +0,0 @@
-/* Decode header for m32rbf.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
-
-This file is part of the GNU Simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#ifndef M32RBF_DECODE_H
-#define M32RBF_DECODE_H
-
-/* Run-time computed instruction descriptor.  */
-
-struct idesc {
-#if WITH_SEM_SWITCH_FULL
-#ifdef __GNUC__
-  void *sem_full_lab;
-#endif
-#else
-  SEMANTIC_FN *sem_full;
-#endif
-
-#if WITH_SEM_SWITCH_FAST
-#ifdef __GNUC__
-  void *sem_fast_lab;
-#endif
-#else
-  SEMANTIC_FN *sem_fast;
-#endif
-
-  /* Instruction number (index in IDESC table, profile table).
-     Also used to switch on in non-gcc semantic switches.  */
-  int num;
-
-  /* opcode table data */
-  const CGEN_INSN *opcode;
-
-  /* profiling/modelling support */
-  const INSN_TIMING *timing;
-};
-
-extern const IDESC *m32rbf_decode (SIM_CPU *, IADDR,
-                                  CGEN_INSN_INT, CGEN_INSN_INT,
-                                  ARGBUF *);
-
-/* Enum declaration for instructions in cpu family m32rbf.  */
-typedef enum m32rbf_insn_type {
-  M32RBF_INSN_X_INVALID, M32RBF_INSN_X_AFTER, M32RBF_INSN_X_BEFORE, M32RBF_INSN_X_CTI_CHAIN
- , M32RBF_INSN_X_CHAIN, M32RBF_INSN_X_BEGIN, M32RBF_INSN_ADD, M32RBF_INSN_ADD3
- , M32RBF_INSN_AND, M32RBF_INSN_AND3, M32RBF_INSN_OR, M32RBF_INSN_OR3
- , M32RBF_INSN_XOR, M32RBF_INSN_XOR3, M32RBF_INSN_ADDI, M32RBF_INSN_ADDV
- , M32RBF_INSN_ADDV3, M32RBF_INSN_ADDX, M32RBF_INSN_BC8, M32RBF_INSN_BC24
- , M32RBF_INSN_BEQ, M32RBF_INSN_BEQZ, M32RBF_INSN_BGEZ, M32RBF_INSN_BGTZ
- , M32RBF_INSN_BLEZ, M32RBF_INSN_BLTZ, M32RBF_INSN_BNEZ, M32RBF_INSN_BL8
- , M32RBF_INSN_BL24, M32RBF_INSN_BNC8, M32RBF_INSN_BNC24, M32RBF_INSN_BNE
- , M32RBF_INSN_BRA8, M32RBF_INSN_BRA24, M32RBF_INSN_CMP, M32RBF_INSN_CMPI
- , M32RBF_INSN_CMPU, M32RBF_INSN_CMPUI, M32RBF_INSN_DIV, M32RBF_INSN_DIVU
- , M32RBF_INSN_REM, M32RBF_INSN_REMU, M32RBF_INSN_JL, M32RBF_INSN_JMP
- , M32RBF_INSN_LD, M32RBF_INSN_LD_D, M32RBF_INSN_LDB, M32RBF_INSN_LDB_D
- , M32RBF_INSN_LDH, M32RBF_INSN_LDH_D, M32RBF_INSN_LDUB, M32RBF_INSN_LDUB_D
- , M32RBF_INSN_LDUH, M32RBF_INSN_LDUH_D, M32RBF_INSN_LD_PLUS, M32RBF_INSN_LD24
- , M32RBF_INSN_LDI8, M32RBF_INSN_LDI16, M32RBF_INSN_LOCK, M32RBF_INSN_MACHI
- , M32RBF_INSN_MACLO, M32RBF_INSN_MACWHI, M32RBF_INSN_MACWLO, M32RBF_INSN_MUL
- , M32RBF_INSN_MULHI, M32RBF_INSN_MULLO, M32RBF_INSN_MULWHI, M32RBF_INSN_MULWLO
- , M32RBF_INSN_MV, M32RBF_INSN_MVFACHI, M32RBF_INSN_MVFACLO, M32RBF_INSN_MVFACMI
- , M32RBF_INSN_MVFC, M32RBF_INSN_MVTACHI, M32RBF_INSN_MVTACLO, M32RBF_INSN_MVTC
- , M32RBF_INSN_NEG, M32RBF_INSN_NOP, M32RBF_INSN_NOT, M32RBF_INSN_RAC
- , M32RBF_INSN_RACH, M32RBF_INSN_RTE, M32RBF_INSN_SETH, M32RBF_INSN_SLL
- , M32RBF_INSN_SLL3, M32RBF_INSN_SLLI, M32RBF_INSN_SRA, M32RBF_INSN_SRA3
- , M32RBF_INSN_SRAI, M32RBF_INSN_SRL, M32RBF_INSN_SRL3, M32RBF_INSN_SRLI
- , M32RBF_INSN_ST, M32RBF_INSN_ST_D, M32RBF_INSN_STB, M32RBF_INSN_STB_D
- , M32RBF_INSN_STH, M32RBF_INSN_STH_D, M32RBF_INSN_ST_PLUS, M32RBF_INSN_ST_MINUS
- , M32RBF_INSN_SUB, M32RBF_INSN_SUBV, M32RBF_INSN_SUBX, M32RBF_INSN_TRAP
- , M32RBF_INSN_UNLOCK, M32RBF_INSN_MAX
-} M32RBF_INSN_TYPE;
-
-#if ! WITH_SEM_SWITCH_FULL
-#define SEMFULL(fn) extern SEMANTIC_FN CONCAT3 (m32rbf,_sem_,fn);
-#else
-#define SEMFULL(fn)
-#endif
-
-#if ! WITH_SEM_SWITCH_FAST
-#define SEMFAST(fn) extern SEMANTIC_FN CONCAT3 (m32rbf,_semf_,fn);
-#else
-#define SEMFAST(fn)
-#endif
-
-#define SEM(fn) SEMFULL (fn) SEMFAST (fn)
-
-/* The function version of the before/after handlers is always needed,
-   so we always want the SEMFULL declaration of them.  */
-extern SEMANTIC_FN CONCAT3 (m32rbf,_sem_,x_before);
-extern SEMANTIC_FN CONCAT3 (m32rbf,_sem_,x_after);
-
-SEM (x_invalid)
-SEM (x_after)
-SEM (x_before)
-SEM (x_cti_chain)
-SEM (x_chain)
-SEM (x_begin)
-SEM (add)
-SEM (add3)
-SEM (and)
-SEM (and3)
-SEM (or)
-SEM (or3)
-SEM (xor)
-SEM (xor3)
-SEM (addi)
-SEM (addv)
-SEM (addv3)
-SEM (addx)
-SEM (bc8)
-SEM (bc24)
-SEM (beq)
-SEM (beqz)
-SEM (bgez)
-SEM (bgtz)
-SEM (blez)
-SEM (bltz)
-SEM (bnez)
-SEM (bl8)
-SEM (bl24)
-SEM (bnc8)
-SEM (bnc24)
-SEM (bne)
-SEM (bra8)
-SEM (bra24)
-SEM (cmp)
-SEM (cmpi)
-SEM (cmpu)
-SEM (cmpui)
-SEM (div)
-SEM (divu)
-SEM (rem)
-SEM (remu)
-SEM (jl)
-SEM (jmp)
-SEM (ld)
-SEM (ld_d)
-SEM (ldb)
-SEM (ldb_d)
-SEM (ldh)
-SEM (ldh_d)
-SEM (ldub)
-SEM (ldub_d)
-SEM (lduh)
-SEM (lduh_d)
-SEM (ld_plus)
-SEM (ld24)
-SEM (ldi8)
-SEM (ldi16)
-SEM (lock)
-SEM (machi)
-SEM (maclo)
-SEM (macwhi)
-SEM (macwlo)
-SEM (mul)
-SEM (mulhi)
-SEM (mullo)
-SEM (mulwhi)
-SEM (mulwlo)
-SEM (mv)
-SEM (mvfachi)
-SEM (mvfaclo)
-SEM (mvfacmi)
-SEM (mvfc)
-SEM (mvtachi)
-SEM (mvtaclo)
-SEM (mvtc)
-SEM (neg)
-SEM (nop)
-SEM (not)
-SEM (rac)
-SEM (rach)
-SEM (rte)
-SEM (seth)
-SEM (sll)
-SEM (sll3)
-SEM (slli)
-SEM (sra)
-SEM (sra3)
-SEM (srai)
-SEM (srl)
-SEM (srl3)
-SEM (srli)
-SEM (st)
-SEM (st_d)
-SEM (stb)
-SEM (stb_d)
-SEM (sth)
-SEM (sth_d)
-SEM (st_plus)
-SEM (st_minus)
-SEM (sub)
-SEM (subv)
-SEM (subx)
-SEM (trap)
-SEM (unlock)
-
-#undef SEMFULL
-#undef SEMFAST
-#undef SEM
-
-/* Function unit handlers (user written).  */
-
-extern int m32rbf_model_m32r_d_u_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
-extern int m32rbf_model_m32r_d_u_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/, INT /*dr*/);
-extern int m32rbf_model_m32r_d_u_cti (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/);
-extern int m32rbf_model_m32r_d_u_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
-extern int m32rbf_model_m32r_d_u_cmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
-extern int m32rbf_model_m32r_d_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/, INT /*sr2*/, INT /*dr*/);
-extern int m32rbf_model_test_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
-
-/* Profiling before/after handlers (user written) */
-
-extern void m32rbf_model_insn_before (SIM_CPU *, int /*first_p*/);
-extern void m32rbf_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
-
-#endif /* M32RBF_DECODE_H */
diff --git a/sim/m32r/decodex.c b/sim/m32r/decodex.c
deleted file mode 100644
index bc61f5d..0000000
--- a/sim/m32r/decodex.c
+++ /dev/null
@@ -1,2453 +0,0 @@
-/* Simulator instruction decoder for m32rxf.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
-
-This file is part of the GNU Simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#define WANT_CPU m32rxf
-#define WANT_CPU_M32RXF
-
-#include "sim-main.h"
-#include "sim-assert.h"
-
-#ifdef __GNUC__
-#define FMT(n)
-#else
-#define FMT(n) CONCAT2 (M32RXF_,n) ,
-#endif
-
-/* FIXME: Need to review choices for the following.  */
-
-#if WITH_SEM_SWITCH_FULL
-#define FULL(fn)
-#else
-#define FULL(fn) CONCAT3 (m32rxf,_sem_,fn) ,
-#endif
-
-#if WITH_FAST
-#if WITH_SEM_SWITCH_FAST
-#define FAST(fn)
-#else
-#define FAST(fn) CONCAT3 (m32rxf,_semf_,fn) , /* f for fast */
-#endif
-#else
-#define FAST(fn)
-#endif
-
-/* The instruction descriptor array.
-   This is computed at runtime.  Space for it is not malloc'd to save a
-   teensy bit of cpu in the decoder.  Moving it to malloc space is trivial
-   but won't be done until necessary (we don't currently support the runtime
-   addition of instructions nor an SMP machine with different cpus).  */
-static IDESC m32rxf_insn_data[M32RXF_INSN_MAX];
-
-/* Instruction semantic handlers and support.
-   This struct defines the part of an IDESC that can be computed at
-   compile time.  */
-
-struct insn_sem {
-  /* The instruction type (a number that identifies each insn over the
-     entire architecture).  */
-  CGEN_INSN_TYPE type;
-
-  /* Index in IDESC table.  */
-  int index;
-
-  /* Index in IDESC table of parallel handler.  */
-  int par_index;
-
-  /* Index in IDESC table of writeback handler.  */
-  int write_index;
-
-  /* Routines to execute the insn.
-     The full version has all features (profiling,tracing) compiled in.
-     The fast version has none of that.  */
-#if ! WITH_SEM_SWITCH_FULL
-  SEMANTIC_FN *sem_full;
-#endif
-#if WITH_FAST && ! WITH_SEM_SWITCH_FAST
-  SEMANTIC_FN *sem_fast;
-#endif
-
-};
-/* The INSN_ prefix is not here and is instead part of the `insn' argument
-   to avoid collisions with header files (e.g. `AND' in ansidecl.h).  */
-#define IDX(insn) CONCAT2 (M32RXF_,insn)
-#define TYPE(insn) CONCAT2 (M32R_,insn)
-
-/* Insn can't be executed in parallel.
-   Or is that "do NOt Pass to Air defense Radar"? :-) */
-#define NOPAR (-1)
-
-/* Commas between elements are contained in the macros.
-   Some of these are conditionally compiled out.  */
-
-static const struct insn_sem m32rxf_insn_sem[] =
-{
-  { VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), NOPAR, NOPAR, FULL (x_invalid) FAST (x_invalid) },
-  { VIRTUAL_INSN_X_AFTER, IDX (INSN_X_AFTER), NOPAR, NOPAR, FULL (x_after) FAST (x_after) },
-  { VIRTUAL_INSN_X_BEFORE, IDX (INSN_X_BEFORE), NOPAR, NOPAR, FULL (x_before) FAST (x_before) },
-  { VIRTUAL_INSN_X_CTI_CHAIN, IDX (INSN_X_CTI_CHAIN), NOPAR, NOPAR, FULL (x_cti_chain) FAST (x_cti_chain) },
-  { VIRTUAL_INSN_X_CHAIN, IDX (INSN_X_CHAIN), NOPAR, NOPAR, FULL (x_chain) FAST (x_chain) },
-  { VIRTUAL_INSN_X_BEGIN, IDX (INSN_X_BEGIN), NOPAR, NOPAR, FULL (x_begin) FAST (x_begin) },
-  { TYPE (INSN_ADD), IDX (INSN_ADD), IDX (INSN_PAR_ADD), IDX (INSN_WRITE_ADD), FULL (add) FAST (add) },
-  { TYPE (INSN_ADD3), IDX (INSN_ADD3), NOPAR, NOPAR, FULL (add3) FAST (add3) },
-  { TYPE (INSN_AND), IDX (INSN_AND), IDX (INSN_PAR_AND), IDX (INSN_WRITE_AND), FULL (and) FAST (and) },
-  { TYPE (INSN_AND3), IDX (INSN_AND3), NOPAR, NOPAR, FULL (and3) FAST (and3) },
-  { TYPE (INSN_OR), IDX (INSN_OR), IDX (INSN_PAR_OR), IDX (INSN_WRITE_OR), FULL (or) FAST (or) },
-  { TYPE (INSN_OR3), IDX (INSN_OR3), NOPAR, NOPAR, FULL (or3) FAST (or3) },
-  { TYPE (INSN_XOR), IDX (INSN_XOR), IDX (INSN_PAR_XOR), IDX (INSN_WRITE_XOR), FULL (xor) FAST (xor) },
-  { TYPE (INSN_XOR3), IDX (INSN_XOR3), NOPAR, NOPAR, FULL (xor3) FAST (xor3) },
-  { TYPE (INSN_ADDI), IDX (INSN_ADDI), IDX (INSN_PAR_ADDI), IDX (INSN_WRITE_ADDI), FULL (addi) FAST (addi) },
-  { TYPE (INSN_ADDV), IDX (INSN_ADDV), IDX (INSN_PAR_ADDV), IDX (INSN_WRITE_ADDV), FULL (addv) FAST (addv) },
-  { TYPE (INSN_ADDV3), IDX (INSN_ADDV3), NOPAR, NOPAR, FULL (addv3) FAST (addv3) },
-  { TYPE (INSN_ADDX), IDX (INSN_ADDX), IDX (INSN_PAR_ADDX), IDX (INSN_WRITE_ADDX), FULL (addx) FAST (addx) },
-  { TYPE (INSN_BC8), IDX (INSN_BC8), IDX (INSN_PAR_BC8), IDX (INSN_WRITE_BC8), FULL (bc8) FAST (bc8) },
-  { TYPE (INSN_BC24), IDX (INSN_BC24), NOPAR, NOPAR, FULL (bc24) FAST (bc24) },
-  { TYPE (INSN_BEQ), IDX (INSN_BEQ), NOPAR, NOPAR, FULL (beq) FAST (beq) },
-  { TYPE (INSN_BEQZ), IDX (INSN_BEQZ), NOPAR, NOPAR, FULL (beqz) FAST (beqz) },
-  { TYPE (INSN_BGEZ), IDX (INSN_BGEZ), NOPAR, NOPAR, FULL (bgez) FAST (bgez) },
-  { TYPE (INSN_BGTZ), IDX (INSN_BGTZ), NOPAR, NOPAR, FULL (bgtz) FAST (bgtz) },
-  { TYPE (INSN_BLEZ), IDX (INSN_BLEZ), NOPAR, NOPAR, FULL (blez) FAST (blez) },
-  { TYPE (INSN_BLTZ), IDX (INSN_BLTZ), NOPAR, NOPAR, FULL (bltz) FAST (bltz) },
-  { TYPE (INSN_BNEZ), IDX (INSN_BNEZ), NOPAR, NOPAR, FULL (bnez) FAST (bnez) },
-  { TYPE (INSN_BL8), IDX (INSN_BL8), IDX (INSN_PAR_BL8), IDX (INSN_WRITE_BL8), FULL (bl8) FAST (bl8) },
-  { TYPE (INSN_BL24), IDX (INSN_BL24), NOPAR, NOPAR, FULL (bl24) FAST (bl24) },
-  { TYPE (INSN_BCL8), IDX (INSN_BCL8), IDX (INSN_PAR_BCL8), IDX (INSN_WRITE_BCL8), FULL (bcl8) FAST (bcl8) },
-  { TYPE (INSN_BCL24), IDX (INSN_BCL24), NOPAR, NOPAR, FULL (bcl24) FAST (bcl24) },
-  { TYPE (INSN_BNC8), IDX (INSN_BNC8), IDX (INSN_PAR_BNC8), IDX (INSN_WRITE_BNC8), FULL (bnc8) FAST (bnc8) },
-  { TYPE (INSN_BNC24), IDX (INSN_BNC24), NOPAR, NOPAR, FULL (bnc24) FAST (bnc24) },
-  { TYPE (INSN_BNE), IDX (INSN_BNE), NOPAR, NOPAR, FULL (bne) FAST (bne) },
-  { TYPE (INSN_BRA8), IDX (INSN_BRA8), IDX (INSN_PAR_BRA8), IDX (INSN_WRITE_BRA8), FULL (bra8) FAST (bra8) },
-  { TYPE (INSN_BRA24), IDX (INSN_BRA24), NOPAR, NOPAR, FULL (bra24) FAST (bra24) },
-  { TYPE (INSN_BNCL8), IDX (INSN_BNCL8), IDX (INSN_PAR_BNCL8), IDX (INSN_WRITE_BNCL8), FULL (bncl8) FAST (bncl8) },
-  { TYPE (INSN_BNCL24), IDX (INSN_BNCL24), NOPAR, NOPAR, FULL (bncl24) FAST (bncl24) },
-  { TYPE (INSN_CMP), IDX (INSN_CMP), IDX (INSN_PAR_CMP), IDX (INSN_WRITE_CMP), FULL (cmp) FAST (cmp) },
-  { TYPE (INSN_CMPI), IDX (INSN_CMPI), NOPAR, NOPAR, FULL (cmpi) FAST (cmpi) },
-  { TYPE (INSN_CMPU), IDX (INSN_CMPU), IDX (INSN_PAR_CMPU), IDX (INSN_WRITE_CMPU), FULL (cmpu) FAST (cmpu) },
-  { TYPE (INSN_CMPUI), IDX (INSN_CMPUI), NOPAR, NOPAR, FULL (cmpui) FAST (cmpui) },
-  { TYPE (INSN_CMPEQ), IDX (INSN_CMPEQ), IDX (INSN_PAR_CMPEQ), IDX (INSN_WRITE_CMPEQ), FULL (cmpeq) FAST (cmpeq) },
-  { TYPE (INSN_CMPZ), IDX (INSN_CMPZ), IDX (INSN_PAR_CMPZ), IDX (INSN_WRITE_CMPZ), FULL (cmpz) FAST (cmpz) },
-  { TYPE (INSN_DIV), IDX (INSN_DIV), NOPAR, NOPAR, FULL (div) FAST (div) },
-  { TYPE (INSN_DIVU), IDX (INSN_DIVU), NOPAR, NOPAR, FULL (divu) FAST (divu) },
-  { TYPE (INSN_REM), IDX (INSN_REM), NOPAR, NOPAR, FULL (rem) FAST (rem) },
-  { TYPE (INSN_REMU), IDX (INSN_REMU), NOPAR, NOPAR, FULL (remu) FAST (remu) },
-  { TYPE (INSN_DIVH), IDX (INSN_DIVH), NOPAR, NOPAR, FULL (divh) FAST (divh) },
-  { TYPE (INSN_JC), IDX (INSN_JC), IDX (INSN_PAR_JC), IDX (INSN_WRITE_JC), FULL (jc) FAST (jc) },
-  { TYPE (INSN_JNC), IDX (INSN_JNC), IDX (INSN_PAR_JNC), IDX (INSN_WRITE_JNC), FULL (jnc) FAST (jnc) },
-  { TYPE (INSN_JL), IDX (INSN_JL), IDX (INSN_PAR_JL), IDX (INSN_WRITE_JL), FULL (jl) FAST (jl) },
-  { TYPE (INSN_JMP), IDX (INSN_JMP), IDX (INSN_PAR_JMP), IDX (INSN_WRITE_JMP), FULL (jmp) FAST (jmp) },
-  { TYPE (INSN_LD), IDX (INSN_LD), IDX (INSN_PAR_LD), IDX (INSN_WRITE_LD), FULL (ld) FAST (ld) },
-  { TYPE (INSN_LD_D), IDX (INSN_LD_D), NOPAR, NOPAR, FULL (ld_d) FAST (ld_d) },
-  { TYPE (INSN_LDB), IDX (INSN_LDB), IDX (INSN_PAR_LDB), IDX (INSN_WRITE_LDB), FULL (ldb) FAST (ldb) },
-  { TYPE (INSN_LDB_D), IDX (INSN_LDB_D), NOPAR, NOPAR, FULL (ldb_d) FAST (ldb_d) },
-  { TYPE (INSN_LDH), IDX (INSN_LDH), IDX (INSN_PAR_LDH), IDX (INSN_WRITE_LDH), FULL (ldh) FAST (ldh) },
-  { TYPE (INSN_LDH_D), IDX (INSN_LDH_D), NOPAR, NOPAR, FULL (ldh_d) FAST (ldh_d) },
-  { TYPE (INSN_LDUB), IDX (INSN_LDUB), IDX (INSN_PAR_LDUB), IDX (INSN_WRITE_LDUB), FULL (ldub) FAST (ldub) },
-  { TYPE (INSN_LDUB_D), IDX (INSN_LDUB_D), NOPAR, NOPAR, FULL (ldub_d) FAST (ldub_d) },
-  { TYPE (INSN_LDUH), IDX (INSN_LDUH), IDX (INSN_PAR_LDUH), IDX (INSN_WRITE_LDUH), FULL (lduh) FAST (lduh) },
-  { TYPE (INSN_LDUH_D), IDX (INSN_LDUH_D), NOPAR, NOPAR, FULL (lduh_d) FAST (lduh_d) },
-  { TYPE (INSN_LD_PLUS), IDX (INSN_LD_PLUS), IDX (INSN_PAR_LD_PLUS), IDX (INSN_WRITE_LD_PLUS), FULL (ld_plus) FAST (ld_plus) },
-  { TYPE (INSN_LD24), IDX (INSN_LD24), NOPAR, NOPAR, FULL (ld24) FAST (ld24) },
-  { TYPE (INSN_LDI8), IDX (INSN_LDI8), IDX (INSN_PAR_LDI8), IDX (INSN_WRITE_LDI8), FULL (ldi8) FAST (ldi8) },
-  { TYPE (INSN_LDI16), IDX (INSN_LDI16), NOPAR, NOPAR, FULL (ldi16) FAST (ldi16) },
-  { TYPE (INSN_LOCK), IDX (INSN_LOCK), IDX (INSN_PAR_LOCK), IDX (INSN_WRITE_LOCK), FULL (lock) FAST (lock) },
-  { TYPE (INSN_MACHI_A), IDX (INSN_MACHI_A), IDX (INSN_PAR_MACHI_A), IDX (INSN_WRITE_MACHI_A), FULL (machi_a) FAST (machi_a) },
-  { TYPE (INSN_MACLO_A), IDX (INSN_MACLO_A), IDX (INSN_PAR_MACLO_A), IDX (INSN_WRITE_MACLO_A), FULL (maclo_a) FAST (maclo_a) },
-  { TYPE (INSN_MACWHI_A), IDX (INSN_MACWHI_A), IDX (INSN_PAR_MACWHI_A), IDX (INSN_WRITE_MACWHI_A), FULL (macwhi_a) FAST (macwhi_a) },
-  { TYPE (INSN_MACWLO_A), IDX (INSN_MACWLO_A), IDX (INSN_PAR_MACWLO_A), IDX (INSN_WRITE_MACWLO_A), FULL (macwlo_a) FAST (macwlo_a) },
-  { TYPE (INSN_MUL), IDX (INSN_MUL), IDX (INSN_PAR_MUL), IDX (INSN_WRITE_MUL), FULL (mul) FAST (mul) },
-  { TYPE (INSN_MULHI_A), IDX (INSN_MULHI_A), IDX (INSN_PAR_MULHI_A), IDX (INSN_WRITE_MULHI_A), FULL (mulhi_a) FAST (mulhi_a) },
-  { TYPE (INSN_MULLO_A), IDX (INSN_MULLO_A), IDX (INSN_PAR_MULLO_A), IDX (INSN_WRITE_MULLO_A), FULL (mullo_a) FAST (mullo_a) },
-  { TYPE (INSN_MULWHI_A), IDX (INSN_MULWHI_A), IDX (INSN_PAR_MULWHI_A), IDX (INSN_WRITE_MULWHI_A), FULL (mulwhi_a) FAST (mulwhi_a) },
-  { TYPE (INSN_MULWLO_A), IDX (INSN_MULWLO_A), IDX (INSN_PAR_MULWLO_A), IDX (INSN_WRITE_MULWLO_A), FULL (mulwlo_a) FAST (mulwlo_a) },
-  { TYPE (INSN_MV), IDX (INSN_MV), IDX (INSN_PAR_MV), IDX (INSN_WRITE_MV), FULL (mv) FAST (mv) },
-  { TYPE (INSN_MVFACHI_A), IDX (INSN_MVFACHI_A), IDX (INSN_PAR_MVFACHI_A), IDX (INSN_WRITE_MVFACHI_A), FULL (mvfachi_a) FAST (mvfachi_a) },
-  { TYPE (INSN_MVFACLO_A), IDX (INSN_MVFACLO_A), IDX (INSN_PAR_MVFACLO_A), IDX (INSN_WRITE_MVFACLO_A), FULL (mvfaclo_a) FAST (mvfaclo_a) },
-  { TYPE (INSN_MVFACMI_A), IDX (INSN_MVFACMI_A), IDX (INSN_PAR_MVFACMI_A), IDX (INSN_WRITE_MVFACMI_A), FULL (mvfacmi_a) FAST (mvfacmi_a) },
-  { TYPE (INSN_MVFC), IDX (INSN_MVFC), IDX (INSN_PAR_MVFC), IDX (INSN_WRITE_MVFC), FULL (mvfc) FAST (mvfc) },
-  { TYPE (INSN_MVTACHI_A), IDX (INSN_MVTACHI_A), IDX (INSN_PAR_MVTACHI_A), IDX (INSN_WRITE_MVTACHI_A), FULL (mvtachi_a) FAST (mvtachi_a) },
-  { TYPE (INSN_MVTACLO_A), IDX (INSN_MVTACLO_A), IDX (INSN_PAR_MVTACLO_A), IDX (INSN_WRITE_MVTACLO_A), FULL (mvtaclo_a) FAST (mvtaclo_a) },
-  { TYPE (INSN_MVTC), IDX (INSN_MVTC), IDX (INSN_PAR_MVTC), IDX (INSN_WRITE_MVTC), FULL (mvtc) FAST (mvtc) },
-  { TYPE (INSN_NEG), IDX (INSN_NEG), IDX (INSN_PAR_NEG), IDX (INSN_WRITE_NEG), FULL (neg) FAST (neg) },
-  { TYPE (INSN_NOP), IDX (INSN_NOP), IDX (INSN_PAR_NOP), IDX (INSN_WRITE_NOP), FULL (nop) FAST (nop) },
-  { TYPE (INSN_NOT), IDX (INSN_NOT), IDX (INSN_PAR_NOT), IDX (INSN_WRITE_NOT), FULL (not) FAST (not) },
-  { TYPE (INSN_RAC_DSI), IDX (INSN_RAC_DSI), IDX (INSN_PAR_RAC_DSI), IDX (INSN_WRITE_RAC_DSI), FULL (rac_dsi) FAST (rac_dsi) },
-  { TYPE (INSN_RACH_DSI), IDX (INSN_RACH_DSI), IDX (INSN_PAR_RACH_DSI), IDX (INSN_WRITE_RACH_DSI), FULL (rach_dsi) FAST (rach_dsi) },
-  { TYPE (INSN_RTE), IDX (INSN_RTE), IDX (INSN_PAR_RTE), IDX (INSN_WRITE_RTE), FULL (rte) FAST (rte) },
-  { TYPE (INSN_SETH), IDX (INSN_SETH), NOPAR, NOPAR, FULL (seth) FAST (seth) },
-  { TYPE (INSN_SLL), IDX (INSN_SLL), IDX (INSN_PAR_SLL), IDX (INSN_WRITE_SLL), FULL (sll) FAST (sll) },
-  { TYPE (INSN_SLL3), IDX (INSN_SLL3), NOPAR, NOPAR, FULL (sll3) FAST (sll3) },
-  { TYPE (INSN_SLLI), IDX (INSN_SLLI), IDX (INSN_PAR_SLLI), IDX (INSN_WRITE_SLLI), FULL (slli) FAST (slli) },
-  { TYPE (INSN_SRA), IDX (INSN_SRA), IDX (INSN_PAR_SRA), IDX (INSN_WRITE_SRA), FULL (sra) FAST (sra) },
-  { TYPE (INSN_SRA3), IDX (INSN_SRA3), NOPAR, NOPAR, FULL (sra3) FAST (sra3) },
-  { TYPE (INSN_SRAI), IDX (INSN_SRAI), IDX (INSN_PAR_SRAI), IDX (INSN_WRITE_SRAI), FULL (srai) FAST (srai) },
-  { TYPE (INSN_SRL), IDX (INSN_SRL), IDX (INSN_PAR_SRL), IDX (INSN_WRITE_SRL), FULL (srl) FAST (srl) },
-  { TYPE (INSN_SRL3), IDX (INSN_SRL3), NOPAR, NOPAR, FULL (srl3) FAST (srl3) },
-  { TYPE (INSN_SRLI), IDX (INSN_SRLI), IDX (INSN_PAR_SRLI), IDX (INSN_WRITE_SRLI), FULL (srli) FAST (srli) },
-  { TYPE (INSN_ST), IDX (INSN_ST), IDX (INSN_PAR_ST), IDX (INSN_WRITE_ST), FULL (st) FAST (st) },
-  { TYPE (INSN_ST_D), IDX (INSN_ST_D), NOPAR, NOPAR, FULL (st_d) FAST (st_d) },
-  { TYPE (INSN_STB), IDX (INSN_STB), IDX (INSN_PAR_STB), IDX (INSN_WRITE_STB), FULL (stb) FAST (stb) },
-  { TYPE (INSN_STB_D), IDX (INSN_STB_D), NOPAR, NOPAR, FULL (stb_d) FAST (stb_d) },
-  { TYPE (INSN_STH), IDX (INSN_STH), IDX (INSN_PAR_STH), IDX (INSN_WRITE_STH), FULL (sth) FAST (sth) },
-  { TYPE (INSN_STH_D), IDX (INSN_STH_D), NOPAR, NOPAR, FULL (sth_d) FAST (sth_d) },
-  { TYPE (INSN_ST_PLUS), IDX (INSN_ST_PLUS), IDX (INSN_PAR_ST_PLUS), IDX (INSN_WRITE_ST_PLUS), FULL (st_plus) FAST (st_plus) },
-  { TYPE (INSN_ST_MINUS), IDX (INSN_ST_MINUS), IDX (INSN_PAR_ST_MINUS), IDX (INSN_WRITE_ST_MINUS), FULL (st_minus) FAST (st_minus) },
-  { TYPE (INSN_SUB), IDX (INSN_SUB), IDX (INSN_PAR_SUB), IDX (INSN_WRITE_SUB), FULL (sub) FAST (sub) },
-  { TYPE (INSN_SUBV), IDX (INSN_SUBV), IDX (INSN_PAR_SUBV), IDX (INSN_WRITE_SUBV), FULL (subv) FAST (subv) },
-  { TYPE (INSN_SUBX), IDX (INSN_SUBX), IDX (INSN_PAR_SUBX), IDX (INSN_WRITE_SUBX), FULL (subx) FAST (subx) },
-  { TYPE (INSN_TRAP), IDX (INSN_TRAP), IDX (INSN_PAR_TRAP), IDX (INSN_WRITE_TRAP), FULL (trap) FAST (trap) },
-  { TYPE (INSN_UNLOCK), IDX (INSN_UNLOCK), IDX (INSN_PAR_UNLOCK), IDX (INSN_WRITE_UNLOCK), FULL (unlock) FAST (unlock) },
-  { TYPE (INSN_SATB), IDX (INSN_SATB), NOPAR, NOPAR, FULL (satb) FAST (satb) },
-  { TYPE (INSN_SATH), IDX (INSN_SATH), NOPAR, NOPAR, FULL (sath) FAST (sath) },
-  { TYPE (INSN_SAT), IDX (INSN_SAT), NOPAR, NOPAR, FULL (sat) FAST (sat) },
-  { TYPE (INSN_PCMPBZ), IDX (INSN_PCMPBZ), IDX (INSN_PAR_PCMPBZ), IDX (INSN_WRITE_PCMPBZ), FULL (pcmpbz) FAST (pcmpbz) },
-  { TYPE (INSN_SADD), IDX (INSN_SADD), IDX (INSN_PAR_SADD), IDX (INSN_WRITE_SADD), FULL (sadd) FAST (sadd) },
-  { TYPE (INSN_MACWU1), IDX (INSN_MACWU1), IDX (INSN_PAR_MACWU1), IDX (INSN_WRITE_MACWU1), FULL (macwu1) FAST (macwu1) },
-  { TYPE (INSN_MSBLO), IDX (INSN_MSBLO), IDX (INSN_PAR_MSBLO), IDX (INSN_WRITE_MSBLO), FULL (msblo) FAST (msblo) },
-  { TYPE (INSN_MULWU1), IDX (INSN_MULWU1), IDX (INSN_PAR_MULWU1), IDX (INSN_WRITE_MULWU1), FULL (mulwu1) FAST (mulwu1) },
-  { TYPE (INSN_MACLH1), IDX (INSN_MACLH1), IDX (INSN_PAR_MACLH1), IDX (INSN_WRITE_MACLH1), FULL (maclh1) FAST (maclh1) },
-  { TYPE (INSN_SC), IDX (INSN_SC), IDX (INSN_PAR_SC), IDX (INSN_WRITE_SC), FULL (sc) FAST (sc) },
-  { TYPE (INSN_SNC), IDX (INSN_SNC), IDX (INSN_PAR_SNC), IDX (INSN_WRITE_SNC), FULL (snc) FAST (snc) },
-};
-
-static const struct insn_sem m32rxf_insn_sem_invalid =
-{
-  VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), IDX (INSN_X_INVALID), 0 /*unused*/, FULL (x_invalid) FAST (x_invalid)
-};
-
-#undef IDX
-#undef TYPE
-
-/* Initialize an IDESC from the compile-time computable parts.  */
-
-static INLINE void
-init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
-{
-  const CGEN_INSN *opcode_table = m32r_cgen_insn_table_entries;
-
-  id->num = t->index;
-  if ((int) t->type <= 0)
-    id->opcode = & cgen_virtual_opcode_table[- t->type];
-  else
-    id->opcode = & opcode_table[t->type];
-#if ! WITH_SEM_SWITCH_FULL
-  id->sem_full = t->sem_full;
-#endif
-#if WITH_FAST && ! WITH_SEM_SWITCH_FAST
-  id->sem_fast = t->sem_fast;
-#endif
-#if WITH_PROFILE_MODEL_P
-  id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];
-  {
-    SIM_DESC sd = CPU_STATE (cpu);
-    SIM_ASSERT (t->index == id->timing->num);
-  }
-#endif
-}
-
-/* Initialize the instruction descriptor table.  */
-
-void
-m32rxf_init_idesc_table (SIM_CPU *cpu)
-{
-  IDESC *id,*tabend;
-  const struct insn_sem *t,*tend;
-  int tabsize = M32RXF_INSN_MAX;
-  IDESC *table = m32rxf_insn_data;
-
-  memset (table, 0, tabsize * sizeof (IDESC));
-
-  /* First set all entries to the `invalid insn'.  */
-  t = & m32rxf_insn_sem_invalid;
-  for (id = table, tabend = table + tabsize; id < tabend; ++id)
-    init_idesc (cpu, id, t);
-
-  /* Now fill in the values for the chosen cpu.  */
-  for (t = m32rxf_insn_sem, tend = t + sizeof (m32rxf_insn_sem) / sizeof (*t);
-       t != tend; ++t)
-    {
-      init_idesc (cpu, & table[t->index], t);
-      if (t->par_index != NOPAR)
-	{
-	  init_idesc (cpu, &table[t->par_index], t);
-	  table[t->index].par_idesc = &table[t->par_index];
-	}
-      if (t->par_index != NOPAR)
-	{
-	  init_idesc (cpu, &table[t->write_index], t);
-	  table[t->par_index].par_idesc = &table[t->write_index];
-	}
-    }
-
-  /* Link the IDESC table into the cpu.  */
-  CPU_IDESC (cpu) = table;
-}
-
-/* Enum declaration for all instruction semantic formats.  */
-typedef enum sfmt {
-  FMT_EMPTY, FMT_ADD, FMT_ADD3, FMT_AND3
- , FMT_OR3, FMT_ADDI, FMT_ADDV, FMT_ADDV3
- , FMT_ADDX, FMT_BC8, FMT_BC24, FMT_BEQ
- , FMT_BEQZ, FMT_BL8, FMT_BL24, FMT_BCL8
- , FMT_BCL24, FMT_BRA8, FMT_BRA24, FMT_CMP
- , FMT_CMPI, FMT_CMPZ, FMT_DIV, FMT_JC
- , FMT_JL, FMT_JMP, FMT_LD, FMT_LD_D
- , FMT_LDB, FMT_LDB_D, FMT_LDH, FMT_LDH_D
- , FMT_LD_PLUS, FMT_LD24, FMT_LDI8, FMT_LDI16
- , FMT_LOCK, FMT_MACHI_A, FMT_MULHI_A, FMT_MV
- , FMT_MVFACHI_A, FMT_MVFC, FMT_MVTACHI_A, FMT_MVTC
- , FMT_NOP, FMT_RAC_DSI, FMT_RTE, FMT_SETH
- , FMT_SLL3, FMT_SLLI, FMT_ST, FMT_ST_D
- , FMT_STB, FMT_STB_D, FMT_STH, FMT_STH_D
- , FMT_ST_PLUS, FMT_TRAP, FMT_UNLOCK, FMT_SATB
- , FMT_SAT, FMT_SADD, FMT_MACWU1, FMT_MSBLO
- , FMT_MULWU1, FMT_SC
-} SFMT;
-
-/* The decoder uses this to record insns and direct extraction handling.  */
-
-typedef struct {
-  const IDESC *idesc;
-#ifdef __GNUC__
-  void *sfmt;
-#else
-  enum sfmt sfmt;
-#endif
-} DECODE_DESC;
-
-/* Macro to go from decode phase to extraction phase.  */
-
-#ifdef __GNUC__
-#define GOTO_EXTRACT(id) goto *(id)->sfmt
-#else
-#define GOTO_EXTRACT(id) goto extract
-#endif
-
-/* The decoder needs a slightly different computed goto switch control.  */
-#ifdef __GNUC__
-#define DECODE_SWITCH(N, X) goto *labels_##N[X];
-#else
-#define DECODE_SWITCH(N, X) switch (X)
-#endif
-
-/* Given an instruction, return a pointer to its IDESC entry.  */
-
-const IDESC *
-m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
-              CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn,
-              ARGBUF *abuf)
-{
-  /* Result of decoder, used by extractor.  */
-  const DECODE_DESC *idecode;
-
-  /* First decode the instruction.  */
-
-  {
-#define I(insn) & m32rxf_insn_data[CONCAT2 (M32RXF_,insn)]
-#ifdef __GNUC__
-#define E(fmt) && case_ex_##fmt
-#else
-#define E(fmt) fmt
-#endif
-    CGEN_INSN_INT insn = base_insn;
-    static const DECODE_DESC idecode_invalid = { I (INSN_X_INVALID), E (FMT_EMPTY) };
-
-    {
-#ifdef __GNUC__
-      static const void *labels_0[256] = {
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && case_0_7, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && case_0_28, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && case_0_87, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && case_0_95, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && case_0_112, && case_0_113, && case_0_114, && case_0_115, 
-        && case_0_116, && case_0_117, && case_0_118, && case_0_119, 
-        && case_0_120, && case_0_121, && case_0_122, && case_0_123, 
-        && case_0_124, && case_0_125, && case_0_126, && case_0_127, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && case_0_134, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && case_0_144, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && default_0, && default_0, && default_0, && default_0, 
-        && case_0_240, && case_0_241, && case_0_242, && case_0_243, 
-        && case_0_244, && case_0_245, && case_0_246, && case_0_247, 
-        && case_0_248, && case_0_249, && case_0_250, && case_0_251, 
-        && case_0_252, && case_0_253, && case_0_254, && case_0_255, 
-      };
-#endif
-      static const DECODE_DESC insns[256] = {
-        { I (INSN_SUBV), E (FMT_ADDV) }, { I (INSN_SUBX), E (FMT_ADDX) }, 
-        { I (INSN_SUB), E (FMT_ADD) }, { I (INSN_NEG), E (FMT_MV) }, 
-        { I (INSN_CMP), E (FMT_CMP) }, { I (INSN_CMPU), E (FMT_CMP) }, 
-        { I (INSN_CMPEQ), E (FMT_CMP) }, { 0 }, 
-        { I (INSN_ADDV), E (FMT_ADDV) }, { I (INSN_ADDX), E (FMT_ADDX) }, 
-        { I (INSN_ADD), E (FMT_ADD) }, { I (INSN_NOT), E (FMT_MV) }, 
-        { I (INSN_AND), E (FMT_ADD) }, { I (INSN_XOR), E (FMT_ADD) }, 
-        { I (INSN_OR), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_SRL), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_SRA), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_SLL), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_MUL), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_MV), E (FMT_MV) }, { I (INSN_MVFC), E (FMT_MVFC) }, 
-        { I (INSN_MVTC), E (FMT_MVTC) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { 0 }, { I (INSN_RTE), E (FMT_RTE) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_TRAP), E (FMT_TRAP) }, 
-        { I (INSN_STB), E (FMT_STB) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_STH), E (FMT_STH) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_ST), E (FMT_ST) }, { I (INSN_UNLOCK), E (FMT_UNLOCK) }, 
-        { I (INSN_ST_PLUS), E (FMT_ST_PLUS) }, { I (INSN_ST_MINUS), E (FMT_ST_PLUS) }, 
-        { I (INSN_LDB), E (FMT_LDB) }, { I (INSN_LDUB), E (FMT_LDB) }, 
-        { I (INSN_LDH), E (FMT_LDH) }, { I (INSN_LDUH), E (FMT_LDH) }, 
-        { I (INSN_LD), E (FMT_LD) }, { I (INSN_LOCK), E (FMT_LOCK) }, 
-        { I (INSN_LD_PLUS), E (FMT_LD_PLUS) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_MULHI_A), E (FMT_MULHI_A) }, { I (INSN_MULLO_A), E (FMT_MULHI_A) }, 
-        { I (INSN_MULWHI_A), E (FMT_MULHI_A) }, { I (INSN_MULWLO_A), E (FMT_MULHI_A) }, 
-        { I (INSN_MACHI_A), E (FMT_MACHI_A) }, { I (INSN_MACLO_A), E (FMT_MACHI_A) }, 
-        { I (INSN_MACWHI_A), E (FMT_MACHI_A) }, { I (INSN_MACWLO_A), E (FMT_MACHI_A) }, 
-        { I (INSN_MULHI_A), E (FMT_MULHI_A) }, { I (INSN_MULLO_A), E (FMT_MULHI_A) }, 
-        { I (INSN_MULWHI_A), E (FMT_MULHI_A) }, { I (INSN_MULWLO_A), E (FMT_MULHI_A) }, 
-        { I (INSN_MACHI_A), E (FMT_MACHI_A) }, { I (INSN_MACLO_A), E (FMT_MACHI_A) }, 
-        { I (INSN_MACWHI_A), E (FMT_MACHI_A) }, { I (INSN_MACWLO_A), E (FMT_MACHI_A) }, 
-        { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, 
-        { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, 
-        { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, 
-        { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, 
-        { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, 
-        { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, 
-        { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, 
-        { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) }, 
-        { I (INSN_SRLI), E (FMT_SLLI) }, { I (INSN_SRLI), E (FMT_SLLI) }, 
-        { I (INSN_SRAI), E (FMT_SLLI) }, { I (INSN_SRAI), E (FMT_SLLI) }, 
-        { I (INSN_SLLI), E (FMT_SLLI) }, { I (INSN_SLLI), E (FMT_SLLI) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { 0 }, 
-        { I (INSN_RACH_DSI), E (FMT_RAC_DSI) }, { I (INSN_RAC_DSI), E (FMT_RAC_DSI) }, 
-        { I (INSN_MULWU1), E (FMT_MULWU1) }, { I (INSN_MACWU1), E (FMT_MACWU1) }, 
-        { I (INSN_MACLH1), E (FMT_MACWU1) }, { I (INSN_MSBLO), E (FMT_MSBLO) }, 
-        { I (INSN_SADD), E (FMT_SADD) }, { 0 }, 
-        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
-        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
-        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
-        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
-        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
-        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
-        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
-        { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_CMPI), E (FMT_CMPI) }, { I (INSN_CMPUI), E (FMT_CMPI) }, 
-        { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_ADDV3), E (FMT_ADDV3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_ADD3), E (FMT_ADD3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_AND3), E (FMT_AND3) }, { I (INSN_XOR3), E (FMT_AND3) }, 
-        { I (INSN_OR3), E (FMT_OR3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { 0 }, { I (INSN_DIVU), E (FMT_DIV) }, 
-        { I (INSN_REM), E (FMT_DIV) }, { I (INSN_REMU), E (FMT_DIV) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_SRL3), E (FMT_SLL3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_SRA3), E (FMT_SLL3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_SLL3), E (FMT_SLL3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LDI16), E (FMT_LDI16) }, 
-        { I (INSN_STB_D), E (FMT_STB_D) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_STH_D), E (FMT_STH_D) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_ST_D), E (FMT_ST_D) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_LDB_D), E (FMT_LDB_D) }, { I (INSN_LDUB_D), E (FMT_LDB_D) }, 
-        { I (INSN_LDH_D), E (FMT_LDH_D) }, { I (INSN_LDUH_D), E (FMT_LDH_D) }, 
-        { I (INSN_LD_D), E (FMT_LD_D) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_BEQ), E (FMT_BEQ) }, { I (INSN_BNE), E (FMT_BEQ) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_BEQZ), E (FMT_BEQZ) }, { I (INSN_BNEZ), E (FMT_BEQZ) }, 
-        { I (INSN_BLTZ), E (FMT_BEQZ) }, { I (INSN_BGEZ), E (FMT_BEQZ) }, 
-        { I (INSN_BLEZ), E (FMT_BEQZ) }, { I (INSN_BGTZ), E (FMT_BEQZ) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_SETH), E (FMT_SETH) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-        { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, 
-        { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, 
-        { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, 
-        { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, 
-        { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, 
-        { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, 
-        { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, 
-        { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-        { 0 }, { 0 }, 
-      };
-      unsigned int val;
-      val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
-      DECODE_SWITCH (0, val)
-        {
-        CASE (0, 7) :
-          {
-            static const DECODE_DESC insns[16] = {
-              { I (INSN_CMPZ), E (FMT_CMPZ) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_PCMPBZ), E (FMT_CMPZ) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-            };
-            unsigned int val = (((insn >> 8) & (15 << 0)));
-            idecode = &insns[val];
-            GOTO_EXTRACT (idecode);
-          }
-        CASE (0, 28) :
-          {
-            static const DECODE_DESC insns[16] = {
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_JC), E (FMT_JC) }, { I (INSN_JNC), E (FMT_JC) }, 
-              { I (INSN_JL), E (FMT_JL) }, { I (INSN_JMP), E (FMT_JMP) }, 
-            };
-            unsigned int val = (((insn >> 8) & (15 << 0)));
-            idecode = &insns[val];
-            GOTO_EXTRACT (idecode);
-          }
-        CASE (0, 87) :
-          {
-            static const DECODE_DESC insns[4] = {
-              { I (INSN_MVTACHI_A), E (FMT_MVTACHI_A) }, { I (INSN_MVTACLO_A), E (FMT_MVTACHI_A) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-            };
-            unsigned int val = (((insn >> 0) & (3 << 0)));
-            idecode = &insns[val];
-            GOTO_EXTRACT (idecode);
-          }
-        CASE (0, 95) :
-          {
-            static const DECODE_DESC insns[4] = {
-              { I (INSN_MVFACHI_A), E (FMT_MVFACHI_A) }, { I (INSN_MVFACLO_A), E (FMT_MVFACHI_A) }, 
-              { I (INSN_MVFACMI_A), E (FMT_MVFACHI_A) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-            };
-            unsigned int val = (((insn >> 0) & (3 << 0)));
-            idecode = &insns[val];
-            GOTO_EXTRACT (idecode);
-          }
-        CASE (0, 112) :
-          {
-            static const DECODE_DESC insns[16] = {
-              { I (INSN_NOP), E (FMT_NOP) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_SC), E (FMT_SC) }, { I (INSN_SNC), E (FMT_SC) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_BCL8), E (FMT_BCL8) }, { I (INSN_BNCL8), E (FMT_BCL8) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_BC8), E (FMT_BC8) }, { I (INSN_BNC8), E (FMT_BC8) }, 
-              { I (INSN_BL8), E (FMT_BL8) }, { I (INSN_BRA8), E (FMT_BRA8) }, 
-            };
-            unsigned int val = (((insn >> 8) & (15 << 0)));
-            idecode = &insns[val];
-            GOTO_EXTRACT (idecode);
-          }
-        CASE (0, 113) : /* fall through */
-        CASE (0, 114) : /* fall through */
-        CASE (0, 115) : /* fall through */
-        CASE (0, 116) : /* fall through */
-        CASE (0, 117) : /* fall through */
-        CASE (0, 118) : /* fall through */
-        CASE (0, 119) : /* fall through */
-        CASE (0, 120) : /* fall through */
-        CASE (0, 121) : /* fall through */
-        CASE (0, 122) : /* fall through */
-        CASE (0, 123) : /* fall through */
-        CASE (0, 124) : /* fall through */
-        CASE (0, 125) : /* fall through */
-        CASE (0, 126) : /* fall through */
-        CASE (0, 127) :
-          {
-            static const DECODE_DESC insns[16] = {
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_BCL8), E (FMT_BCL8) }, { I (INSN_BNCL8), E (FMT_BCL8) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_BC8), E (FMT_BC8) }, { I (INSN_BNC8), E (FMT_BC8) }, 
-              { I (INSN_BL8), E (FMT_BL8) }, { I (INSN_BRA8), E (FMT_BRA8) }, 
-            };
-            unsigned int val = (((insn >> 8) & (15 << 0)));
-            idecode = &insns[val];
-            GOTO_EXTRACT (idecode);
-          }
-        CASE (0, 134) :
-          {
-#ifdef __GNUC__
-            static const void *labels_0_134[16] = {
-              && case_0_134_0, && default_0_134, && default_0_134, && default_0_134, 
-              && default_0_134, && default_0_134, && default_0_134, && default_0_134, 
-              && default_0_134, && default_0_134, && default_0_134, && default_0_134, 
-              && default_0_134, && default_0_134, && default_0_134, && default_0_134, 
-            };
-#endif
-            static const DECODE_DESC insns[16] = {
-              { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-            };
-            unsigned int val;
-            /* Must fetch more bits.  */
-            insn = GETIMEMUHI (current_cpu, pc + 2);
-            val = (((insn >> 12) & (15 << 0)));
-            DECODE_SWITCH (0_134, val)
-              {
-              CASE (0_134, 0) :
-                {
-                  static const DECODE_DESC insns[16] = {
-                    { I (INSN_SAT), E (FMT_SAT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-                    { I (INSN_SATH), E (FMT_SATB) }, { I (INSN_SATB), E (FMT_SATB) }, 
-                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-                  };
-                  unsigned int val = (((insn >> 8) & (15 << 0)));
-                  idecode = &insns[val];
-                  GOTO_EXTRACT (idecode);
-                }
-              DEFAULT (0_134) :
-                idecode = &insns[val];
-                GOTO_EXTRACT (idecode);
-              }
-            ENDSWITCH (0_134)
-          }
-        CASE (0, 144) :
-          {
-#ifdef __GNUC__
-            static const void *labels_0_144[16] = {
-              && case_0_144_0, && default_0_144, && default_0_144, && default_0_144, 
-              && default_0_144, && default_0_144, && default_0_144, && default_0_144, 
-              && default_0_144, && default_0_144, && default_0_144, && default_0_144, 
-              && default_0_144, && default_0_144, && default_0_144, && default_0_144, 
-            };
-#endif
-            static const DECODE_DESC insns[16] = {
-              { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-            };
-            unsigned int val;
-            /* Must fetch more bits.  */
-            insn = GETIMEMUHI (current_cpu, pc + 2);
-            val = (((insn >> 12) & (15 << 0)));
-            DECODE_SWITCH (0_144, val)
-              {
-              CASE (0_144, 0) :
-                {
-#ifdef __GNUC__
-                  static const void *labels_0_144_0[16] = {
-                    && case_0_144_0_0, && default_0_144_0, && default_0_144_0, && default_0_144_0, 
-                    && default_0_144_0, && default_0_144_0, && default_0_144_0, && default_0_144_0, 
-                    && default_0_144_0, && default_0_144_0, && default_0_144_0, && default_0_144_0, 
-                    && default_0_144_0, && default_0_144_0, && default_0_144_0, && default_0_144_0, 
-                  };
-#endif
-                  static const DECODE_DESC insns[16] = {
-                    { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-                    { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-                  };
-                  unsigned int val;
-                  val = (((insn >> 8) & (15 << 0)));
-                  DECODE_SWITCH (0_144_0, val)
-                    {
-                    CASE (0_144_0, 0) :
-                      {
-                        static const DECODE_DESC insns[16] = {
-                          { I (INSN_DIV), E (FMT_DIV) }, { I (INSN_DIVH), E (FMT_DIV) }, 
-                          { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-                          { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-                          { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-                          { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-                          { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-                          { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-                          { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-                        };
-                        unsigned int val = (((insn >> 4) & (15 << 0)));
-                        idecode = &insns[val];
-                        GOTO_EXTRACT (idecode);
-                      }
-                    DEFAULT (0_144_0) :
-                      idecode = &insns[val];
-                      GOTO_EXTRACT (idecode);
-                    }
-                  ENDSWITCH (0_144_0)
-                }
-              DEFAULT (0_144) :
-                idecode = &insns[val];
-                GOTO_EXTRACT (idecode);
-              }
-            ENDSWITCH (0_144)
-          }
-        CASE (0, 240) : /* fall through */
-        CASE (0, 241) : /* fall through */
-        CASE (0, 242) : /* fall through */
-        CASE (0, 243) : /* fall through */
-        CASE (0, 244) : /* fall through */
-        CASE (0, 245) : /* fall through */
-        CASE (0, 246) : /* fall through */
-        CASE (0, 247) : /* fall through */
-        CASE (0, 248) : /* fall through */
-        CASE (0, 249) : /* fall through */
-        CASE (0, 250) : /* fall through */
-        CASE (0, 251) : /* fall through */
-        CASE (0, 252) : /* fall through */
-        CASE (0, 253) : /* fall through */
-        CASE (0, 254) : /* fall through */
-        CASE (0, 255) :
-          {
-            static const DECODE_DESC insns[16] = {
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_BCL24), E (FMT_BCL24) }, { I (INSN_BNCL24), E (FMT_BCL24) }, 
-              { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, 
-              { I (INSN_BC24), E (FMT_BC24) }, { I (INSN_BNC24), E (FMT_BC24) }, 
-              { I (INSN_BL24), E (FMT_BL24) }, { I (INSN_BRA24), E (FMT_BRA24) }, 
-            };
-            unsigned int val = (((insn >> 8) & (15 << 0)));
-            idecode = &insns[val];
-            GOTO_EXTRACT (idecode);
-          }
-        DEFAULT (0) :
-          idecode = &insns[val];
-          GOTO_EXTRACT (idecode);
-        }
-      ENDSWITCH (0)
-    }
-#undef I
-#undef E
-  }
-
-  /* The instruction has been decoded, now extract the fields.  */
-
- extract:
-  {
-#ifndef __GNUC__
-    switch (idecode->sfmt)
-#endif
-      {
-
-  CASE (ex, FMT_EMPTY) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_empty.f
-  EXTRACT_IFMT_EMPTY_VARS /* */
-
-  EXTRACT_IFMT_EMPTY_CODE
-
-  /* Record the fields for the semantic handler.  */
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_empty", (char *) 0));
-
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_ADD) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_add.f
-  EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_IFMT_ADD_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_add", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_dr) = f_r1;
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_ADD3) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_add3.f
-  EXTRACT_IFMT_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
-
-  EXTRACT_IFMT_ADD3_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_add3", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_AND3) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_and3.f
-  EXTRACT_IFMT_AND3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
-
-  EXTRACT_IFMT_AND3_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_uimm16) = f_uimm16;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_and3", "f_uimm16 0x%x", 'x', f_uimm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_OR3) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_or3.f
-  EXTRACT_IFMT_OR3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
-
-  EXTRACT_IFMT_OR3_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_uimm16) = f_uimm16;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_or3", "f_uimm16 0x%x", 'x', f_uimm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_ADDI) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_addi.f
-  EXTRACT_IFMT_ADDI_VARS /* f-op1 f-r1 f-simm8 */
-
-  EXTRACT_IFMT_ADDI_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm8) = f_simm8;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addi", "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_dr) = f_r1;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_ADDV) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_addv.f
-  EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_IFMT_ADD_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addv", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_dr) = f_r1;
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_ADDV3) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_addv3.f
-  EXTRACT_IFMT_ADDV3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
-
-  EXTRACT_IFMT_ADDV3_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addv3", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_ADDX) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_addx.f
-  EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_IFMT_ADD_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addx", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_dr) = f_r1;
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_BC8) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
-  EXTRACT_IFMT_BC8_VARS /* f-op1 f-r1 f-disp8 */
-
-  EXTRACT_IFMT_BC8_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_disp8) = f_disp8;
-  SEM_BRANCH_INIT_EXTRACT (abuf);
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_BC24) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
-  EXTRACT_IFMT_BC24_VARS /* f-op1 f-r1 f-disp24 */
-
-  EXTRACT_IFMT_BC24_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_disp24) = f_disp24;
-  SEM_BRANCH_INIT_EXTRACT (abuf);
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_BEQ) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.cti.fields.fmt_beq.f
-  EXTRACT_IFMT_BEQ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
-
-  EXTRACT_IFMT_BEQ_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_disp16) = f_disp16;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  SEM_BRANCH_INIT_EXTRACT (abuf);
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_beq", "disp16 0x%x", 'x', f_disp16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_BEQZ) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
-  EXTRACT_IFMT_BEQZ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
-
-  EXTRACT_IFMT_BEQZ_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_disp16) = f_disp16;
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  SEM_BRANCH_INIT_EXTRACT (abuf);
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_beqz", "disp16 0x%x", 'x', f_disp16, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_BL8) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.cti.fields.fmt_bl8.f
-  EXTRACT_IFMT_BC8_VARS /* f-op1 f-r1 f-disp8 */
-
-  EXTRACT_IFMT_BC8_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_disp8) = f_disp8;
-  SEM_BRANCH_INIT_EXTRACT (abuf);
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_h_gr_14) = 14;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_BL24) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.cti.fields.fmt_bl24.f
-  EXTRACT_IFMT_BC24_VARS /* f-op1 f-r1 f-disp24 */
-
-  EXTRACT_IFMT_BC24_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_disp24) = f_disp24;
-  SEM_BRANCH_INIT_EXTRACT (abuf);
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_h_gr_14) = 14;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_BCL8) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.cti.fields.fmt_bcl8.f
-  EXTRACT_IFMT_BC8_VARS /* f-op1 f-r1 f-disp8 */
-
-  EXTRACT_IFMT_BC8_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_disp8) = f_disp8;
-  SEM_BRANCH_INIT_EXTRACT (abuf);
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bcl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_h_gr_14) = 14;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_BCL24) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.cti.fields.fmt_bcl24.f
-  EXTRACT_IFMT_BC24_VARS /* f-op1 f-r1 f-disp24 */
-
-  EXTRACT_IFMT_BC24_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_disp24) = f_disp24;
-  SEM_BRANCH_INIT_EXTRACT (abuf);
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bcl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_h_gr_14) = 14;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_BRA8) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.cti.fields.fmt_bra8.f
-  EXTRACT_IFMT_BC8_VARS /* f-op1 f-r1 f-disp8 */
-
-  EXTRACT_IFMT_BC8_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_disp8) = f_disp8;
-  SEM_BRANCH_INIT_EXTRACT (abuf);
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_BRA24) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.cti.fields.fmt_bra24.f
-  EXTRACT_IFMT_BC24_VARS /* f-op1 f-r1 f-disp24 */
-
-  EXTRACT_IFMT_BC24_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_disp24) = f_disp24;
-  SEM_BRANCH_INIT_EXTRACT (abuf);
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_CMP) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_cmp.f
-  EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_IFMT_CMP_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmp", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_CMPI) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_cmpi.f
-  EXTRACT_IFMT_CMPI_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
-
-  EXTRACT_IFMT_CMPI_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpi", "f_simm16 0x%x", 'x', f_simm16, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_CMPZ) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_cmpz.f
-  EXTRACT_IFMT_CMPZ_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_IFMT_CMPZ_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpz", "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_DIV) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_div.f
-  EXTRACT_IFMT_DIV_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
-
-  EXTRACT_IFMT_DIV_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_div", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_dr) = f_r1;
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_JC) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.cti.fields.fmt_jc.f
-  EXTRACT_IFMT_JC_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_IFMT_JC_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  SEM_BRANCH_INIT_EXTRACT (abuf);
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_jc", "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_JL) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.cti.fields.fmt_jl.f
-  EXTRACT_IFMT_JC_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_IFMT_JC_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  SEM_BRANCH_INIT_EXTRACT (abuf);
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_jl", "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_h_gr_14) = 14;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_JMP) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
-  EXTRACT_IFMT_JC_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_IFMT_JC_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  SEM_BRANCH_INIT_EXTRACT (abuf);
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_jmp", "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_LD) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_ld.f
-  EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_IFMT_ADD_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_LD_D) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_ld_d.f
-  EXTRACT_IFMT_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
-
-  EXTRACT_IFMT_ADD3_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_d", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_LDB) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_ldb.f
-  EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_IFMT_ADD_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldb", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_LDB_D) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_ldb_d.f
-  EXTRACT_IFMT_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
-
-  EXTRACT_IFMT_ADD3_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldb_d", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_LDH) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_ldh.f
-  EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_IFMT_ADD_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldh", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_LDH_D) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_ldh_d.f
-  EXTRACT_IFMT_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
-
-  EXTRACT_IFMT_ADD3_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldh_d", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_LD_PLUS) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_ld_plus.f
-  EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_IFMT_ADD_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_plus", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-      FLD (out_sr) = f_r2;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_LD24) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_ld24.f
-  EXTRACT_IFMT_LD24_VARS /* f-op1 f-r1 f-uimm24 */
-
-  EXTRACT_IFMT_LD24_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_uimm24) = f_uimm24;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld24", "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_LDI8) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_ldi8.f
-  EXTRACT_IFMT_ADDI_VARS /* f-op1 f-r1 f-simm8 */
-
-  EXTRACT_IFMT_ADDI_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm8) = f_simm8;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldi8", "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_LDI16) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_ldi16.f
-  EXTRACT_IFMT_LDI16_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
-
-  EXTRACT_IFMT_LDI16_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldi16", "f_simm16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_LOCK) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_lock.f
-  EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_IFMT_ADD_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_lock", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_MACHI_A) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_machi_a.f
-  EXTRACT_IFMT_MACHI_A_VARS /* f-op1 f-r1 f-acc f-op23 f-r2 */
-
-  EXTRACT_IFMT_MACHI_A_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_acc) = f_acc;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_machi_a", "f_acc 0x%x", 'x', f_acc, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_MULHI_A) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_mulhi_a.f
-  EXTRACT_IFMT_MACHI_A_VARS /* f-op1 f-r1 f-acc f-op23 f-r2 */
-
-  EXTRACT_IFMT_MACHI_A_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_acc) = f_acc;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mulhi_a", "f_acc 0x%x", 'x', f_acc, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_MV) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_mv.f
-  EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_IFMT_ADD_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mv", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_MVFACHI_A) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_mvfachi_a.f
-  EXTRACT_IFMT_MVFACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
-
-  EXTRACT_IFMT_MVFACHI_A_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_accs) = f_accs;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mvfachi_a", "f_accs 0x%x", 'x', f_accs, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_MVFC) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_mvfc.f
-  EXTRACT_IFMT_MVFC_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_IFMT_MVFC_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mvfc", "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_MVTACHI_A) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_mvtachi_a.f
-  EXTRACT_IFMT_MVTACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
-
-  EXTRACT_IFMT_MVTACHI_A_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_accs) = f_accs;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mvtachi_a", "f_accs 0x%x", 'x', f_accs, "src1 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_MVTC) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_mvtc.f
-  EXTRACT_IFMT_MVTC_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_IFMT_MVTC_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mvtc", "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_NOP) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_nop.f
-  EXTRACT_IFMT_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_IFMT_NOP_CODE
-
-  /* Record the fields for the semantic handler.  */
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_nop", (char *) 0));
-
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_RAC_DSI) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_rac_dsi.f
-  EXTRACT_IFMT_RAC_DSI_VARS /* f-op1 f-accd f-bits67 f-op2 f-accs f-bit14 f-imm1 */
-
-  EXTRACT_IFMT_RAC_DSI_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_accs) = f_accs;
-  FLD (f_imm1) = f_imm1;
-  FLD (f_accd) = f_accd;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_rac_dsi", "f_accs 0x%x", 'x', f_accs, "f_imm1 0x%x", 'x', f_imm1, "f_accd 0x%x", 'x', f_accd, (char *) 0));
-
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_RTE) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.cti.fields.fmt_rte.f
-  EXTRACT_IFMT_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_IFMT_NOP_CODE
-
-  /* Record the fields for the semantic handler.  */
-  SEM_BRANCH_INIT_EXTRACT (abuf);
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_rte", (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_SETH) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_seth.f
-  EXTRACT_IFMT_SETH_VARS /* f-op1 f-r1 f-op2 f-r2 f-hi16 */
-
-  EXTRACT_IFMT_SETH_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_hi16) = f_hi16;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_seth", "f_hi16 0x%x", 'x', f_hi16, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_SLL3) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_sll3.f
-  EXTRACT_IFMT_ADDV3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
-
-  EXTRACT_IFMT_ADDV3_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_sll3", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_SLLI) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_slli.f
-  EXTRACT_IFMT_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */
-
-  EXTRACT_IFMT_SLLI_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_uimm5) = f_uimm5;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_slli", "f_uimm5 0x%x", 'x', f_uimm5, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_dr) = f_r1;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_ST) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_st.f
-  EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_IFMT_CMP_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_ST_D) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_st_d.f
-  EXTRACT_IFMT_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
-
-  EXTRACT_IFMT_ST_D_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_d", "f_simm16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_STB) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_stb.f
-  EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_IFMT_CMP_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stb", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_STB_D) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_stb_d.f
-  EXTRACT_IFMT_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
-
-  EXTRACT_IFMT_ST_D_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stb_d", "f_simm16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_STH) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_sth.f
-  EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_IFMT_CMP_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_sth", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_STH_D) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_sth_d.f
-  EXTRACT_IFMT_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
-
-  EXTRACT_IFMT_ST_D_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_sth_d", "f_simm16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_ST_PLUS) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_st_plus.f
-  EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_IFMT_CMP_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_plus", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-      FLD (out_src2) = f_r2;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_TRAP) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.cti.fields.fmt_trap.f
-  EXTRACT_IFMT_TRAP_VARS /* f-op1 f-r1 f-op2 f-uimm4 */
-
-  EXTRACT_IFMT_TRAP_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_uimm4) = f_uimm4;
-  SEM_BRANCH_INIT_EXTRACT (abuf);
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_trap", "f_uimm4 0x%x", 'x', f_uimm4, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_UNLOCK) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_unlock.f
-  EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_IFMT_CMP_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_unlock", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_SATB) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_satb.f
-  EXTRACT_IFMT_SATB_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
-
-  EXTRACT_IFMT_SATB_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_satb", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_SAT) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_sat.f
-  EXTRACT_IFMT_SATB_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
-
-  EXTRACT_IFMT_SATB_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_sat", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_SADD) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_sadd.f
-  EXTRACT_IFMT_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_IFMT_NOP_CODE
-
-  /* Record the fields for the semantic handler.  */
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_sadd", (char *) 0));
-
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_MACWU1) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_macwu1.f
-  EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_IFMT_CMP_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_macwu1", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_MSBLO) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_msblo.f
-  EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_IFMT_CMP_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_msblo", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_MULWU1) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_mulwu1.f
-  EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_IFMT_CMP_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mulwu1", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-  BREAK (ex);
-  }
-
-  CASE (ex, FMT_SC) :
-  {
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.cti.fields.fmt_sc.f
-  EXTRACT_IFMT_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_IFMT_NOP_CODE
-
-  /* Record the fields for the semantic handler.  */
-  SEM_BRANCH_INIT_EXTRACT (abuf);
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_sc", (char *) 0));
-
-#undef FLD
-  BREAK (ex);
-  }
-
-
-      }
-    ENDSWITCH (ex)
-
-  }
-
-  return idecode->idesc;
-}
diff --git a/sim/m32r/decodex.h b/sim/m32r/decodex.h
deleted file mode 100644
index 36ba4f1..0000000
--- a/sim/m32r/decodex.h
+++ /dev/null
@@ -1,566 +0,0 @@
-/* Decode header for m32rxf.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
-
-This file is part of the GNU Simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#ifndef M32RXF_DECODE_H
-#define M32RXF_DECODE_H
-
-/* Run-time computed instruction descriptor.  */
-
-struct idesc {
-  /* Pointer to parallel handler if serial insn.
-     Pointer to writeback handler if parallel insn.  */
-  struct idesc *par_idesc;
-
-#if WITH_SEM_SWITCH_FULL
-#ifdef __GNUC__
-  void *sem_full_lab;
-#endif
-#else
-  SEMANTIC_FN *sem_full;
-#endif
-
-#if WITH_SEM_SWITCH_FAST
-#ifdef __GNUC__
-  void *sem_fast_lab;
-#endif
-#else
-  SEMANTIC_FN *sem_fast;
-#endif
-
-  /* Instruction number (index in IDESC table, profile table).
-     Also used to switch on in non-gcc semantic switches.  */
-  int num;
-
-  /* opcode table data */
-  const CGEN_INSN *opcode;
-
-  /* profiling/modelling support */
-  const INSN_TIMING *timing;
-};
-
-extern const IDESC *m32rxf_decode (SIM_CPU *, IADDR,
-                                  CGEN_INSN_INT, CGEN_INSN_INT,
-                                  ARGBUF *);
-
-/* Enum declaration for instructions in cpu family m32rxf.  */
-typedef enum m32rxf_insn_type {
-  M32RXF_INSN_X_INVALID, M32RXF_INSN_X_AFTER, M32RXF_INSN_X_BEFORE, M32RXF_INSN_X_CTI_CHAIN
- , M32RXF_INSN_X_CHAIN, M32RXF_INSN_X_BEGIN, M32RXF_INSN_ADD, M32RXF_INSN_ADD3
- , M32RXF_INSN_AND, M32RXF_INSN_AND3, M32RXF_INSN_OR, M32RXF_INSN_OR3
- , M32RXF_INSN_XOR, M32RXF_INSN_XOR3, M32RXF_INSN_ADDI, M32RXF_INSN_ADDV
- , M32RXF_INSN_ADDV3, M32RXF_INSN_ADDX, M32RXF_INSN_BC8, M32RXF_INSN_BC24
- , M32RXF_INSN_BEQ, M32RXF_INSN_BEQZ, M32RXF_INSN_BGEZ, M32RXF_INSN_BGTZ
- , M32RXF_INSN_BLEZ, M32RXF_INSN_BLTZ, M32RXF_INSN_BNEZ, M32RXF_INSN_BL8
- , M32RXF_INSN_BL24
-/* start-sanitize-m32rx */
- , M32RXF_INSN_BCL8
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_BCL24
-/* end-sanitize-m32rx */
- , M32RXF_INSN_BNC8, M32RXF_INSN_BNC24, M32RXF_INSN_BNE, M32RXF_INSN_BRA8
- , M32RXF_INSN_BRA24
-/* start-sanitize-m32rx */
- , M32RXF_INSN_BNCL8
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_BNCL24
-/* end-sanitize-m32rx */
- , M32RXF_INSN_CMP, M32RXF_INSN_CMPI, M32RXF_INSN_CMPU, M32RXF_INSN_CMPUI
-/* start-sanitize-m32rx */
- , M32RXF_INSN_CMPEQ
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_CMPZ
-/* end-sanitize-m32rx */
- , M32RXF_INSN_DIV, M32RXF_INSN_DIVU, M32RXF_INSN_REM, M32RXF_INSN_REMU
-/* start-sanitize-m32rx */
- , M32RXF_INSN_DIVH
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_JC
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_JNC
-/* end-sanitize-m32rx */
- , M32RXF_INSN_JL, M32RXF_INSN_JMP, M32RXF_INSN_LD, M32RXF_INSN_LD_D
- , M32RXF_INSN_LDB, M32RXF_INSN_LDB_D, M32RXF_INSN_LDH, M32RXF_INSN_LDH_D
- , M32RXF_INSN_LDUB, M32RXF_INSN_LDUB_D, M32RXF_INSN_LDUH, M32RXF_INSN_LDUH_D
- , M32RXF_INSN_LD_PLUS, M32RXF_INSN_LD24, M32RXF_INSN_LDI8, M32RXF_INSN_LDI16
- , M32RXF_INSN_LOCK
-/* start-sanitize-m32rx */
- , M32RXF_INSN_MACHI_A
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_MACLO_A
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_MACWHI_A
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_MACWLO_A
-/* end-sanitize-m32rx */
- , M32RXF_INSN_MUL
-/* start-sanitize-m32rx */
- , M32RXF_INSN_MULHI_A
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_MULLO_A
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_MULWHI_A
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_MULWLO_A
-/* end-sanitize-m32rx */
- , M32RXF_INSN_MV
-/* start-sanitize-m32rx */
- , M32RXF_INSN_MVFACHI_A
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_MVFACLO_A
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_MVFACMI_A
-/* end-sanitize-m32rx */
- , M32RXF_INSN_MVFC
-/* start-sanitize-m32rx */
- , M32RXF_INSN_MVTACHI_A
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_MVTACLO_A
-/* end-sanitize-m32rx */
- , M32RXF_INSN_MVTC, M32RXF_INSN_NEG, M32RXF_INSN_NOP, M32RXF_INSN_NOT
-/* start-sanitize-m32rx */
- , M32RXF_INSN_RAC_DSI
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_RACH_DSI
-/* end-sanitize-m32rx */
- , M32RXF_INSN_RTE, M32RXF_INSN_SETH, M32RXF_INSN_SLL, M32RXF_INSN_SLL3
- , M32RXF_INSN_SLLI, M32RXF_INSN_SRA, M32RXF_INSN_SRA3, M32RXF_INSN_SRAI
- , M32RXF_INSN_SRL, M32RXF_INSN_SRL3, M32RXF_INSN_SRLI, M32RXF_INSN_ST
- , M32RXF_INSN_ST_D, M32RXF_INSN_STB, M32RXF_INSN_STB_D, M32RXF_INSN_STH
- , M32RXF_INSN_STH_D, M32RXF_INSN_ST_PLUS, M32RXF_INSN_ST_MINUS, M32RXF_INSN_SUB
- , M32RXF_INSN_SUBV, M32RXF_INSN_SUBX, M32RXF_INSN_TRAP, M32RXF_INSN_UNLOCK
-/* start-sanitize-m32rx */
- , M32RXF_INSN_SATB
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_SATH
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_SAT
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_PCMPBZ
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_SADD
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_MACWU1
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_MSBLO
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_MULWU1
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_MACLH1
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_SC
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_SNC
-/* end-sanitize-m32rx */
- , M32RXF_INSN_PAR_ADD, M32RXF_INSN_WRITE_ADD, M32RXF_INSN_PAR_AND, M32RXF_INSN_WRITE_AND
- , M32RXF_INSN_PAR_OR, M32RXF_INSN_WRITE_OR, M32RXF_INSN_PAR_XOR, M32RXF_INSN_WRITE_XOR
- , M32RXF_INSN_PAR_ADDI, M32RXF_INSN_WRITE_ADDI, M32RXF_INSN_PAR_ADDV, M32RXF_INSN_WRITE_ADDV
- , M32RXF_INSN_PAR_ADDX, M32RXF_INSN_WRITE_ADDX, M32RXF_INSN_PAR_BC8, M32RXF_INSN_WRITE_BC8
- , M32RXF_INSN_PAR_BL8, M32RXF_INSN_WRITE_BL8
-/* start-sanitize-m32rx */
- , M32RXF_INSN_PAR_BCL8
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_WRITE_BCL8
-/* end-sanitize-m32rx */
- , M32RXF_INSN_PAR_BNC8, M32RXF_INSN_WRITE_BNC8, M32RXF_INSN_PAR_BRA8, M32RXF_INSN_WRITE_BRA8
-/* start-sanitize-m32rx */
- , M32RXF_INSN_PAR_BNCL8
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_WRITE_BNCL8
-/* end-sanitize-m32rx */
- , M32RXF_INSN_PAR_CMP, M32RXF_INSN_WRITE_CMP, M32RXF_INSN_PAR_CMPU, M32RXF_INSN_WRITE_CMPU
-/* start-sanitize-m32rx */
- , M32RXF_INSN_PAR_CMPEQ
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_WRITE_CMPEQ
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_PAR_CMPZ
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_WRITE_CMPZ
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_PAR_JC
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_WRITE_JC
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_PAR_JNC
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_WRITE_JNC
-/* end-sanitize-m32rx */
- , M32RXF_INSN_PAR_JL, M32RXF_INSN_WRITE_JL, M32RXF_INSN_PAR_JMP, M32RXF_INSN_WRITE_JMP
- , M32RXF_INSN_PAR_LD, M32RXF_INSN_WRITE_LD, M32RXF_INSN_PAR_LDB, M32RXF_INSN_WRITE_LDB
- , M32RXF_INSN_PAR_LDH, M32RXF_INSN_WRITE_LDH, M32RXF_INSN_PAR_LDUB, M32RXF_INSN_WRITE_LDUB
- , M32RXF_INSN_PAR_LDUH, M32RXF_INSN_WRITE_LDUH, M32RXF_INSN_PAR_LD_PLUS, M32RXF_INSN_WRITE_LD_PLUS
- , M32RXF_INSN_PAR_LDI8, M32RXF_INSN_WRITE_LDI8, M32RXF_INSN_PAR_LOCK, M32RXF_INSN_WRITE_LOCK
-/* start-sanitize-m32rx */
- , M32RXF_INSN_PAR_MACHI_A
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_WRITE_MACHI_A
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_PAR_MACLO_A
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_WRITE_MACLO_A
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_PAR_MACWHI_A
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_WRITE_MACWHI_A
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_PAR_MACWLO_A
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_WRITE_MACWLO_A
-/* end-sanitize-m32rx */
- , M32RXF_INSN_PAR_MUL, M32RXF_INSN_WRITE_MUL
-/* start-sanitize-m32rx */
- , M32RXF_INSN_PAR_MULHI_A
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_WRITE_MULHI_A
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_PAR_MULLO_A
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_WRITE_MULLO_A
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_PAR_MULWHI_A
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_WRITE_MULWHI_A
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_PAR_MULWLO_A
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_WRITE_MULWLO_A
-/* end-sanitize-m32rx */
- , M32RXF_INSN_PAR_MV, M32RXF_INSN_WRITE_MV
-/* start-sanitize-m32rx */
- , M32RXF_INSN_PAR_MVFACHI_A
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_WRITE_MVFACHI_A
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_PAR_MVFACLO_A
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_WRITE_MVFACLO_A
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_PAR_MVFACMI_A
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_WRITE_MVFACMI_A
-/* end-sanitize-m32rx */
- , M32RXF_INSN_PAR_MVFC, M32RXF_INSN_WRITE_MVFC
-/* start-sanitize-m32rx */
- , M32RXF_INSN_PAR_MVTACHI_A
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_WRITE_MVTACHI_A
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_PAR_MVTACLO_A
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_WRITE_MVTACLO_A
-/* end-sanitize-m32rx */
- , M32RXF_INSN_PAR_MVTC, M32RXF_INSN_WRITE_MVTC, M32RXF_INSN_PAR_NEG, M32RXF_INSN_WRITE_NEG
- , M32RXF_INSN_PAR_NOP, M32RXF_INSN_WRITE_NOP, M32RXF_INSN_PAR_NOT, M32RXF_INSN_WRITE_NOT
-/* start-sanitize-m32rx */
- , M32RXF_INSN_PAR_RAC_DSI
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_WRITE_RAC_DSI
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_PAR_RACH_DSI
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_WRITE_RACH_DSI
-/* end-sanitize-m32rx */
- , M32RXF_INSN_PAR_RTE, M32RXF_INSN_WRITE_RTE, M32RXF_INSN_PAR_SLL, M32RXF_INSN_WRITE_SLL
- , M32RXF_INSN_PAR_SLLI, M32RXF_INSN_WRITE_SLLI, M32RXF_INSN_PAR_SRA, M32RXF_INSN_WRITE_SRA
- , M32RXF_INSN_PAR_SRAI, M32RXF_INSN_WRITE_SRAI, M32RXF_INSN_PAR_SRL, M32RXF_INSN_WRITE_SRL
- , M32RXF_INSN_PAR_SRLI, M32RXF_INSN_WRITE_SRLI, M32RXF_INSN_PAR_ST, M32RXF_INSN_WRITE_ST
- , M32RXF_INSN_PAR_STB, M32RXF_INSN_WRITE_STB, M32RXF_INSN_PAR_STH, M32RXF_INSN_WRITE_STH
- , M32RXF_INSN_PAR_ST_PLUS, M32RXF_INSN_WRITE_ST_PLUS, M32RXF_INSN_PAR_ST_MINUS, M32RXF_INSN_WRITE_ST_MINUS
- , M32RXF_INSN_PAR_SUB, M32RXF_INSN_WRITE_SUB, M32RXF_INSN_PAR_SUBV, M32RXF_INSN_WRITE_SUBV
- , M32RXF_INSN_PAR_SUBX, M32RXF_INSN_WRITE_SUBX, M32RXF_INSN_PAR_TRAP, M32RXF_INSN_WRITE_TRAP
- , M32RXF_INSN_PAR_UNLOCK, M32RXF_INSN_WRITE_UNLOCK
-/* start-sanitize-m32rx */
- , M32RXF_INSN_PAR_PCMPBZ
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_WRITE_PCMPBZ
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_PAR_SADD
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_WRITE_SADD
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_PAR_MACWU1
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_WRITE_MACWU1
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_PAR_MSBLO
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_WRITE_MSBLO
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_PAR_MULWU1
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_WRITE_MULWU1
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_PAR_MACLH1
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_WRITE_MACLH1
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_PAR_SC
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_WRITE_SC
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_PAR_SNC
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32RXF_INSN_WRITE_SNC
-/* end-sanitize-m32rx */
- , M32RXF_INSN_MAX
-} M32RXF_INSN_TYPE;
-
-#if ! WITH_SEM_SWITCH_FULL
-#define SEMFULL(fn) extern SEMANTIC_FN CONCAT3 (m32rxf,_sem_,fn);
-#else
-#define SEMFULL(fn)
-#endif
-
-#if ! WITH_SEM_SWITCH_FAST
-#define SEMFAST(fn) extern SEMANTIC_FN CONCAT3 (m32rxf,_semf_,fn);
-#else
-#define SEMFAST(fn)
-#endif
-
-#define SEM(fn) SEMFULL (fn) SEMFAST (fn)
-
-/* The function version of the before/after handlers is always needed,
-   so we always want the SEMFULL declaration of them.  */
-extern SEMANTIC_FN CONCAT3 (m32rxf,_sem_,x_before);
-extern SEMANTIC_FN CONCAT3 (m32rxf,_sem_,x_after);
-
-SEM (x_invalid)
-SEM (x_after)
-SEM (x_before)
-SEM (x_cti_chain)
-SEM (x_chain)
-SEM (x_begin)
-SEM (add)
-SEM (add3)
-SEM (and)
-SEM (and3)
-SEM (or)
-SEM (or3)
-SEM (xor)
-SEM (xor3)
-SEM (addi)
-SEM (addv)
-SEM (addv3)
-SEM (addx)
-SEM (bc8)
-SEM (bc24)
-SEM (beq)
-SEM (beqz)
-SEM (bgez)
-SEM (bgtz)
-SEM (blez)
-SEM (bltz)
-SEM (bnez)
-SEM (bl8)
-SEM (bl24)
-SEM (bcl8)
-SEM (bcl24)
-SEM (bnc8)
-SEM (bnc24)
-SEM (bne)
-SEM (bra8)
-SEM (bra24)
-SEM (bncl8)
-SEM (bncl24)
-SEM (cmp)
-SEM (cmpi)
-SEM (cmpu)
-SEM (cmpui)
-SEM (cmpeq)
-SEM (cmpz)
-SEM (div)
-SEM (divu)
-SEM (rem)
-SEM (remu)
-SEM (divh)
-SEM (jc)
-SEM (jnc)
-SEM (jl)
-SEM (jmp)
-SEM (ld)
-SEM (ld_d)
-SEM (ldb)
-SEM (ldb_d)
-SEM (ldh)
-SEM (ldh_d)
-SEM (ldub)
-SEM (ldub_d)
-SEM (lduh)
-SEM (lduh_d)
-SEM (ld_plus)
-SEM (ld24)
-SEM (ldi8)
-SEM (ldi16)
-SEM (lock)
-SEM (machi_a)
-SEM (maclo_a)
-SEM (macwhi_a)
-SEM (macwlo_a)
-SEM (mul)
-SEM (mulhi_a)
-SEM (mullo_a)
-SEM (mulwhi_a)
-SEM (mulwlo_a)
-SEM (mv)
-SEM (mvfachi_a)
-SEM (mvfaclo_a)
-SEM (mvfacmi_a)
-SEM (mvfc)
-SEM (mvtachi_a)
-SEM (mvtaclo_a)
-SEM (mvtc)
-SEM (neg)
-SEM (nop)
-SEM (not)
-SEM (rac_dsi)
-SEM (rach_dsi)
-SEM (rte)
-SEM (seth)
-SEM (sll)
-SEM (sll3)
-SEM (slli)
-SEM (sra)
-SEM (sra3)
-SEM (srai)
-SEM (srl)
-SEM (srl3)
-SEM (srli)
-SEM (st)
-SEM (st_d)
-SEM (stb)
-SEM (stb_d)
-SEM (sth)
-SEM (sth_d)
-SEM (st_plus)
-SEM (st_minus)
-SEM (sub)
-SEM (subv)
-SEM (subx)
-SEM (trap)
-SEM (unlock)
-SEM (satb)
-SEM (sath)
-SEM (sat)
-SEM (pcmpbz)
-SEM (sadd)
-SEM (macwu1)
-SEM (msblo)
-SEM (mulwu1)
-SEM (maclh1)
-SEM (sc)
-SEM (snc)
-
-#undef SEMFULL
-#undef SEMFAST
-#undef SEM
-
-/* Function unit handlers (user written).  */
-
-extern int m32rxf_model_m32rx_u_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
-extern int m32rxf_model_m32rx_u_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/, INT /*dr*/);
-extern int m32rxf_model_m32rx_u_cti (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/);
-extern int m32rxf_model_m32rx_u_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
-extern int m32rxf_model_m32rx_u_cmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
-extern int m32rxf_model_m32rx_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/, INT /*sr2*/, INT /*dr*/);
-
-/* Profiling before/after handlers (user written) */
-
-extern void m32rxf_model_insn_before (SIM_CPU *, int /*first_p*/);
-extern void m32rxf_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
-
-#endif /* M32RXF_DECODE_H */
diff --git a/sim/m32r/devices.c b/sim/m32r/devices.c
deleted file mode 100644
index 0f4ee2d..0000000
--- a/sim/m32r/devices.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/* m32r device support
-   Copyright (C) 1997, 1998 Free Software Foundation, Inc.
-   Contributed by Cygnus Solutions.
-
-This file is part of GDB, the GNU debugger.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
-
-#include "sim-main.h"
-
-#ifdef HAVE_DV_SOCKSER
-#include "dv-sockser.h"
-#endif
-
-/* Handling the MSPR register is done by creating a device in the core
-   mapping that winds up here.  */
-
-device m32r_devices;
-
-int
-device_io_read_buffer (device *me, void *source, int space,
-		       address_word addr, unsigned nr_bytes,
-		       SIM_CPU *cpu, sim_cia cia)
-{
-  SIM_DESC sd = CPU_STATE (cpu);
-
-  if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
-    return nr_bytes;
-
-#ifdef HAVE_DV_SOCKSER
-  if (addr == UART_INCHAR_ADDR)
-    {
-      int c = dv_sockser_read (sd);
-      if (c == -1)
-	return 0;
-      *(char *) source = c;
-      return 1;
-    }
-  if (addr == UART_STATUS_ADDR)
-    {
-      int status = dv_sockser_status (sd);
-      unsigned char *p = source;
-      p[0] = 0;
-      p[1] = (((status & DV_SOCKSER_INPUT_EMPTY)
-#ifdef UART_INPUT_READY0
-	       ? UART_INPUT_READY : 0)
-#else
-	       ? 0 : UART_INPUT_READY)
-#endif
-	      + ((status & DV_SOCKSER_OUTPUT_EMPTY) ? UART_OUTPUT_READY : 0));
-      return 2;
-    }
-#endif
-
-  return nr_bytes;
-}
-
-int
-device_io_write_buffer (device *me, const void *source, int space,
-			address_word addr, unsigned nr_bytes,
-			SIM_CPU *cpu, sim_cia cia)
-{
-  SIM_DESC sd = CPU_STATE (cpu);
-
-#if WITH_SCACHE
-  /* MSPR support is deprecated but is kept in for upward compatibility
-     with existing overlay support.  */
-  if (addr == MSPR_ADDR)
-    {
-      if ((*(const char *) source & MSPR_PURGE) != 0)
-	scache_flush (sd);
-      return nr_bytes;
-    }
-  if (addr == MCCR_ADDR)
-    {
-      if ((*(const char *) source & MCCR_CP) != 0)
-	scache_flush (sd);
-      return nr_bytes;
-    }
-#endif
-
-  if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
-    return nr_bytes;
-
-#if HAVE_DV_SOCKSER
-  if (addr == UART_OUTCHAR_ADDR)
-    {
-      int rc = dv_sockser_write (sd, *(char *) source);
-      return rc == 1;
-    }
-#endif
-
-  return nr_bytes;
-}
-
-void device_error () {}
diff --git a/sim/m32r/m32r-sim.h b/sim/m32r/m32r-sim.h
deleted file mode 100644
index 7985092..0000000
--- a/sim/m32r/m32r-sim.h
+++ /dev/null
@@ -1,174 +0,0 @@
-/* collection of junk waiting time to sort out
-   Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
-   Contributed by Cygnus Support.
-
-This file is part of the GNU Simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
-
-#ifndef M32R_SIM_H
-#define M32R_SIM_H
-
-/* Register numbers used in gdb interface.  */
-#define PC_REGNUM	21
-#define ACCL_REGNUM	22
-#define ACCH_REGNUM	23
-
-/* Misc. profile data.  */
-
-typedef struct {
-  /* nop insn slot filler count */
-  unsigned int fillnop_count;
-  /* number of parallel insns */
-  unsigned int parallel_count;
-
-  /* FIXME: generalize this to handle all insn lengths, move to common.  */
-  /* number of short insns, not including parallel ones */
-  unsigned int short_count;
-  /* number of long insns */
-  unsigned int long_count;
-
-  /* Working area for computing cycle counts.  */
-  unsigned long insn_cycles;
-  unsigned long cti_stall;
-  unsigned long load_stall;
-  unsigned long biggest_cycles;
-} M32R_MISC_PROFILE;
-
-/* Initialize the working area.  */
-void m32r_init_insn_cycles (SIM_CPU *, int);
-/* Update the totals for the insn.  */
-void m32r_record_insn_cycles (SIM_CPU *, int);
-
-/* This is invoked by the nop pattern in the .cpu file.  */
-#define PROFILE_COUNT_FILLNOPS(cpu, addr) \
-do { \
-  if (PROFILE_INSN_P (cpu) \
-      && (addr & 3) != 0) \
-    ++ CPU_M32R_MISC_PROFILE (cpu).fillnop_count; \
-} while (0)
-
-/* This is invoked by the execute section of mloop{,x}.in.  */
-#define PROFILE_COUNT_PARINSNS(cpu) \
-do { \
-  if (PROFILE_INSN_P (cpu)) \
-    ++ CPU_M32R_MISC_PROFILE (cpu).parallel_count; \
-} while (0)
-
-/* This is invoked by the execute section of mloop{,x}.in.  */
-#define PROFILE_COUNT_SHORTINSNS(cpu) \
-do { \
-  if (PROFILE_INSN_P (cpu)) \
-    ++ CPU_M32R_MISC_PROFILE (cpu).short_count; \
-} while (0)
-
-/* This is invoked by the execute section of mloop{,x}.in.  */
-#define PROFILE_COUNT_LONGINSNS(cpu) \
-do { \
-  if (PROFILE_INSN_P (cpu)) \
-    ++ CPU_M32R_MISC_PROFILE (cpu).long_count; \
-} while (0)
-
-#define GETTWI GETTSI
-#define SETTWI SETTSI
-
-/* Additional execution support.  */
-
-/* Result of semantic function is one of
-   - next address, branch only
-   - NEW_PC_SKIP, sc/snc insn
-   - NEW_PC_2, 2 byte non-branch non-sc/snc insn
-   - NEW_PC_4, 4 byte non-branch insn
-   The special values have bit 1 set so it's cheap to distinguish them.
-   This works because all cti's are defined to zero the bottom two bits.  */
-/* FIXME: replace 0xffff0001 with 1?  */
-#define NEW_PC_BASE 0xffff0001
-#define NEW_PC_SKIP NEW_PC_BASE
-#define NEW_PC_2 (NEW_PC_BASE + 2)
-#define NEW_PC_4 (NEW_PC_BASE + 4)
-#define NEW_PC_BRANCH_P(addr) (((addr) & 1) == 0)
-
-/* start-sanitize-m32rx */
-/* Modify "next pc" handling to handle parallel execution.  */
-#ifdef WANT_CPU_M32RX
-#undef SEM_NEXT_PC
-#define SEM_NEXT_PC(abuf, len) (NEW_PC_BASE + (len))
-#endif
-/* end-sanitize-m32rx */
-
-/* This macro is emitted by the generator to record branch addresses.  */
-#define BRANCH_NEW_PC(var, addr) \
-do { var = (addr); } while (0)
-
-/* Hardware/device support.  */
-
-/* Exception, Interrupt, and Trap addresses */
-#define EIT_SYSBREAK_ADDR	0x10
-#define EIT_RSVD_INSN_ADDR	0x20
-#define EIT_ADDR_EXCP_ADDR	0x30
-#define EIT_TRAP_BASE_ADDR	0x40
-#define EIT_EXTERN_ADDR		0x80
-#define EIT_RESET_ADDR		0x7ffffff0
-#define EIT_WAKEUP_ADDR		0x7ffffff0
-
-/* Special purpose traps.  */
-#define TRAP_SYSCALL	0
-#define TRAP_BREAKPOINT	1
-
-/* Support for the MSPR register (Cache Purge Control Register)
-   and the MCCR register (Cache Control Register) are needed in order for
-   overlays to work correctly with the scache.
-   MSPR no longer exists but is supported for upward compatibility with
-   early overlay support.  */
-
-/* Cache Purge Control (only exists on early versions of chips) */
-#define MSPR_ADDR 0xfffffff7
-#define MSPR_PURGE 1
-
-/* Lock Control Register (not supported) */
-#define MLCR_ADDR 0xfffffff7
-#define MLCR_LM 1
-
-/* Power Management Control Register (not supported) */
-#define MPMR_ADDR 0xfffffffb
-
-/* Cache Control Register */
-#define MCCR_ADDR 0xffffffff
-#define MCCR_CP 0x80
-/* not supported */
-#define MCCR_CM0 2
-#define MCCR_CM1 1
-
-/* Serial device addresses.  */
-#define UART_INCHAR_ADDR	0xff102013
-#define UART_OUTCHAR_ADDR	0xff10200f
-#define UART_STATUS_ADDR	0xff102006
-#define UART_INPUT_EMPTY	0x4
-#define UART_OUTPUT_EMPTY	0x1
-
-/* Start address and length of all device support.  */
-#define M32R_DEVICE_ADDR	0xff000000
-#define M32R_DEVICE_LEN		0x00ffffff
-
-/* sim_core_attach device argument.  */
-extern device m32r_devices;
-
-/* FIXME: Temporary, until device support ready.  */
-struct _device { int foo; };
-
-/* Handle the trap insn.  */
-USI m32r_trap (SIM_CPU *, PCADDR, int);
-
-#endif /* M32R_SIM_H */
diff --git a/sim/m32r/m32r.c b/sim/m32r/m32r.c
deleted file mode 100644
index 863da1e..0000000
--- a/sim/m32r/m32r.c
+++ /dev/null
@@ -1,258 +0,0 @@
-/* m32r simulator support code
-   Copyright (C) 1996, 1997 Free Software Foundation, Inc.
-   Contributed by Cygnus Support.
-
-This file is part of GDB, the GNU debugger.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
-
-#define WANT_CPU
-#define WANT_CPU_M32R
-
-#include "sim-main.h"
-#include <signal.h>
-#include "libiberty.h"
-#include "bfd.h"
-/* FIXME: need to provide general mechanism for accessing target files 
-   these.  For now this is a hack to avoid getting the host version.  */
-#include "../../libgloss/m32r/sys/syscall.h"
-#include "targ-vals.h"
-
-/* The contents of BUF are in target byte order.  */
-
-void
-m32r_fetch_register (sd, rn, buf)
-     SIM_DESC sd;
-     int rn;
-     unsigned char *buf;
-{
-  SIM_CPU *current_cpu = STATE_CPU (sd, 0);
-
-  if (rn < 16)
-    SETTWI (buf, GET_H_GR (rn));
-  else if (rn < 21)
-    SETTWI (buf, GET_H_CR (rn - 16));
-  else switch (rn) {
-    case PC_REGNUM:
-      SETTWI (buf, GET_H_PC ());
-      break;
-    case ACCL_REGNUM:
-      SETTWI (buf, GETLODI (GET_H_ACCUM ()));
-      break;
-    case ACCH_REGNUM:
-      SETTWI (buf, GETHIDI (GET_H_ACCUM ()));
-      break;
-#if 0
-    case 23: *reg = STATE_CPU_CPU (sd, 0)->h_cond;		break;
-    case 24: *reg = STATE_CPU_CPU (sd, 0)->h_sm;		break;
-    case 25: *reg = STATE_CPU_CPU (sd, 0)->h_bsm;		break;
-    case 26: *reg = STATE_CPU_CPU (sd, 0)->h_ie;		break;
-    case 27: *reg = STATE_CPU_CPU (sd, 0)->h_bie;		break;
-    case 28: *reg = STATE_CPU_CPU (sd, 0)->h_bcarry;		break; /* rename: bc */
-    case 29: memcpy (buf, &STATE_CPU_CPU (sd, 0)->h_bpc, sizeof(WI));	break; /* duplicate */
-#endif
-    default: abort ();
-  }
-}
- 
-/* The contents of BUF are in target byte order.  */
-
-void
-m32r_store_register (sd, rn, buf)
-     SIM_DESC sd;
-     int rn;
-     unsigned char *buf;
-{
-  SIM_CPU *current_cpu = STATE_CPU (sd, 0);
-
-  if (rn < 16)
-    SET_H_GR (rn, GETTWI (buf));
-  else if (rn < 21)
-    SET_H_CR (rn - 16, GETTWI (buf));
-  else switch (rn) {
-    case PC_REGNUM:
-      SET_H_PC (GETTWI (buf));
-      break;
-    case ACCL_REGNUM:
-      SETLODI (CPU (h_accum), GETTWI (buf));
-      break;
-    case ACCH_REGNUM:
-      SETHIDI (CPU (h_accum), GETTWI (buf));
-      break;
-#if 0
-    case 23: STATE_CPU_CPU (sd, 0)->h_cond   = *reg;			break;
-    case 24: STATE_CPU_CPU (sd, 0)->h_sm     = *reg;			break;
-    case 25: STATE_CPU_CPU (sd, 0)->h_bsm    = *reg;			break;
-    case 26: STATE_CPU_CPU (sd, 0)->h_ie     = *reg;			break;
-    case 27: STATE_CPU_CPU (sd, 0)->h_bie    = *reg;			break;
-    case 28: STATE_CPU_CPU (sd, 0)->h_bcarry = *reg;			break; /* rename: bc */
-    case 29: memcpy (&STATE_CPU_CPU (sd, 0)->h_bpc, buf, sizeof(DI));	break; /* duplicate */
-#endif
-  }
-}
-
-/* Handling the MSPR register is done by creating a device in the core
-   mapping that winds up here.  */
-
-device m32r_mspr_device;
-
-int
-device_io_read_buffer (device *me, const void *source, int space,
-			address_word addr, unsigned nr_bytes,
-			SIM_CPU *cpu, sim_cia cia)
-{
-  abort ();
-}
-
-int
-device_io_write_buffer (device *me, const void *source, int space,
-			address_word addr, unsigned nr_bytes,
-			SIM_CPU *cpu, sim_cia cia)
-{
-#if WITH_SCACHE
-  if (addr == MSPR_ADDR
-      && (*(char *) source & 1) != 0)
-    scache_flush (CPU_STATE (cpu));
-#endif
-  return nr_bytes;
-}
-
-void device_error () {}
-
-#if WITH_PROFILE_MODEL_P
-
-void
-m32r_model_mark_get_h_gr (SIM_CPU *cpu, ARGBUF *abuf)
-{
-  if ((CPU_CGEN_PROFILE (cpu)->h_gr & abuf->h_gr_get) != 0)
-    {
-      PROFILE_MODEL_LOAD_STALL_COUNT (CPU_PROFILE_DATA (cpu)) += 2;
-      if (TRACE_INSN_P (cpu))
-	cgen_trace_printf (cpu, " ; Load stall of 2 cycles.");
-    }
-}
-
-void
-m32r_model_mark_set_h_gr (SIM_CPU *cpu, ARGBUF *abuf)
-{
-}
-
-void
-m32r_model_mark_busy_reg (SIM_CPU *cpu, ARGBUF *abuf)
-{
-  CPU_CGEN_PROFILE (cpu)->h_gr = abuf->h_gr_set;
-}
-
-void
-m32r_model_mark_unbusy_reg (SIM_CPU *cpu, ARGBUF *abuf)
-{
-  CPU_CGEN_PROFILE (cpu)->h_gr = 0;
-}
-
-#endif /* WITH_PROFILE_MODEL_P */
-
-USI
-m32r_h_cr_get (SIM_CPU *current_cpu, UINT cr)
-{
-  /* FIXME: Create enums H_CR_FOO, etc.  */
-  switch (cr)
-    {
-    case 0 : /* psw */
-      return ((CPU (h_bsm) << 15)
-	      | (CPU (h_bie) << 14)
-	      | (CPU (h_bcond) << 8)
-	      | (CPU (h_sm) << 7)
-	      | (CPU (h_ie) << 6)
-	      | (CPU (h_cond) << 0));
-    case 1 : /* condition bit */
-      return CPU (h_cond);
-    case 2 : /* interrupt stack pointer */
-      if (! CPU (h_sm))
-	return CPU (h_gr[15]);
-      else
-	return CPU (h_cr[2]);
-    case 3 : /* user stack pointer */
-      if (CPU (h_sm))
-	return CPU (h_gr[15]);
-      else
-	return CPU (h_cr[3]);
-    case 6 : /* backup pc */
-      /* ??? We don't really support this yet.  */
-    case 4 : /* unused */
-    case 5 : /* unused */
-      return CPU (h_cr[cr]);
-    default :
-      return 0;
-    }
-}
-
-void
-m32r_h_cr_set (SIM_CPU *current_cpu, UINT cr, USI newval)
-{
-  /* FIXME: Create enums H_CR_FOO, etc.  */
-  switch (cr)
-    {
-    case 0 : /* psw */
-      {
-	int old_sm = CPU (h_sm);
-	CPU (h_bsm) = (newval & (1 << 15)) != 0;
-	CPU (h_bie) = (newval & (1 << 14)) != 0;
-	CPU (h_bcond) = (newval & (1 << 8)) != 0;
-	CPU (h_sm) = (newval & (1 << 7)) != 0;
-	CPU (h_ie) = (newval & (1 << 6)) != 0;
-	CPU (h_cond) = (newval & (1 << 0)) != 0;
-	/* When switching stack modes, update the registers.  */
-	if (old_sm != CPU (h_sm))
-	  {
-	    if (old_sm)
-	      {
-		/* Switching user -> system.  */
-		CPU (h_cr[3]) = CPU (h_gr[15]);
-		CPU (h_gr[15]) = CPU (h_cr[2]);
-	      }
-	    else
-	      {
-		/* Switching system -> user.  */
-		CPU (h_cr[2]) = CPU (h_gr[15]);
-		CPU (h_gr[15]) = CPU (h_cr[3]);
-	      }
-	  }
-	break;
-      }
-    case 1 : /* condition bit */
-      CPU (h_cond) = (newval & 1) != 0;
-      break;
-    case 2 : /* interrupt stack pointer */
-      if (! CPU (h_sm))
-	CPU (h_gr[15]) = newval;
-      else
-	CPU (h_cr[2]) = newval;
-      break;
-    case 3 : /* user stack pointer */
-      if (CPU (h_sm))
-	CPU (h_gr[15]) = newval;
-      else
-	CPU (h_cr[3]) = newval;
-      break;
-    case 4 : /* unused */
-    case 5 : /* unused */
-    case 6 : /* backup pc */
-      CPU (h_cr[cr]) = newval;
-      break;
-    default :
-      /* ignore */
-      break;
-    }
-}
diff --git a/sim/m32r/m32rx.c b/sim/m32r/m32rx.c
deleted file mode 100644
index 1710428..0000000
--- a/sim/m32r/m32rx.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/* m32rx simulator support code
-   Copyright (C) 1997, 1998 Free Software Foundation, Inc.
-   Contributed by Cygnus Support.
-
-This file is part of GDB, the GNU debugger.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
-
-#define WANT_CPU
-#define WANT_CPU_M32RX
-
-#include "sim-main.h"
-#include <signal.h>
-#include "libiberty.h"
-#include "bfd.h"
-/* FIXME: need to provide general mechanism for accessing target files 
-   these.  For now this is a hack to avoid getting the host version.  */
-#include "../../libgloss/m32r/sys/syscall.h"
-#include "targ-vals.h"
-
-/* The contents of BUF are in target byte order.  */
-
-void
-m32rx_fetch_register (sd, rn, buf)
-     SIM_DESC sd;
-     int rn;
-     unsigned char *buf;
-{
-  SIM_CPU *current_cpu = STATE_CPU (sd, 0);
-
-  if (rn < 16)
-    SETTWI (buf, GET_H_GR (rn));
-  else if (rn < 21)
-    SETTWI (buf, GET_H_CR (rn - 16));
-  else switch (rn) {
-    case PC_REGNUM:
-      SETTWI (buf, GET_H_PC ());
-      break;
-    case ACCL_REGNUM:
-      SETTWI (buf, GETLODI (GET_H_ACCUM ()));
-      break;
-    case ACCH_REGNUM:
-      SETTWI (buf, GETHIDI (GET_H_ACCUM ()));
-      break;
-#if 0
-    case 23: *reg = STATE_CPU_CPU (sd, 0)->h_cond;		break;
-    case 24: *reg = STATE_CPU_CPU (sd, 0)->h_sm;		break;
-    case 25: *reg = STATE_CPU_CPU (sd, 0)->h_bsm;		break;
-    case 26: *reg = STATE_CPU_CPU (sd, 0)->h_ie;		break;
-    case 27: *reg = STATE_CPU_CPU (sd, 0)->h_bie;		break;
-    case 28: *reg = STATE_CPU_CPU (sd, 0)->h_bcarry;		break; /* rename: bc */
-    case 29: memcpy (buf, &STATE_CPU_CPU (sd, 0)->h_bpc, sizeof(WI));	break; /* duplicate */
-#endif
-    default: abort ();
-  }
-}
- 
-/* The contents of BUF are in target byte order.  */
-
-void
-m32rx_store_register (sd, rn, buf)
-     SIM_DESC sd;
-     int rn;
-     unsigned char *buf;
-{
-  SIM_CPU *current_cpu = STATE_CPU (sd, 0);
-
-  if (rn < 16)
-    SET_H_GR (rn, GETTWI (buf));
-  else if (rn < 21)
-    SET_H_CR (rn - 16, GETTWI (buf));
-  else switch (rn) {
-    case PC_REGNUM:
-      SET_H_PC (GETTWI (buf));
-      break;
-    case ACCL_REGNUM:
-      SETLODI (CPU (h_accum), GETTWI (buf));
-      break;
-    case ACCH_REGNUM:
-      SETHIDI (CPU (h_accum), GETTWI (buf));
-      break;
-#if 0
-    case 23: STATE_CPU_CPU (sd, 0)->h_cond   = *reg;			break;
-    case 24: STATE_CPU_CPU (sd, 0)->h_sm     = *reg;			break;
-    case 25: STATE_CPU_CPU (sd, 0)->h_bsm    = *reg;			break;
-    case 26: STATE_CPU_CPU (sd, 0)->h_ie     = *reg;			break;
-    case 27: STATE_CPU_CPU (sd, 0)->h_bie    = *reg;			break;
-    case 28: STATE_CPU_CPU (sd, 0)->h_bcarry = *reg;			break; /* rename: bc */
-    case 29: memcpy (&STATE_CPU_CPU (sd, 0)->h_bpc, buf, sizeof(DI));	break; /* duplicate */
-#endif
-  }
-}
-
-/* Cover fn to access h-accums.  */
-
-UDI
-m32rx_h_accums_get (SIM_CPU *current_cpu, UINT accum)
-{
-  return 0;
-}
diff --git a/sim/m32r/mloop.in b/sim/m32r/mloop.in
deleted file mode 100644
index 921fa89..0000000
--- a/sim/m32r/mloop.in
+++ /dev/null
@@ -1,187 +0,0 @@
-# Simulator main loop for m32r. -*- C -*-
-# Copyright (C) 1996, 1997 Free Software Foundation, Inc.
-#
-# This file is part of the GNU Simulators.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License along
-# with this program; if not, write to the Free Software Foundation, Inc.,
-# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-# Syntax:
-# /bin/sh mainloop.in init|support|{full,fast}-{extract,exec}-{scache,noscache}
-
-# ??? After a few more ports are done, revisit.
-# Will eventually need to machine generate a lot of this.
-
-case "x$1" in
-
-xsupport)
-
-cat <<EOF
-
-static INLINE void
-extract16 (SIM_CPU *current_cpu, PCADDR pc, insn_t insn,
-	   SCACHE *sc, int fast_p)
-{
-  const IDESC *d = @cpu@_decode (current_cpu, pc, insn);
-  (*d->extract) (current_cpu, pc, insn, &sc->argbuf);
-  if (fast_p)
-    {
-#if WITH_SEM_SWITCH_FAST
-#ifdef __GNUC__
-      sc->semantic.sem_case = d->sem_fast_lab;
-#else
-      sc->semantic.sem_case = d->num;
-#endif
-#else
-      sc->semantic.sem_fast = d->sem_fast;
-#endif
-    }
-  else
-    {
-      sc->semantic.sem_full = d->sem_full;
-    }
-  sc->argbuf.idesc = d;
-  sc->next = pc + 2;
-}
-
-static INLINE void
-extract32 (SIM_CPU *current_cpu, PCADDR pc, insn_t insn,
-	   SCACHE *sc, int fast_p)
-{
-  const IDESC *d = @cpu@_decode (current_cpu, pc, (USI) insn >> 16);
-  (*d->extract) (current_cpu, pc, insn, &sc->argbuf);
-  if (fast_p)
-    {
-#if WITH_SEM_SWITCH_FAST
-#ifdef __GNUC__
-      sc->semantic.sem_case = d->sem_fast_lab;
-#else
-      sc->semantic.sem_case = d->num;
-#endif
-#else
-      sc->semantic.sem_fast_fn = d->sem_fast;
-#endif
-    }
-  else
-    {
-      sc->semantic.sem_full = d->sem_full;
-    }
-  sc->argbuf.idesc = d;
-  sc->next = pc + 4;
-}
-
-static INLINE PCADDR
-execute (SIM_CPU *current_cpu, SCACHE *sc, int fast_p)
-{
-  PCADDR pc;
-
-  if (fast_p)
-    {
-#if WITH_SCACHE && ! WITH_SEM_SWITCH_FAST
-      pc = (*sc->semantic.sem_fast) (current_cpu, sc);
-#else
-#if 0
-      pc = (*sc->semantic.sem_full) (current_cpu, &sc->argbuf);
-#else
-      pc = (*sc->semantic.sem_full) (current_cpu, sc);
-#endif
-#endif
-    }
-  else
-    {
-      m32r_model_init_insn_cycles (current_cpu, 1);
-      TRACE_INSN_INIT (current_cpu, 1);
-      TRACE_INSN (current_cpu, sc->argbuf.idesc->opcode, (const struct argbuf *) &sc->argbuf, sc->argbuf.addr);
-#if 0
-      pc = (*sc->semantic.sem_full) (current_cpu, &sc->argbuf);
-#else
-      pc = (*sc->semantic.sem_full) (current_cpu, sc);
-#endif
-      m32r_model_update_insn_cycles (current_cpu, 1);
-      TRACE_INSN_FINI (current_cpu, 1);
-    }
-
-  return pc;
-}
-
-EOF
-
-;;
-
-xinit)
-
-cat <<EOF
-/*xxxinit*/
-EOF
-
-;;
-
-xfull-extract-* | xfast-extract-*)
-
-cat <<EOF
-{
-  PCADDR pc = CPU (h_pc);
-
-  if ((pc & 3) != 0)
-    {
-      /* This only occurs when single stepping.
-	 The test is unnecessary otherwise, but the cost is teensy,
-	 compared with decoding/extraction.  */
-      UHI insn = GETIMEMUHI (current_cpu, pc);
-      extract16 (current_cpu, pc, insn & 0x7fff, sc, FAST_P);
-    }
-  else
-    {
-      USI insn = GETIMEMUSI (current_cpu, pc);
-      if ((SI) insn < 0)
-	{
-	  extract32 (current_cpu, pc, insn, sc, FAST_P);
-	}
-      else
-	{
-	  extract16 (current_cpu, pc, insn >> 16, sc, FAST_P);
-	  extract16 (current_cpu, pc + 2, insn & 0x7fff, sc + 1, FAST_P);
-	  /* The m32r doesn't support parallel execution.  */
-	  if ((insn & 0x8000) != 0
-	      && (insn & 0x7fff) != 0x7000) /* parallel nops are ok */
-	    sim_engine_illegal_insn (current_cpu, pc);
-	}
-    }
-}
-EOF
-
-;;
-
-xfull-exec-* | xfast-exec-*)
-
-cat <<EOF
-{
-#if WITH_SCACHE && FAST_P && WITH_SEM_SWITCH_FAST
-#define DEFINE_SWITCH
-#include "sem-switch.c"
-#else
-  PCADDR new_pc = execute (current_cpu, sc, FAST_P);
-  CPU (h_pc) = new_pc;
-#endif
-}
-EOF
-
-;;
-
-*)
-  echo "Invalid argument to mainloop.in: $1" >&2
-  exit 1
-  ;;
-
-esac
diff --git a/sim/m32r/mloopx.in b/sim/m32r/mloopx.in
deleted file mode 100644
index 6b084f4..0000000
--- a/sim/m32r/mloopx.in
+++ /dev/null
@@ -1,205 +0,0 @@
-# Simulator main loop for m32rx. -*- C -*-
-# Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
-#
-# This file is part of the GNU Simulators.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License along
-# with this program; if not, write to the Free Software Foundation, Inc.,
-# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-# Syntax:
-# /bin/sh mainloop.in init|support|{full,fast}-{extract,exec}-{scache,noscache}
-
-# ??? After a few more ports are done, revisit.
-# Will eventually need to machine generate a lot of this.
-
-case "x$1" in
-
-xsupport)
-
-cat <<EOF
-
-EOF
-
-;;
-
-xinit)
-
-cat <<EOF
-  const IDESC *d1,*d2;
-  ARGBUF abufs[MAX_PARALLEL_INSNS];
-  PAREXEC pbufs[MAX_PARALLEL_INSNS];
-EOF
-
-;;
-
-xfull-extract-* | xfast-extract-*)
-
-cat <<EOF
-{
-  PCADDR pc = CPU (h_pc);
-
-  /* ??? This code isn't very fast.  Let's get it working first.  */
-
-  if ((pc & 3) != 0)
-    {
-      USI insn = GETIMEMUHI (current_cpu, pc);
-      insn &= 0x7fff;
-      d1 = m32rx_decode (current_cpu, pc, insn);
-      abufs[0].insn = insn;
-      abufs[0].idesc = d1;
-      abufs[0].addr = pc; /* FIXME: wip */
-      icount = 1;
-    }
-  else
-    {
-      USI insn = GETIMEMUSI (current_cpu, pc);
-      if ((SI) insn < 0)
-	{
-	  d1 = m32rx_decode (current_cpu, pc, insn >> 16);
-	  abufs[0].insn = insn;
-	  abufs[0].idesc = d1;
-	  abufs[0].addr = pc; /* FIXME: wip */
-	  icount = 1;
-	}
-      else
-	{
-	  if (insn & 0x8000)
-	    {
-	      d1 = m32rx_decode (current_cpu, pc, insn >> 16);
-	      abufs[0].insn = insn >> 16;
-	      abufs[0].idesc = d1;
-	      abufs[0].addr = pc; /* FIXME: wip */
-	      d2 = m32rx_decode (current_cpu, pc + 2, insn & 0x7fff);
-	      abufs[1].insn = insn & 0x7fff;
-	      abufs[1].idesc = d2;
-	      abufs[1].addr = pc + 2; /* FIXME: wip */
-	      icount = 2;
-	    }
-	  else
-	    {
-	      d1 = m32rx_decode (current_cpu, pc, insn >> 16);
-	      abufs[0].insn = insn >> 16;
-	      abufs[0].idesc = d1;
-	      abufs[0].addr = pc; /* FIXME: wip */
-	      icount = 1;
-	    }
-	}
-    }
-
-  {
-    int icount2 = icount;
-    USI insn = abufs[0].insn;
-    const IDESC *decode = d1;
-    /* decode, par_exec, and insn are refered to by readx.c.  */
-    PAREXEC *par_exec = &pbufs[0];
-    do
-      {
-#define DEFINE_SWITCH
-#include "readx.c"
-
-	decode = d2;
-	insn = abufs[1].insn;
-	++par_exec;
-      }
-    while (--icount2 != 0);
-  }
-}
-EOF
-
-;;
-
-xfull-exec-* | xfast-exec-*)
-
-cat <<EOF
-{
-  SEM_ARG sem_arg = &abufs[0];
-  PAREXEC *par_exec = &pbufs[0];
-  PCADDR new_pc;
-
-#if 0 /* wip */
-  /* If doing parallel execution, verify insns are in the right pipeline.  */
-  if (icount == 2)
-    {
-      ...
-    }
-#endif
-
-  m32r_model_init_insn_cycles (current_cpu, 1);
-  TRACE_INSN_INIT (current_cpu, 1);
-  TRACE_INSN (current_cpu, d1->opcode, sem_arg, CPU (h_pc));
-  new_pc = (*d1->sem_full) (current_cpu, sem_arg, par_exec);
-  m32r_model_update_insn_cycles (current_cpu, icount == 1);
-  TRACE_INSN_FINI (current_cpu, icount == 1);
-
-  /* The result of the semantic fn is one of:
-     - next address, branch only
-     - NEW_PC_SKIP, sc/snc insn
-     - NEW_PC_2, 2 byte non-branch non-sc/snc insn
-     - NEW_PC_4, 4 byte non-branch insn
-     */
-
-  /* The tests are ordered to try to favor the more frequent cases, while
-     keeping the over all costs down.  */
-  if (new_pc == NEW_PC_4)
-    CPU (h_pc) += 4;
-  else if (icount == 2)
-    {
-      /* Note that we only get here if doing parallel execution.  */
-
-      if (new_pc == NEW_PC_SKIP)
-	{
-	  /* ??? Need generic notion of bypassing an insn for the name of
-	     this macro.  Annulled?  On the otherhand such tracing can go
-	     in the sc/snc semantic fn.  */
-	  ; /*TRACE_INSN_SKIPPED (current_cpu);*/
-	  CPU (h_pc) += 4;
-	}
-      else
-        {
-	  PCADDR pc2;
-
-	  ++sem_arg;
-	  ++par_exec;
-	  m32r_model_init_insn_cycles (current_cpu, 0);
-	  TRACE_INSN_INIT (current_cpu, 0);
-	  TRACE_INSN (current_cpu, d2->opcode, sem_arg, CPU (h_pc) + 2);
-	  /* pc2 isn't used.  It's assigned a value for debugging.  */
-	  pc2 = (*d2->sem_full) (current_cpu, sem_arg, par_exec);
-	  m32r_model_update_insn_cycles (current_cpu, 1);
-	  TRACE_INSN_FINI (current_cpu, 1);
-
-	  if (NEW_PC_BRANCH_P (new_pc))
-	    CPU (h_pc) = new_pc;
-	  else
-	    CPU (h_pc) += 4;
-	}
-
-      /* Update count of parallel insns executed.  */
-      PROFILE_COUNT_PARINSNS (current_cpu);
-    }
-  else if (NEW_PC_BRANCH_P (new_pc))
-    CPU (h_pc) = new_pc;
-  else
-    CPU (h_pc) += 2;
-}
-EOF
-
-;;
-
-*)
-  echo "Invalid argument to mainloop.in: $1" >&2
-  exit 1
-  ;;
-
-esac
diff --git a/sim/m32r/model.c b/sim/m32r/model.c
deleted file mode 100644
index 02382d1..0000000
--- a/sim/m32r/model.c
+++ /dev/null
@@ -1,4126 +0,0 @@
-/* Simulator model support for m32rbf.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
-
-This file is part of the GNU Simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#define WANT_CPU m32rbf
-#define WANT_CPU_M32RBF
-
-#include "sim-main.h"
-
-/* The profiling data is recorded here, but is accessed via the profiling
-   mechanism.  After all, this is information for profiling.  */
-
-#if WITH_PROFILE_MODEL_P
-
-/* Model handlers for each insn.  */
-
-static int
-model_m32r_d_add (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    sr = FLD (in_sr);
-    dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_add3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    sr = FLD (in_sr);
-    dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_and (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    sr = FLD (in_sr);
-    dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_and3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_and3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    sr = FLD (in_sr);
-    dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_or (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    sr = FLD (in_sr);
-    dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_or3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_or3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    sr = FLD (in_sr);
-    dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_xor (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    sr = FLD (in_sr);
-    dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_xor3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_and3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    sr = FLD (in_sr);
-    dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_addi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_addi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    dr = FLD (out_dr);
-    sr = FLD (in_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_addv (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_addv.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    sr = FLD (in_sr);
-    dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_addv3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_addv3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    sr = FLD (in_sr);
-    dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_addx (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_addx.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    sr = FLD (in_sr);
-    dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_bc8 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_bc24 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_beq (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_beq.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, sr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT src1 = -1;
-    INT src2 = -1;
-    src1 = FLD (in_src1);
-    src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, src1, src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_beqz (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, sr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT src1 = -1;
-    INT src2 = -1;
-    src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, src1, src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_bgez (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, sr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT src1 = -1;
-    INT src2 = -1;
-    src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, src1, src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_bgtz (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, sr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT src1 = -1;
-    INT src2 = -1;
-    src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, src1, src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_blez (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, sr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT src1 = -1;
-    INT src2 = -1;
-    src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, src1, src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_bltz (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, sr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT src1 = -1;
-    INT src2 = -1;
-    src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, src1, src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_bnez (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, sr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT src1 = -1;
-    INT src2 = -1;
-    src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, src1, src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_bl8 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_bl8.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_bl24 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_bl24.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_bnc8 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_bnc24 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_bne (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_beq.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, sr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT src1 = -1;
-    INT src2 = -1;
-    src1 = FLD (in_src1);
-    src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, src1, src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_bra8 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_bra8.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_bra24 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_bra24.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_cmp (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_cmp.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT src1 = -1;
-    INT src2 = -1;
-    src1 = FLD (in_src1);
-    src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 0, referenced, src1, src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_cmpi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_cmpi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT src1 = -1;
-    INT src2 = -1;
-    src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 0, referenced, src1, src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_cmpu (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_cmp.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT src1 = -1;
-    INT src2 = -1;
-    src1 = FLD (in_src1);
-    src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 0, referenced, src1, src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_cmpui (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_cmpi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT src1 = -1;
-    INT src2 = -1;
-    src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 0, referenced, src1, src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_div (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_div.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    sr = FLD (in_sr);
-    dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_divu (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_div.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    sr = FLD (in_sr);
-    dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_rem (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_div.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    sr = FLD (in_sr);
-    dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_remu (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_div.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    sr = FLD (in_sr);
-    dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_jl (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_jl.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    sr = FLD (in_sr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_jmp (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    sr = FLD (in_sr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_ld (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ld.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = 0;
-    INT dr = 0;
-    sr = FLD (in_sr);
-    dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, sr, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_ld_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ld_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = 0;
-    INT dr = 0;
-    sr = FLD (in_sr);
-    dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, sr, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_ldb (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ldb.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = 0;
-    INT dr = 0;
-    sr = FLD (in_sr);
-    dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, sr, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_ldb_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ldb_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = 0;
-    INT dr = 0;
-    sr = FLD (in_sr);
-    dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, sr, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_ldh (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ldh.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = 0;
-    INT dr = 0;
-    sr = FLD (in_sr);
-    dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, sr, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_ldh_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ldh_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = 0;
-    INT dr = 0;
-    sr = FLD (in_sr);
-    dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, sr, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_ldub (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ldb.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = 0;
-    INT dr = 0;
-    sr = FLD (in_sr);
-    dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, sr, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_ldub_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ldb_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = 0;
-    INT dr = 0;
-    sr = FLD (in_sr);
-    dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, sr, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_lduh (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ldh.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = 0;
-    INT dr = 0;
-    sr = FLD (in_sr);
-    dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, sr, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_lduh_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ldh_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = 0;
-    INT dr = 0;
-    sr = FLD (in_sr);
-    dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, sr, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_ld_plus (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = 0;
-    INT dr = 0;
-    sr = FLD (in_sr);
-    dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, sr, dr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    sr = FLD (in_sr);
-    dr = FLD (out_sr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 1, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_ld24 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ld24.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_ldi8 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ldi8.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_ldi16 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ldi16.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_lock (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_lock.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = 0;
-    INT dr = 0;
-    sr = FLD (in_sr);
-    dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, sr, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_machi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_machi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT src1 = -1;
-    INT src2 = -1;
-    src1 = FLD (in_src1);
-    src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_maclo (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_machi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT src1 = -1;
-    INT src2 = -1;
-    src1 = FLD (in_src1);
-    src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_macwhi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_machi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT src1 = -1;
-    INT src2 = -1;
-    src1 = FLD (in_src1);
-    src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_macwlo (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_machi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT src1 = -1;
-    INT src2 = -1;
-    src1 = FLD (in_src1);
-    src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_mul (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    sr = FLD (in_sr);
-    dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_mulhi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mulhi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT src1 = -1;
-    INT src2 = -1;
-    src1 = FLD (in_src1);
-    src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_mullo (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mulhi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT src1 = -1;
-    INT src2 = -1;
-    src1 = FLD (in_src1);
-    src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_mulwhi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mulhi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT src1 = -1;
-    INT src2 = -1;
-    src1 = FLD (in_src1);
-    src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_mulwlo (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mulhi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT src1 = -1;
-    INT src2 = -1;
-    src1 = FLD (in_src1);
-    src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_mv (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mv.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    sr = FLD (in_sr);
-    dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_mvfachi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mvfachi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_mvfaclo (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mvfachi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_mvfacmi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mvfachi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_mvfc (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mvfc.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_mvtachi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mvtachi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    sr = FLD (in_src1);
-    referenced |= 1 << 0;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_mvtaclo (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mvtachi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    sr = FLD (in_src1);
-    referenced |= 1 << 0;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_mvtc (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mvtc.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    sr = FLD (in_sr);
-    referenced |= 1 << 0;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_neg (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mv.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    sr = FLD (in_sr);
-    dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_nop (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_nop.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_not (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mv.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    sr = FLD (in_sr);
-    dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_rac (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_rac.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT src1 = -1;
-    INT src2 = -1;
-    cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_rach (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_rac.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT src1 = -1;
-    INT src2 = -1;
-    cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, src1, src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_rte (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_rte.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_seth (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_seth.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_sll (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    sr = FLD (in_sr);
-    dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_sll3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_sll3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    sr = FLD (in_sr);
-    dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_slli (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_slli.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_sra (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    sr = FLD (in_sr);
-    dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_sra3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_sll3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    sr = FLD (in_sr);
-    dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_srai (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_slli.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_srl (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    sr = FLD (in_sr);
-    dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_srl3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_sll3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    sr = FLD (in_sr);
-    dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_srli (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_slli.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_st (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_st.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT src1 = 0;
-    INT src2 = 0;
-    src1 = FLD (in_src1);
-    src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, src1, src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_st_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_st_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT src1 = 0;
-    INT src2 = 0;
-    src1 = FLD (in_src1);
-    src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, src1, src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_stb (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_stb.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT src1 = 0;
-    INT src2 = 0;
-    src1 = FLD (in_src1);
-    src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, src1, src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_stb_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_stb_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT src1 = 0;
-    INT src2 = 0;
-    src1 = FLD (in_src1);
-    src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, src1, src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_sth (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_sth.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT src1 = 0;
-    INT src2 = 0;
-    src1 = FLD (in_src1);
-    src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, src1, src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_sth_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_sth_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT src1 = 0;
-    INT src2 = 0;
-    src1 = FLD (in_src1);
-    src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, src1, src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_st_plus (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT src1 = 0;
-    INT src2 = 0;
-    src1 = FLD (in_src1);
-    src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, src1, src2);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    dr = FLD (out_src2);
-    sr = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 1, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_st_minus (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT src1 = 0;
-    INT src2 = 0;
-    src1 = FLD (in_src1);
-    src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, src1, src2);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    dr = FLD (out_src2);
-    sr = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 1, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_sub (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    sr = FLD (in_sr);
-    dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_subv (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_addv.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    sr = FLD (in_sr);
-    dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_subx (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_addx.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    sr = FLD (in_sr);
-    dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_trap (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_trap.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = -1;
-    INT sr2 = -1;
-    INT dr = -1;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_unlock (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_unlock.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT sr = 0;
-    INT dr = 0;
-    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, sr, dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_add (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_add3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_and (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_and3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_and3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_or (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_or3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_or3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_xor (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_xor3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_and3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_addi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_addi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_addv (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_addv.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_addv3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_addv3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_addx (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_addx.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_bc8 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_bc24 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_beq (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_beq.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_beqz (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_bgez (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_bgtz (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_blez (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_bltz (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_bnez (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_bl8 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_bl8.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_bl24 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_bl24.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_bnc8 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_bnc24 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_bne (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_beq.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_bra8 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_bra8.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_bra24 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_bra24.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_cmp (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_cmp.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_cmpi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_cmpi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_cmpu (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_cmp.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_cmpui (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_cmpi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_div (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_div.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_divu (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_div.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_rem (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_div.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_remu (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_div.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_jl (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_jl.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_jmp (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_ld (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ld.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_ld_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ld_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_ldb (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ldb.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_ldb_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ldb_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_ldh (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ldh.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_ldh_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ldh_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_ldub (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ldb.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_ldub_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ldb_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_lduh (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ldh.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_lduh_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ldh_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_ld_plus (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_ld24 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ld24.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_ldi8 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ldi8.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_ldi16 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ldi16.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_lock (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_lock.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_machi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_machi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_maclo (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_machi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_macwhi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_machi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_macwlo (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_machi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_mul (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_mulhi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mulhi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_mullo (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mulhi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_mulwhi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mulhi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_mulwlo (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mulhi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_mv (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mv.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_mvfachi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mvfachi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_mvfaclo (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mvfachi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_mvfacmi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mvfachi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_mvfc (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mvfc.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_mvtachi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mvtachi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_mvtaclo (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mvtachi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_mvtc (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mvtc.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_neg (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mv.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_nop (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_nop.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_not (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mv.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_rac (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_rac.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_rach (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_rac.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_rte (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_rte.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_seth (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_seth.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_sll (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_sll3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_sll3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_slli (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_slli.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_sra (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_sra3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_sll3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_srai (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_slli.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_srl (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_srl3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_sll3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_srli (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_slli.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_st (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_st.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_st_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_st_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_stb (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_stb.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_stb_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_stb_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_sth (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_sth.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_sth_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_sth_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_st_plus (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_st_minus (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_sub (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_subv (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_addv.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_subx (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_addx.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_trap (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_trap.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_unlock (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_unlock.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-/* We assume UNIT_NONE == 0 because the tables don't always terminate
-   entries with it.  */
-
-/* Model timing data for `m32r/d'.  */
-
-static const INSN_TIMING m32r_d_timing[] = {
-  { M32RBF_INSN_X_INVALID, 0, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_X_AFTER, 0, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_X_BEFORE, 0, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_X_CHAIN, 0, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_X_BEGIN, 0, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_ADD, model_m32r_d_add, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_ADD3, model_m32r_d_add3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_AND, model_m32r_d_and, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_AND3, model_m32r_d_and3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_OR, model_m32r_d_or, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_OR3, model_m32r_d_or3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_XOR, model_m32r_d_xor, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_XOR3, model_m32r_d_xor3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_ADDI, model_m32r_d_addi, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_ADDV, model_m32r_d_addv, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_ADDV3, model_m32r_d_addv3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_ADDX, model_m32r_d_addx, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_BC8, model_m32r_d_bc8, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
-  { M32RBF_INSN_BC24, model_m32r_d_bc24, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
-  { M32RBF_INSN_BEQ, model_m32r_d_beq, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
-  { M32RBF_INSN_BEQZ, model_m32r_d_beqz, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
-  { M32RBF_INSN_BGEZ, model_m32r_d_bgez, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
-  { M32RBF_INSN_BGTZ, model_m32r_d_bgtz, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
-  { M32RBF_INSN_BLEZ, model_m32r_d_blez, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
-  { M32RBF_INSN_BLTZ, model_m32r_d_bltz, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
-  { M32RBF_INSN_BNEZ, model_m32r_d_bnez, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
-  { M32RBF_INSN_BL8, model_m32r_d_bl8, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
-  { M32RBF_INSN_BL24, model_m32r_d_bl24, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
-  { M32RBF_INSN_BNC8, model_m32r_d_bnc8, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
-  { M32RBF_INSN_BNC24, model_m32r_d_bnc24, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
-  { M32RBF_INSN_BNE, model_m32r_d_bne, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
-  { M32RBF_INSN_BRA8, model_m32r_d_bra8, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
-  { M32RBF_INSN_BRA24, model_m32r_d_bra24, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
-  { M32RBF_INSN_CMP, model_m32r_d_cmp, { { (int) UNIT_M32R_D_U_CMP, 1, 1 } } },
-  { M32RBF_INSN_CMPI, model_m32r_d_cmpi, { { (int) UNIT_M32R_D_U_CMP, 1, 1 } } },
-  { M32RBF_INSN_CMPU, model_m32r_d_cmpu, { { (int) UNIT_M32R_D_U_CMP, 1, 1 } } },
-  { M32RBF_INSN_CMPUI, model_m32r_d_cmpui, { { (int) UNIT_M32R_D_U_CMP, 1, 1 } } },
-  { M32RBF_INSN_DIV, model_m32r_d_div, { { (int) UNIT_M32R_D_U_EXEC, 1, 37 } } },
-  { M32RBF_INSN_DIVU, model_m32r_d_divu, { { (int) UNIT_M32R_D_U_EXEC, 1, 37 } } },
-  { M32RBF_INSN_REM, model_m32r_d_rem, { { (int) UNIT_M32R_D_U_EXEC, 1, 37 } } },
-  { M32RBF_INSN_REMU, model_m32r_d_remu, { { (int) UNIT_M32R_D_U_EXEC, 1, 37 } } },
-  { M32RBF_INSN_JL, model_m32r_d_jl, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
-  { M32RBF_INSN_JMP, model_m32r_d_jmp, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
-  { M32RBF_INSN_LD, model_m32r_d_ld, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
-  { M32RBF_INSN_LD_D, model_m32r_d_ld_d, { { (int) UNIT_M32R_D_U_LOAD, 1, 2 } } },
-  { M32RBF_INSN_LDB, model_m32r_d_ldb, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
-  { M32RBF_INSN_LDB_D, model_m32r_d_ldb_d, { { (int) UNIT_M32R_D_U_LOAD, 1, 2 } } },
-  { M32RBF_INSN_LDH, model_m32r_d_ldh, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
-  { M32RBF_INSN_LDH_D, model_m32r_d_ldh_d, { { (int) UNIT_M32R_D_U_LOAD, 1, 2 } } },
-  { M32RBF_INSN_LDUB, model_m32r_d_ldub, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
-  { M32RBF_INSN_LDUB_D, model_m32r_d_ldub_d, { { (int) UNIT_M32R_D_U_LOAD, 1, 2 } } },
-  { M32RBF_INSN_LDUH, model_m32r_d_lduh, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
-  { M32RBF_INSN_LDUH_D, model_m32r_d_lduh_d, { { (int) UNIT_M32R_D_U_LOAD, 1, 2 } } },
-  { M32RBF_INSN_LD_PLUS, model_m32r_d_ld_plus, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 }, { (int) UNIT_M32R_D_U_EXEC, 1, 0 } } },
-  { M32RBF_INSN_LD24, model_m32r_d_ld24, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_LDI8, model_m32r_d_ldi8, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_LDI16, model_m32r_d_ldi16, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_LOCK, model_m32r_d_lock, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
-  { M32RBF_INSN_MACHI, model_m32r_d_machi, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
-  { M32RBF_INSN_MACLO, model_m32r_d_maclo, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
-  { M32RBF_INSN_MACWHI, model_m32r_d_macwhi, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
-  { M32RBF_INSN_MACWLO, model_m32r_d_macwlo, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
-  { M32RBF_INSN_MUL, model_m32r_d_mul, { { (int) UNIT_M32R_D_U_EXEC, 1, 4 } } },
-  { M32RBF_INSN_MULHI, model_m32r_d_mulhi, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
-  { M32RBF_INSN_MULLO, model_m32r_d_mullo, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
-  { M32RBF_INSN_MULWHI, model_m32r_d_mulwhi, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
-  { M32RBF_INSN_MULWLO, model_m32r_d_mulwlo, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
-  { M32RBF_INSN_MV, model_m32r_d_mv, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MVFACHI, model_m32r_d_mvfachi, { { (int) UNIT_M32R_D_U_EXEC, 1, 2 } } },
-  { M32RBF_INSN_MVFACLO, model_m32r_d_mvfaclo, { { (int) UNIT_M32R_D_U_EXEC, 1, 2 } } },
-  { M32RBF_INSN_MVFACMI, model_m32r_d_mvfacmi, { { (int) UNIT_M32R_D_U_EXEC, 1, 2 } } },
-  { M32RBF_INSN_MVFC, model_m32r_d_mvfc, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MVTACHI, model_m32r_d_mvtachi, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MVTACLO, model_m32r_d_mvtaclo, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MVTC, model_m32r_d_mvtc, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_NEG, model_m32r_d_neg, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_NOP, model_m32r_d_nop, { { (int) UNIT_M32R_D_U_EXEC, 1, 0 } } },
-  { M32RBF_INSN_NOT, model_m32r_d_not, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_RAC, model_m32r_d_rac, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
-  { M32RBF_INSN_RACH, model_m32r_d_rach, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
-  { M32RBF_INSN_RTE, model_m32r_d_rte, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SETH, model_m32r_d_seth, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SLL, model_m32r_d_sll, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SLL3, model_m32r_d_sll3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SLLI, model_m32r_d_slli, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SRA, model_m32r_d_sra, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SRA3, model_m32r_d_sra3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SRAI, model_m32r_d_srai, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SRL, model_m32r_d_srl, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SRL3, model_m32r_d_srl3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SRLI, model_m32r_d_srli, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_ST, model_m32r_d_st, { { (int) UNIT_M32R_D_U_STORE, 1, 1 } } },
-  { M32RBF_INSN_ST_D, model_m32r_d_st_d, { { (int) UNIT_M32R_D_U_STORE, 1, 2 } } },
-  { M32RBF_INSN_STB, model_m32r_d_stb, { { (int) UNIT_M32R_D_U_STORE, 1, 1 } } },
-  { M32RBF_INSN_STB_D, model_m32r_d_stb_d, { { (int) UNIT_M32R_D_U_STORE, 1, 2 } } },
-  { M32RBF_INSN_STH, model_m32r_d_sth, { { (int) UNIT_M32R_D_U_STORE, 1, 1 } } },
-  { M32RBF_INSN_STH_D, model_m32r_d_sth_d, { { (int) UNIT_M32R_D_U_STORE, 1, 2 } } },
-  { M32RBF_INSN_ST_PLUS, model_m32r_d_st_plus, { { (int) UNIT_M32R_D_U_STORE, 1, 1 }, { (int) UNIT_M32R_D_U_EXEC, 1, 0 } } },
-  { M32RBF_INSN_ST_MINUS, model_m32r_d_st_minus, { { (int) UNIT_M32R_D_U_STORE, 1, 1 }, { (int) UNIT_M32R_D_U_EXEC, 1, 0 } } },
-  { M32RBF_INSN_SUB, model_m32r_d_sub, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SUBV, model_m32r_d_subv, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SUBX, model_m32r_d_subx, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_TRAP, model_m32r_d_trap, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_UNLOCK, model_m32r_d_unlock, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
-};
-
-/* Model timing data for `test'.  */
-
-static const INSN_TIMING test_timing[] = {
-  { M32RBF_INSN_X_INVALID, 0, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_X_AFTER, 0, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_X_BEFORE, 0, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_X_CHAIN, 0, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_X_BEGIN, 0, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_ADD, model_test_add, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_ADD3, model_test_add3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_AND, model_test_and, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_AND3, model_test_and3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_OR, model_test_or, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_OR3, model_test_or3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_XOR, model_test_xor, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_XOR3, model_test_xor3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_ADDI, model_test_addi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_ADDV, model_test_addv, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_ADDV3, model_test_addv3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_ADDX, model_test_addx, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_BC8, model_test_bc8, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_BC24, model_test_bc24, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_BEQ, model_test_beq, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_BEQZ, model_test_beqz, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_BGEZ, model_test_bgez, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_BGTZ, model_test_bgtz, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_BLEZ, model_test_blez, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_BLTZ, model_test_bltz, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_BNEZ, model_test_bnez, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_BL8, model_test_bl8, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_BL24, model_test_bl24, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_BNC8, model_test_bnc8, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_BNC24, model_test_bnc24, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_BNE, model_test_bne, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_BRA8, model_test_bra8, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_BRA24, model_test_bra24, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_CMP, model_test_cmp, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_CMPI, model_test_cmpi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_CMPU, model_test_cmpu, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_CMPUI, model_test_cmpui, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_DIV, model_test_div, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_DIVU, model_test_divu, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_REM, model_test_rem, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_REMU, model_test_remu, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_JL, model_test_jl, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_JMP, model_test_jmp, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_LD, model_test_ld, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_LD_D, model_test_ld_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_LDB, model_test_ldb, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_LDB_D, model_test_ldb_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_LDH, model_test_ldh, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_LDH_D, model_test_ldh_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_LDUB, model_test_ldub, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_LDUB_D, model_test_ldub_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_LDUH, model_test_lduh, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_LDUH_D, model_test_lduh_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_LD_PLUS, model_test_ld_plus, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_LD24, model_test_ld24, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_LDI8, model_test_ldi8, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_LDI16, model_test_ldi16, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_LOCK, model_test_lock, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MACHI, model_test_machi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MACLO, model_test_maclo, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MACWHI, model_test_macwhi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MACWLO, model_test_macwlo, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MUL, model_test_mul, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MULHI, model_test_mulhi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MULLO, model_test_mullo, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MULWHI, model_test_mulwhi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MULWLO, model_test_mulwlo, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MV, model_test_mv, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MVFACHI, model_test_mvfachi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MVFACLO, model_test_mvfaclo, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MVFACMI, model_test_mvfacmi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MVFC, model_test_mvfc, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MVTACHI, model_test_mvtachi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MVTACLO, model_test_mvtaclo, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MVTC, model_test_mvtc, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_NEG, model_test_neg, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_NOP, model_test_nop, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_NOT, model_test_not, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_RAC, model_test_rac, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_RACH, model_test_rach, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_RTE, model_test_rte, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SETH, model_test_seth, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SLL, model_test_sll, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SLL3, model_test_sll3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SLLI, model_test_slli, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SRA, model_test_sra, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SRA3, model_test_sra3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SRAI, model_test_srai, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SRL, model_test_srl, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SRL3, model_test_srl3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SRLI, model_test_srli, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_ST, model_test_st, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_ST_D, model_test_st_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_STB, model_test_stb, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_STB_D, model_test_stb_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_STH, model_test_sth, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_STH_D, model_test_sth_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_ST_PLUS, model_test_st_plus, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_ST_MINUS, model_test_st_minus, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SUB, model_test_sub, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SUBV, model_test_subv, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SUBX, model_test_subx, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_TRAP, model_test_trap, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_UNLOCK, model_test_unlock, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-};
-
-#endif /* WITH_PROFILE_MODEL_P */
-
-static void
-m32r_d_model_init (SIM_CPU *cpu)
-{
-  CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_M32R_D_DATA));
-}
-
-static void
-test_model_init (SIM_CPU *cpu)
-{
-  CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_TEST_DATA));
-}
-
-#if WITH_PROFILE_MODEL_P
-#define TIMING_DATA(td) td
-#else
-#define TIMING_DATA(td) 0
-#endif
-
-static const MODEL m32r_models[] =
-{
-  { "m32r/d", & m32r_mach, MODEL_M32R_D, TIMING_DATA (& m32r_d_timing[0]), m32r_d_model_init },
-  { "test", & m32r_mach, MODEL_TEST, TIMING_DATA (& test_timing[0]), test_model_init },
-  { 0 }
-};
-
-/* The properties of this cpu's implementation.  */
-
-static const MACH_IMP_PROPERTIES m32rbf_imp_properties =
-{
-  sizeof (SIM_CPU),
-#if WITH_SCACHE
-  sizeof (SCACHE)
-#else
-  0
-#endif
-};
-
-static const CGEN_INSN *
-m32rbf_opcode (SIM_CPU *cpu, int inum)
-{
-  return CPU_IDESC (cpu) [inum].opcode;
-}
-
-static void
-m32r_init_cpu (SIM_CPU *cpu)
-{
-  CPU_REG_FETCH (cpu) = m32rbf_fetch_register;
-  CPU_REG_STORE (cpu) = m32rbf_store_register;
-  CPU_PC_FETCH (cpu) = m32rbf_h_pc_get;
-  CPU_PC_STORE (cpu) = m32rbf_h_pc_set;
-  CPU_OPCODE (cpu) = m32rbf_opcode;
-  CPU_MAX_INSNS (cpu) = M32RBF_INSN_MAX;
-  CPU_INSN_NAME (cpu) = cgen_insn_name;
-  CPU_FULL_ENGINE_FN (cpu) = m32rbf_engine_run_full;
-#if WITH_FAST
-  CPU_FAST_ENGINE_FN (cpu) = m32rbf_engine_run_fast;
-#else
-  CPU_FAST_ENGINE_FN (cpu) = m32rbf_engine_run_full;
-#endif
-  m32rbf_init_idesc_table (cpu);
-}
-
-const MACH m32r_mach =
-{
-  "m32r", "m32r",
-  32, 32, & m32r_models[0], & m32rbf_imp_properties,
-  m32r_init_cpu
-};
-
diff --git a/sim/m32r/modelx.c b/sim/m32r/modelx.c
deleted file mode 100644
index 7ff4ad1..0000000
--- a/sim/m32r/modelx.c
+++ /dev/null
@@ -1,2893 +0,0 @@
-/* Simulator model support for m32rxf.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
-
-This file is part of the GNU Simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#define WANT_CPU m32rxf
-#define WANT_CPU_M32RXF
-
-#include "sim-main.h"
-
-/* The profiling data is recorded here, but is accessed via the profiling
-   mechanism.  After all, this is information for profiling.  */
-
-#if WITH_PROFILE_MODEL_P
-
-/* Model handlers for each insn.  */
-
-static int
-model_m32rx_add (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_add3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_and (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_and3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_and3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_or (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_or3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_or3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_xor (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_xor3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_and3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_addi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_addi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_addv (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_addv.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_addv3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_addv3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_addx (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_addx.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_bc8 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_bc24 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_beq (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_beq.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_beqz (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_bgez (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_bgtz (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_blez (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_bltz (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_bnez (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_bl8 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_bl8.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_bl24 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_bl24.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_bcl8 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_bcl8.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_bcl24 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_bcl24.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_bnc8 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_bnc24 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_bne (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_beq.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_bra8 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_bra8.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_bra24 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_bra24.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_bncl8 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_bcl8.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_bncl24 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_bcl24.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_cmp (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_cmp.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_cmpi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_cmpi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_cmpu (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_cmp.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_cmpui (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_cmpi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_cmpeq (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_cmp.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_cmpz (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_cmpz.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_div (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_div.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_divu (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_div.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_rem (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_div.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_remu (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_div.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_divh (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_div.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_jc (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_jc.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    in_sr = FLD (in_sr);
-    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_jnc (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_jc.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    in_sr = FLD (in_sr);
-    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_jl (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_jl.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    in_sr = FLD (in_sr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_jmp (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    in_sr = FLD (in_sr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_ld (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ld.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_ld_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ld_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_ldb (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ldb.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_ldb_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ldb_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_ldh (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ldh.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_ldh_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ldh_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_ldub (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ldb.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_ldub_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ldb_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_lduh (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ldh.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_lduh_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ldh_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_ld_plus (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_dr = FLD (in_sr);
-    out_dr = FLD (out_sr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_ld24 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ld24.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_ldi8 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ldi8.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_ldi16 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ldi16.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_lock (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_lock.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_machi_a (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_machi_a.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_maclo_a (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_machi_a.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_macwhi_a (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_machi_a.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_macwlo_a (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_machi_a.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_mul (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_mulhi_a (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mulhi_a.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_mullo_a (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mulhi_a.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_mulwhi_a (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mulhi_a.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_mulwlo_a (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mulhi_a.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_mv (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mv.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_mvfachi_a (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mvfachi_a.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_mvfaclo_a (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mvfachi_a.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_mvfacmi_a (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mvfachi_a.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_mvfc (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mvfc.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_mvtachi_a (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mvtachi_a.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_src1);
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_mvtaclo_a (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mvtachi_a.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_src1);
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_mvtc (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mvtc.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    referenced |= 1 << 0;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_neg (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mv.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_nop (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_nop.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_not (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mv.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_rac_dsi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_rac_dsi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_rach_dsi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_rac_dsi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_rte (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_rte.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_seth (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_seth.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_sll (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_sll3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_sll3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_slli (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_slli.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_sra (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_sra3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_sll3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_srai (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_slli.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_srl (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_srl3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_sll3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_srli (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_slli.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_st (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_st.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = 0;
-    INT in_src2 = 0;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_st_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_st_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = 0;
-    INT in_src2 = 0;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_stb (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_stb.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = 0;
-    INT in_src2 = 0;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_stb_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_stb_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = 0;
-    INT in_src2 = 0;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_sth (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_sth.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = 0;
-    INT in_src2 = 0;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_sth_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_sth_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = 0;
-    INT in_src2 = 0;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_st_plus (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = 0;
-    INT in_src2 = 0;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_dr = FLD (in_src2);
-    out_dr = FLD (out_src2);
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_st_minus (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = 0;
-    INT in_src2 = 0;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_dr = FLD (in_src2);
-    out_dr = FLD (out_src2);
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_sub (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_subv (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_addv.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_subx (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_addx.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_trap (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_trap.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_unlock (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_unlock.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_satb (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_satb.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_sath (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_satb.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_sat (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_sat.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_pcmpbz (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_cmpz.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_sadd (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_sadd.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_macwu1 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_macwu1.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_msblo (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_msblo.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_mulwu1 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mulwu1.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_maclh1 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_macwu1.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_sc (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_sc.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_snc (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_sc.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-/* We assume UNIT_NONE == 0 because the tables don't always terminate
-   entries with it.  */
-
-/* Model timing data for `m32rx'.  */
-
-static const INSN_TIMING m32rx_timing[] = {
-  { M32RXF_INSN_X_INVALID, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_X_AFTER, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_X_BEFORE, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_X_CHAIN, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_X_BEGIN, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_ADD, model_m32rx_add, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_ADD3, model_m32rx_add3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_AND, model_m32rx_and, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_AND3, model_m32rx_and3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_OR, model_m32rx_or, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_OR3, model_m32rx_or3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_XOR, model_m32rx_xor, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_XOR3, model_m32rx_xor3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_ADDI, model_m32rx_addi, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_ADDV, model_m32rx_addv, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_ADDV3, model_m32rx_addv3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_ADDX, model_m32rx_addx, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_BC8, model_m32rx_bc8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
-  { M32RXF_INSN_BC24, model_m32rx_bc24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
-  { M32RXF_INSN_BEQ, model_m32rx_beq, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
-  { M32RXF_INSN_BEQZ, model_m32rx_beqz, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
-  { M32RXF_INSN_BGEZ, model_m32rx_bgez, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
-  { M32RXF_INSN_BGTZ, model_m32rx_bgtz, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
-  { M32RXF_INSN_BLEZ, model_m32rx_blez, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
-  { M32RXF_INSN_BLTZ, model_m32rx_bltz, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
-  { M32RXF_INSN_BNEZ, model_m32rx_bnez, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
-  { M32RXF_INSN_BL8, model_m32rx_bl8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
-  { M32RXF_INSN_BL24, model_m32rx_bl24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
-  { M32RXF_INSN_BCL8, model_m32rx_bcl8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
-  { M32RXF_INSN_BCL24, model_m32rx_bcl24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
-  { M32RXF_INSN_BNC8, model_m32rx_bnc8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
-  { M32RXF_INSN_BNC24, model_m32rx_bnc24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
-  { M32RXF_INSN_BNE, model_m32rx_bne, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
-  { M32RXF_INSN_BRA8, model_m32rx_bra8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
-  { M32RXF_INSN_BRA24, model_m32rx_bra24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
-  { M32RXF_INSN_BNCL8, model_m32rx_bncl8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
-  { M32RXF_INSN_BNCL24, model_m32rx_bncl24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
-  { M32RXF_INSN_CMP, model_m32rx_cmp, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
-  { M32RXF_INSN_CMPI, model_m32rx_cmpi, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
-  { M32RXF_INSN_CMPU, model_m32rx_cmpu, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
-  { M32RXF_INSN_CMPUI, model_m32rx_cmpui, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
-  { M32RXF_INSN_CMPEQ, model_m32rx_cmpeq, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
-  { M32RXF_INSN_CMPZ, model_m32rx_cmpz, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
-  { M32RXF_INSN_DIV, model_m32rx_div, { { (int) UNIT_M32RX_U_EXEC, 1, 37 } } },
-  { M32RXF_INSN_DIVU, model_m32rx_divu, { { (int) UNIT_M32RX_U_EXEC, 1, 37 } } },
-  { M32RXF_INSN_REM, model_m32rx_rem, { { (int) UNIT_M32RX_U_EXEC, 1, 37 } } },
-  { M32RXF_INSN_REMU, model_m32rx_remu, { { (int) UNIT_M32RX_U_EXEC, 1, 37 } } },
-  { M32RXF_INSN_DIVH, model_m32rx_divh, { { (int) UNIT_M32RX_U_EXEC, 1, 21 } } },
-  { M32RXF_INSN_JC, model_m32rx_jc, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
-  { M32RXF_INSN_JNC, model_m32rx_jnc, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
-  { M32RXF_INSN_JL, model_m32rx_jl, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
-  { M32RXF_INSN_JMP, model_m32rx_jmp, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
-  { M32RXF_INSN_LD, model_m32rx_ld, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
-  { M32RXF_INSN_LD_D, model_m32rx_ld_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } },
-  { M32RXF_INSN_LDB, model_m32rx_ldb, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
-  { M32RXF_INSN_LDB_D, model_m32rx_ldb_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } },
-  { M32RXF_INSN_LDH, model_m32rx_ldh, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
-  { M32RXF_INSN_LDH_D, model_m32rx_ldh_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } },
-  { M32RXF_INSN_LDUB, model_m32rx_ldub, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
-  { M32RXF_INSN_LDUB_D, model_m32rx_ldub_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } },
-  { M32RXF_INSN_LDUH, model_m32rx_lduh, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
-  { M32RXF_INSN_LDUH_D, model_m32rx_lduh_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } },
-  { M32RXF_INSN_LD_PLUS, model_m32rx_ld_plus, { { (int) UNIT_M32RX_U_LOAD, 1, 1 }, { (int) UNIT_M32RX_U_EXEC, 1, 0 } } },
-  { M32RXF_INSN_LD24, model_m32rx_ld24, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_LDI8, model_m32rx_ldi8, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_LDI16, model_m32rx_ldi16, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_LOCK, model_m32rx_lock, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
-  { M32RXF_INSN_MACHI_A, model_m32rx_machi_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
-  { M32RXF_INSN_MACLO_A, model_m32rx_maclo_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
-  { M32RXF_INSN_MACWHI_A, model_m32rx_macwhi_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
-  { M32RXF_INSN_MACWLO_A, model_m32rx_macwlo_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
-  { M32RXF_INSN_MUL, model_m32rx_mul, { { (int) UNIT_M32RX_U_EXEC, 1, 4 } } },
-  { M32RXF_INSN_MULHI_A, model_m32rx_mulhi_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
-  { M32RXF_INSN_MULLO_A, model_m32rx_mullo_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
-  { M32RXF_INSN_MULWHI_A, model_m32rx_mulwhi_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
-  { M32RXF_INSN_MULWLO_A, model_m32rx_mulwlo_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
-  { M32RXF_INSN_MV, model_m32rx_mv, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_MVFACHI_A, model_m32rx_mvfachi_a, { { (int) UNIT_M32RX_U_EXEC, 1, 2 } } },
-  { M32RXF_INSN_MVFACLO_A, model_m32rx_mvfaclo_a, { { (int) UNIT_M32RX_U_EXEC, 1, 2 } } },
-  { M32RXF_INSN_MVFACMI_A, model_m32rx_mvfacmi_a, { { (int) UNIT_M32RX_U_EXEC, 1, 2 } } },
-  { M32RXF_INSN_MVFC, model_m32rx_mvfc, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_MVTACHI_A, model_m32rx_mvtachi_a, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_MVTACLO_A, model_m32rx_mvtaclo_a, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_MVTC, model_m32rx_mvtc, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_NEG, model_m32rx_neg, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_NOP, model_m32rx_nop, { { (int) UNIT_M32RX_U_EXEC, 1, 0 } } },
-  { M32RXF_INSN_NOT, model_m32rx_not, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_RAC_DSI, model_m32rx_rac_dsi, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
-  { M32RXF_INSN_RACH_DSI, model_m32rx_rach_dsi, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
-  { M32RXF_INSN_RTE, model_m32rx_rte, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_SETH, model_m32rx_seth, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_SLL, model_m32rx_sll, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_SLL3, model_m32rx_sll3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_SLLI, model_m32rx_slli, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_SRA, model_m32rx_sra, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_SRA3, model_m32rx_sra3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_SRAI, model_m32rx_srai, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_SRL, model_m32rx_srl, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_SRL3, model_m32rx_srl3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_SRLI, model_m32rx_srli, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_ST, model_m32rx_st, { { (int) UNIT_M32RX_U_STORE, 1, 1 } } },
-  { M32RXF_INSN_ST_D, model_m32rx_st_d, { { (int) UNIT_M32RX_U_STORE, 1, 2 } } },
-  { M32RXF_INSN_STB, model_m32rx_stb, { { (int) UNIT_M32RX_U_STORE, 1, 1 } } },
-  { M32RXF_INSN_STB_D, model_m32rx_stb_d, { { (int) UNIT_M32RX_U_STORE, 1, 2 } } },
-  { M32RXF_INSN_STH, model_m32rx_sth, { { (int) UNIT_M32RX_U_STORE, 1, 1 } } },
-  { M32RXF_INSN_STH_D, model_m32rx_sth_d, { { (int) UNIT_M32RX_U_STORE, 1, 2 } } },
-  { M32RXF_INSN_ST_PLUS, model_m32rx_st_plus, { { (int) UNIT_M32RX_U_STORE, 1, 1 }, { (int) UNIT_M32RX_U_EXEC, 1, 0 } } },
-  { M32RXF_INSN_ST_MINUS, model_m32rx_st_minus, { { (int) UNIT_M32RX_U_STORE, 1, 1 }, { (int) UNIT_M32RX_U_EXEC, 1, 0 } } },
-  { M32RXF_INSN_SUB, model_m32rx_sub, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_SUBV, model_m32rx_subv, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_SUBX, model_m32rx_subx, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_TRAP, model_m32rx_trap, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_UNLOCK, model_m32rx_unlock, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
-  { M32RXF_INSN_SATB, model_m32rx_satb, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_SATH, model_m32rx_sath, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_SAT, model_m32rx_sat, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_PCMPBZ, model_m32rx_pcmpbz, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
-  { M32RXF_INSN_SADD, model_m32rx_sadd, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
-  { M32RXF_INSN_MACWU1, model_m32rx_macwu1, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
-  { M32RXF_INSN_MSBLO, model_m32rx_msblo, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
-  { M32RXF_INSN_MULWU1, model_m32rx_mulwu1, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
-  { M32RXF_INSN_MACLH1, model_m32rx_maclh1, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
-  { M32RXF_INSN_SC, model_m32rx_sc, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_SNC, model_m32rx_snc, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-};
-
-#endif /* WITH_PROFILE_MODEL_P */
-
-static void
-m32rx_model_init (SIM_CPU *cpu)
-{
-  CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_M32RX_DATA));
-}
-
-#if WITH_PROFILE_MODEL_P
-#define TIMING_DATA(td) td
-#else
-#define TIMING_DATA(td) 0
-#endif
-
-static const MODEL m32rx_models[] =
-{
-  { "m32rx", & m32rx_mach, MODEL_M32RX, TIMING_DATA (& m32rx_timing[0]), m32rx_model_init },
-  { 0 }
-};
-
-/* The properties of this cpu's implementation.  */
-
-static const MACH_IMP_PROPERTIES m32rxf_imp_properties =
-{
-  sizeof (SIM_CPU),
-#if WITH_SCACHE
-  sizeof (SCACHE)
-#else
-  0
-#endif
-};
-
-static const CGEN_INSN *
-m32rxf_opcode (SIM_CPU *cpu, int inum)
-{
-  return CPU_IDESC (cpu) [inum].opcode;
-}
-
-/* start-sanitize-m32rx */
-static void
-m32rx_init_cpu (SIM_CPU *cpu)
-{
-  CPU_REG_FETCH (cpu) = m32rxf_fetch_register;
-  CPU_REG_STORE (cpu) = m32rxf_store_register;
-  CPU_PC_FETCH (cpu) = m32rxf_h_pc_get;
-  CPU_PC_STORE (cpu) = m32rxf_h_pc_set;
-  CPU_OPCODE (cpu) = m32rxf_opcode;
-  CPU_MAX_INSNS (cpu) = M32RXF_INSN_MAX;
-  CPU_INSN_NAME (cpu) = cgen_insn_name;
-  CPU_FULL_ENGINE_FN (cpu) = m32rxf_engine_run_full;
-#if WITH_FAST
-  CPU_FAST_ENGINE_FN (cpu) = m32rxf_engine_run_fast;
-#else
-  CPU_FAST_ENGINE_FN (cpu) = m32rxf_engine_run_full;
-#endif
-  m32rxf_init_idesc_table (cpu);
-}
-
-const MACH m32rx_mach =
-{
-  "m32rx", "m32rx",
-  32, 32, & m32rx_models[0], & m32rxf_imp_properties,
-  m32rx_init_cpu
-};
-
-/* end-sanitize-m32rx */
diff --git a/sim/m32r/sem-switch.c b/sim/m32r/sem-switch.c
deleted file mode 100644
index 1ee0b60..0000000
--- a/sim/m32r/sem-switch.c
+++ /dev/null
@@ -1,2503 +0,0 @@
-/* Simulator instruction semantics for m32rbf.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
-
-This file is part of the GNU Simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#ifdef DEFINE_LABELS
-
-  /* The labels have the case they have because the enum of insn types
-     is all uppercase and in the non-stdc case the insn symbol is built
-     into the enum name.  */
-
-  static struct {
-    int index;
-    void *label;
-  } labels[] = {
-    { M32RBF_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
-    { M32RBF_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
-    { M32RBF_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
-    { M32RBF_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
-    { M32RBF_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
-    { M32RBF_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
-    { M32RBF_INSN_ADD, && case_sem_INSN_ADD },
-    { M32RBF_INSN_ADD3, && case_sem_INSN_ADD3 },
-    { M32RBF_INSN_AND, && case_sem_INSN_AND },
-    { M32RBF_INSN_AND3, && case_sem_INSN_AND3 },
-    { M32RBF_INSN_OR, && case_sem_INSN_OR },
-    { M32RBF_INSN_OR3, && case_sem_INSN_OR3 },
-    { M32RBF_INSN_XOR, && case_sem_INSN_XOR },
-    { M32RBF_INSN_XOR3, && case_sem_INSN_XOR3 },
-    { M32RBF_INSN_ADDI, && case_sem_INSN_ADDI },
-    { M32RBF_INSN_ADDV, && case_sem_INSN_ADDV },
-    { M32RBF_INSN_ADDV3, && case_sem_INSN_ADDV3 },
-    { M32RBF_INSN_ADDX, && case_sem_INSN_ADDX },
-    { M32RBF_INSN_BC8, && case_sem_INSN_BC8 },
-    { M32RBF_INSN_BC24, && case_sem_INSN_BC24 },
-    { M32RBF_INSN_BEQ, && case_sem_INSN_BEQ },
-    { M32RBF_INSN_BEQZ, && case_sem_INSN_BEQZ },
-    { M32RBF_INSN_BGEZ, && case_sem_INSN_BGEZ },
-    { M32RBF_INSN_BGTZ, && case_sem_INSN_BGTZ },
-    { M32RBF_INSN_BLEZ, && case_sem_INSN_BLEZ },
-    { M32RBF_INSN_BLTZ, && case_sem_INSN_BLTZ },
-    { M32RBF_INSN_BNEZ, && case_sem_INSN_BNEZ },
-    { M32RBF_INSN_BL8, && case_sem_INSN_BL8 },
-    { M32RBF_INSN_BL24, && case_sem_INSN_BL24 },
-    { M32RBF_INSN_BNC8, && case_sem_INSN_BNC8 },
-    { M32RBF_INSN_BNC24, && case_sem_INSN_BNC24 },
-    { M32RBF_INSN_BNE, && case_sem_INSN_BNE },
-    { M32RBF_INSN_BRA8, && case_sem_INSN_BRA8 },
-    { M32RBF_INSN_BRA24, && case_sem_INSN_BRA24 },
-    { M32RBF_INSN_CMP, && case_sem_INSN_CMP },
-    { M32RBF_INSN_CMPI, && case_sem_INSN_CMPI },
-    { M32RBF_INSN_CMPU, && case_sem_INSN_CMPU },
-    { M32RBF_INSN_CMPUI, && case_sem_INSN_CMPUI },
-    { M32RBF_INSN_DIV, && case_sem_INSN_DIV },
-    { M32RBF_INSN_DIVU, && case_sem_INSN_DIVU },
-    { M32RBF_INSN_REM, && case_sem_INSN_REM },
-    { M32RBF_INSN_REMU, && case_sem_INSN_REMU },
-    { M32RBF_INSN_JL, && case_sem_INSN_JL },
-    { M32RBF_INSN_JMP, && case_sem_INSN_JMP },
-    { M32RBF_INSN_LD, && case_sem_INSN_LD },
-    { M32RBF_INSN_LD_D, && case_sem_INSN_LD_D },
-    { M32RBF_INSN_LDB, && case_sem_INSN_LDB },
-    { M32RBF_INSN_LDB_D, && case_sem_INSN_LDB_D },
-    { M32RBF_INSN_LDH, && case_sem_INSN_LDH },
-    { M32RBF_INSN_LDH_D, && case_sem_INSN_LDH_D },
-    { M32RBF_INSN_LDUB, && case_sem_INSN_LDUB },
-    { M32RBF_INSN_LDUB_D, && case_sem_INSN_LDUB_D },
-    { M32RBF_INSN_LDUH, && case_sem_INSN_LDUH },
-    { M32RBF_INSN_LDUH_D, && case_sem_INSN_LDUH_D },
-    { M32RBF_INSN_LD_PLUS, && case_sem_INSN_LD_PLUS },
-    { M32RBF_INSN_LD24, && case_sem_INSN_LD24 },
-    { M32RBF_INSN_LDI8, && case_sem_INSN_LDI8 },
-    { M32RBF_INSN_LDI16, && case_sem_INSN_LDI16 },
-    { M32RBF_INSN_LOCK, && case_sem_INSN_LOCK },
-    { M32RBF_INSN_MACHI, && case_sem_INSN_MACHI },
-    { M32RBF_INSN_MACLO, && case_sem_INSN_MACLO },
-    { M32RBF_INSN_MACWHI, && case_sem_INSN_MACWHI },
-    { M32RBF_INSN_MACWLO, && case_sem_INSN_MACWLO },
-    { M32RBF_INSN_MUL, && case_sem_INSN_MUL },
-    { M32RBF_INSN_MULHI, && case_sem_INSN_MULHI },
-    { M32RBF_INSN_MULLO, && case_sem_INSN_MULLO },
-    { M32RBF_INSN_MULWHI, && case_sem_INSN_MULWHI },
-    { M32RBF_INSN_MULWLO, && case_sem_INSN_MULWLO },
-    { M32RBF_INSN_MV, && case_sem_INSN_MV },
-    { M32RBF_INSN_MVFACHI, && case_sem_INSN_MVFACHI },
-    { M32RBF_INSN_MVFACLO, && case_sem_INSN_MVFACLO },
-    { M32RBF_INSN_MVFACMI, && case_sem_INSN_MVFACMI },
-    { M32RBF_INSN_MVFC, && case_sem_INSN_MVFC },
-    { M32RBF_INSN_MVTACHI, && case_sem_INSN_MVTACHI },
-    { M32RBF_INSN_MVTACLO, && case_sem_INSN_MVTACLO },
-    { M32RBF_INSN_MVTC, && case_sem_INSN_MVTC },
-    { M32RBF_INSN_NEG, && case_sem_INSN_NEG },
-    { M32RBF_INSN_NOP, && case_sem_INSN_NOP },
-    { M32RBF_INSN_NOT, && case_sem_INSN_NOT },
-    { M32RBF_INSN_RAC, && case_sem_INSN_RAC },
-    { M32RBF_INSN_RACH, && case_sem_INSN_RACH },
-    { M32RBF_INSN_RTE, && case_sem_INSN_RTE },
-    { M32RBF_INSN_SETH, && case_sem_INSN_SETH },
-    { M32RBF_INSN_SLL, && case_sem_INSN_SLL },
-    { M32RBF_INSN_SLL3, && case_sem_INSN_SLL3 },
-    { M32RBF_INSN_SLLI, && case_sem_INSN_SLLI },
-    { M32RBF_INSN_SRA, && case_sem_INSN_SRA },
-    { M32RBF_INSN_SRA3, && case_sem_INSN_SRA3 },
-    { M32RBF_INSN_SRAI, && case_sem_INSN_SRAI },
-    { M32RBF_INSN_SRL, && case_sem_INSN_SRL },
-    { M32RBF_INSN_SRL3, && case_sem_INSN_SRL3 },
-    { M32RBF_INSN_SRLI, && case_sem_INSN_SRLI },
-    { M32RBF_INSN_ST, && case_sem_INSN_ST },
-    { M32RBF_INSN_ST_D, && case_sem_INSN_ST_D },
-    { M32RBF_INSN_STB, && case_sem_INSN_STB },
-    { M32RBF_INSN_STB_D, && case_sem_INSN_STB_D },
-    { M32RBF_INSN_STH, && case_sem_INSN_STH },
-    { M32RBF_INSN_STH_D, && case_sem_INSN_STH_D },
-    { M32RBF_INSN_ST_PLUS, && case_sem_INSN_ST_PLUS },
-    { M32RBF_INSN_ST_MINUS, && case_sem_INSN_ST_MINUS },
-    { M32RBF_INSN_SUB, && case_sem_INSN_SUB },
-    { M32RBF_INSN_SUBV, && case_sem_INSN_SUBV },
-    { M32RBF_INSN_SUBX, && case_sem_INSN_SUBX },
-    { M32RBF_INSN_TRAP, && case_sem_INSN_TRAP },
-    { M32RBF_INSN_UNLOCK, && case_sem_INSN_UNLOCK },
-    { 0, 0 }
-  };
-  int i;
-
-  for (i = 0; labels[i].label != 0; ++i)
-#if FAST_P
-    CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
-#else
-    CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
-#endif
-
-#undef DEFINE_LABELS
-#endif /* DEFINE_LABELS */
-
-#ifdef DEFINE_SWITCH
-
-/* If hyper-fast [well not unnecessarily slow] execution is selected, turn
-   off frills like tracing and profiling.  */
-/* FIXME: A better way would be to have TRACE_RESULT check for something
-   that can cause it to be optimized out.  Another way would be to emit
-   special handlers into the instruction "stream".  */
-
-#if FAST_P
-#undef TRACE_RESULT
-#define TRACE_RESULT(cpu, abuf, name, type, val)
-#endif
-
-#undef GET_ATTR
-#define GET_ATTR(cpu, num, attr) CGEN_INSN_ATTR (abuf->idesc->opcode, CGEN_INSN_##attr)
-
-{
-
-#if WITH_SCACHE_PBB
-
-/* Branch to next handler without going around main loop.  */
-#define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
-SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
-
-#else /* ! WITH_SCACHE_PBB */
-
-#define NEXT(vpc) BREAK (sem)
-#ifdef __GNUC__
-#if FAST_P
-  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
-#else
-  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
-#endif
-#else
-  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
-#endif
-
-#endif /* ! WITH_SCACHE_PBB */
-
-    {
-
-  CASE (sem, INSN_X_INVALID) : /* --invalid-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE
-    /* Update the recorded pc in the cpu state struct.  */
-    SET_H_PC (pc);
-#endif
-    sim_engine_invalid_insn (current_cpu, pc);
-    sim_io_error (CPU_STATE (current_cpu), "invalid insn not handled\n");
-    /* NOTREACHED */
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_X_AFTER) : /* --after-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_M32RBF
-    m32rbf_pbb_after (current_cpu, sem_arg);
-#endif
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_X_BEFORE) : /* --before-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_M32RBF
-    m32rbf_pbb_before (current_cpu, sem_arg);
-#endif
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_M32RBF
-#ifdef DEFINE_SWITCH
-    vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg,
-			       pbb_br_npc_ptr, pbb_br_npc);
-    BREAK (sem);
-#else
-    /* FIXME: Allow provision of explicit ifmt spec in insn spec.  */
-    vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg,
-			       CPU_PBB_BR_NPC_PTR (current_cpu),
-			       CPU_PBB_BR_NPC (current_cpu));
-#endif
-#endif
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_X_CHAIN) : /* --chain-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_M32RBF
-    vpc = m32rbf_pbb_chain (current_cpu, sem_arg);
-#ifdef DEFINE_SWITCH
-    BREAK (sem);
-#endif
-#endif
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_X_BEGIN) : /* --begin-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_M32RBF
-#ifdef DEFINE_SWITCH
-    /* In the switch case FAST_P is a constant, allowing several optimizations
-       in any called inline functions.  */
-    vpc = m32rbf_pbb_begin (current_cpu, FAST_P);
-#else
-    vpc = m32rbf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
-#endif
-#endif
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ADD) : /* add $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_add.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ADDSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ADD3) : /* add3 $dr,$sr,$hash$slo16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_add3.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = ADDSI (* FLD (i_sr), FLD (f_simm16));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_AND) : /* and $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_add.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ANDSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_AND3) : /* and3 $dr,$sr,$uimm16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_and3.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = ANDSI (* FLD (i_sr), FLD (f_uimm16));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_OR) : /* or $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_add.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ORSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_OR3) : /* or3 $dr,$sr,$hash$ulo16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_or3.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = ORSI (* FLD (i_sr), FLD (f_uimm16));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_XOR) : /* xor $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_add.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = XORSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_XOR3) : /* xor3 $dr,$sr,$uimm16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_and3.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = XORSI (* FLD (i_sr), FLD (f_uimm16));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ADDI) : /* addi $dr,$simm8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_addi.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ADDSI (* FLD (i_dr), FLD (f_simm8));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ADDV) : /* addv $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_addv.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  BI temp1;SI temp0;
-  temp0 = ADDSI (* FLD (i_dr), * FLD (i_sr));
-  temp1 = ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0);
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
-  }
-} while (0);
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ADDV3) : /* addv3 $dr,$sr,$simm16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_addv3.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-do {
-  BI temp1;SI temp0;
-  temp0 = ADDSI (* FLD (i_sr), FLD (f_simm16));
-  temp1 = ADDOFSI (* FLD (i_sr), FLD (f_simm16), 0);
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
-  }
-} while (0);
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ADDX) : /* addx $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_addx.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  BI temp1;SI temp0;
-  temp0 = ADDCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
-  temp1 = ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
-  }
-} while (0);
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BC8) : /* bc.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (CPU (h_cond)) {
-  {
-    USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BC24) : /* bc.l $disp24 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (CPU (h_cond)) {
-  {
-    USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BEQ) : /* beq $src1,$src2,$disp16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_beq.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (EQSI (* FLD (i_src1), * FLD (i_src2))) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BEQZ) : /* beqz $src2,$disp16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (EQSI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BGEZ) : /* bgez $src2,$disp16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (GESI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BGTZ) : /* bgtz $src2,$disp16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (GTSI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BLEZ) : /* blez $src2,$disp16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (LESI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BLTZ) : /* bltz $src2,$disp16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (LTSI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BNEZ) : /* bnez $src2,$disp16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BL8) : /* bl.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_bl8.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  {
-    SI opval = ADDSI (ANDSI (pc, -4), 4);
-    CPU (h_gr[((UINT) 14)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
-  }
-  {
-    USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-} while (0);
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BL24) : /* bl.l $disp24 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_bl24.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-do {
-  {
-    SI opval = ADDSI (pc, 4);
-    CPU (h_gr[((UINT) 14)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
-  }
-  {
-    USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-} while (0);
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BNC8) : /* bnc.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (CPU (h_cond))) {
-  {
-    USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BNC24) : /* bnc.l $disp24 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NOTBI (CPU (h_cond))) {
-  {
-    USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BNE) : /* bne $src1,$src2,$disp16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_beq.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_src1), * FLD (i_src2))) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BRA8) : /* bra.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_bra8.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BRA24) : /* bra.l $disp24 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_bra24.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CMP) : /* cmp $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_cmp.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = LTSI (* FLD (i_src1), * FLD (i_src2));
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CMPI) : /* cmpi $src2,$simm16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_cmpi.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    BI opval = LTSI (* FLD (i_src2), FLD (f_simm16));
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CMPU) : /* cmpu $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_cmp.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = LTUSI (* FLD (i_src1), * FLD (i_src2));
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CMPUI) : /* cmpui $src2,$simm16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_cmpi.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    BI opval = LTUSI (* FLD (i_src2), FLD (f_simm16));
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_DIV) : /* div $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_div.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_sr), 0)) {
-  {
-    SI opval = DIVSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_DIVU) : /* divu $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_div.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_sr), 0)) {
-  {
-    SI opval = UDIVSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_REM) : /* rem $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_div.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_sr), 0)) {
-  {
-    SI opval = MODSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_REMU) : /* remu $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_div.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_sr), 0)) {
-  {
-    SI opval = UMODSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_JL) : /* jl $sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_jl.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  USI temp1;SI temp0;
-  temp0 = ADDSI (ANDSI (pc, -4), 4);
-  temp1 = ANDSI (* FLD (i_sr), -4);
-  {
-    SI opval = temp0;
-    CPU (h_gr[((UINT) 14)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
-  }
-  {
-    USI opval = temp1;
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-} while (0);
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_JMP) : /* jmp $sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    USI opval = ANDSI (* FLD (i_sr), -4);
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LD) : /* ld $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ld.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LD_D) : /* ld $dr,@($slo16,$sr) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ld_d.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = GETMEMSI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDB) : /* ldb $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ldb.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDB_D) : /* ldb $dr,@($slo16,$sr) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ldb_d.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDH) : /* ldh $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ldh.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDH_D) : /* ldh $dr,@($slo16,$sr) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ldh_d.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDUB) : /* ldub $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ldb.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDUB_D) : /* ldub $dr,@($slo16,$sr) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ldb_d.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDUH) : /* lduh $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ldh.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDUH_D) : /* lduh $dr,@($slo16,$sr) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ldh_d.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LD_PLUS) : /* ld $dr,@$sr+ */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ld_plus.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  SI temp1;SI temp0;
-  temp0 = GETMEMSI (current_cpu, pc, * FLD (i_sr));
-  temp1 = ADDSI (* FLD (i_sr), 4);
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-  {
-    SI opval = temp1;
-    * FLD (i_sr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
-  }
-} while (0);
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LD24) : /* ld24 $dr,$uimm24 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ld24.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = FLD (i_uimm24);
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDI8) : /* ldi8 $dr,$simm8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ldi8.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = FLD (f_simm8);
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDI16) : /* ldi16 $dr,$hash$slo16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ldi16.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = FLD (f_simm16);
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LOCK) : /* lock $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_lock.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  {
-    BI opval = 1;
-    CPU (h_lock) = opval;
-    TRACE_RESULT (current_cpu, abuf, "lock-0", 'x', opval);
-  }
-  {
-    SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-} while (0);
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MACHI) : /* machi $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_machi.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (ADDDI (m32rbf_h_accum_get (current_cpu), MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8);
-    m32rbf_h_accum_set (current_cpu, opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MACLO) : /* maclo $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_machi.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (ADDDI (m32rbf_h_accum_get (current_cpu), MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8);
-    m32rbf_h_accum_set (current_cpu, opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MACWHI) : /* macwhi $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_machi.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (ADDDI (m32rbf_h_accum_get (current_cpu), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8);
-    m32rbf_h_accum_set (current_cpu, opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MACWLO) : /* macwlo $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_machi.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (ADDDI (m32rbf_h_accum_get (current_cpu), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8);
-    m32rbf_h_accum_set (current_cpu, opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MUL) : /* mul $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_add.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = MULSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MULHI) : /* mulhi $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mulhi.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 16), 16);
-    m32rbf_h_accum_set (current_cpu, opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MULLO) : /* mullo $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mulhi.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 16), 16);
-    m32rbf_h_accum_set (current_cpu, opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MULWHI) : /* mulwhi $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mulhi.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 8), 8);
-    m32rbf_h_accum_set (current_cpu, opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MULWLO) : /* mulwlo $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mulhi.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 8), 8);
-    m32rbf_h_accum_set (current_cpu, opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MV) : /* mv $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mv.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = * FLD (i_sr);
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MVFACHI) : /* mvfachi $dr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mvfachi.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = TRUNCDISI (SRADI (m32rbf_h_accum_get (current_cpu), 32));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MVFACLO) : /* mvfaclo $dr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mvfachi.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = TRUNCDISI (m32rbf_h_accum_get (current_cpu));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MVFACMI) : /* mvfacmi $dr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mvfachi.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = TRUNCDISI (SRADI (m32rbf_h_accum_get (current_cpu), 16));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MVFC) : /* mvfc $dr,$scr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mvfc.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = m32rbf_h_cr_get (current_cpu, FLD (f_r2));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MVTACHI) : /* mvtachi $src1 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mvtachi.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ORDI (ANDDI (m32rbf_h_accum_get (current_cpu), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (i_src1)), 32));
-    m32rbf_h_accum_set (current_cpu, opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MVTACLO) : /* mvtaclo $src1 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mvtachi.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ORDI (ANDDI (m32rbf_h_accum_get (current_cpu), MAKEDI (0xffffffff, 0)), ZEXTSIDI (* FLD (i_src1)));
-    m32rbf_h_accum_set (current_cpu, opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MVTC) : /* mvtc $sr,$dcr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mvtc.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    USI opval = * FLD (i_sr);
-    m32rbf_h_cr_set (current_cpu, FLD (f_r1), opval);
-    TRACE_RESULT (current_cpu, abuf, "dcr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_NEG) : /* neg $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mv.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = NEGSI (* FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_NOP) : /* nop */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_nop.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_NOT) : /* not $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mv.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = INVSI (* FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_RAC) : /* rac */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_rac.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  DI tmp_tmp1;
-  tmp_tmp1 = SLLDI (m32rbf_h_accum_get (current_cpu), 1);
-  tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768));
-  {
-    DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000)));
-    m32rbf_h_accum_set (current_cpu, opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-} while (0);
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_RACH) : /* rach */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_rac.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  DI tmp_tmp1;
-  tmp_tmp1 = ANDDI (m32rbf_h_accum_get (current_cpu), MAKEDI (16777215, 0xffffffff));
-if (ANDIF (GEDI (tmp_tmp1, MAKEDI (16383, 0x80000000)), LEDI (tmp_tmp1, MAKEDI (8388607, 0xffffffff)))) {
-  tmp_tmp1 = MAKEDI (16383, 0x80000000);
-} else {
-if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760832, 0)))) {
-  tmp_tmp1 = MAKEDI (16760832, 0);
-} else {
-  tmp_tmp1 = ANDDI (ADDDI (m32rbf_h_accum_get (current_cpu), MAKEDI (0, 1073741824)), MAKEDI (0xffffffff, 0x80000000));
-}
-}
-  tmp_tmp1 = SLLDI (tmp_tmp1, 1);
-  {
-    DI opval = SRADI (SLLDI (tmp_tmp1, 7), 7);
-    m32rbf_h_accum_set (current_cpu, opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-} while (0);
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_RTE) : /* rte */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_rte.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  {
-    USI opval = ANDSI (m32rbf_h_cr_get (current_cpu, ((UINT) 6)), -4);
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-  {
-    USI opval = m32rbf_h_cr_get (current_cpu, ((UINT) 14));
-    m32rbf_h_cr_set (current_cpu, ((UINT) 6), opval);
-    TRACE_RESULT (current_cpu, abuf, "cr-6", 'x', opval);
-  }
-  {
-    UQI opval = CPU (h_bpsw);
-    m32rbf_h_psw_set (current_cpu, opval);
-    TRACE_RESULT (current_cpu, abuf, "psw-0", 'x', opval);
-  }
-  {
-    UQI opval = CPU (h_bbpsw);
-    CPU (h_bpsw) = opval;
-    TRACE_RESULT (current_cpu, abuf, "bpsw-0", 'x', opval);
-  }
-} while (0);
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SETH) : /* seth $dr,$hash$hi16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_seth.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = SLLSI (FLD (f_hi16), 16);
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SLL) : /* sll $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_add.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SLLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SLL3) : /* sll3 $dr,$sr,$simm16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_sll3.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = SLLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SLLI) : /* slli $dr,$uimm5 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_slli.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SLLSI (* FLD (i_dr), FLD (f_uimm5));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SRA) : /* sra $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_add.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRASI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SRA3) : /* sra3 $dr,$sr,$simm16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_sll3.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = SRASI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SRAI) : /* srai $dr,$uimm5 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_slli.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRASI (* FLD (i_dr), FLD (f_uimm5));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SRL) : /* srl $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_add.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SRL3) : /* srl3 $dr,$sr,$simm16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_sll3.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = SRLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SRLI) : /* srli $dr,$uimm5 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_slli.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRLSI (* FLD (i_dr), FLD (f_uimm5));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ST) : /* st $src1,@$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_st.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = * FLD (i_src1);
-    SETMEMSI (current_cpu, pc, * FLD (i_src2), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ST_D) : /* st $src1,@($slo16,$src2) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_st_d.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = * FLD (i_src1);
-    SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STB) : /* stb $src1,@$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_stb.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    QI opval = * FLD (i_src1);
-    SETMEMQI (current_cpu, pc, * FLD (i_src2), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STB_D) : /* stb $src1,@($slo16,$src2) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_stb_d.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    QI opval = * FLD (i_src1);
-    SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STH) : /* sth $src1,@$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_sth.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    HI opval = * FLD (i_src1);
-    SETMEMHI (current_cpu, pc, * FLD (i_src2), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STH_D) : /* sth $src1,@($slo16,$src2) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_sth_d.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    HI opval = * FLD (i_src1);
-    SETMEMHI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ST_PLUS) : /* st $src1,@+$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_st_plus.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  SI tmp_new_src2;
-  tmp_new_src2 = ADDSI (* FLD (i_src2), 4);
-  {
-    SI opval = * FLD (i_src1);
-    SETMEMSI (current_cpu, pc, tmp_new_src2, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  {
-    SI opval = tmp_new_src2;
-    * FLD (i_src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "src2", 'x', opval);
-  }
-} while (0);
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ST_MINUS) : /* st $src1,@-$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_st_plus.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  SI tmp_new_src2;
-  tmp_new_src2 = SUBSI (* FLD (i_src2), 4);
-  {
-    SI opval = * FLD (i_src1);
-    SETMEMSI (current_cpu, pc, tmp_new_src2, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  {
-    SI opval = tmp_new_src2;
-    * FLD (i_src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "src2", 'x', opval);
-  }
-} while (0);
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SUB) : /* sub $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_add.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SUBSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SUBV) : /* subv $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_addv.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  BI temp1;SI temp0;
-  temp0 = SUBSI (* FLD (i_dr), * FLD (i_sr));
-  temp1 = SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0);
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
-  }
-} while (0);
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SUBX) : /* subx $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_addx.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  BI temp1;SI temp0;
-  temp0 = SUBCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
-  temp1 = SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
-  }
-} while (0);
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_TRAP) : /* trap $uimm4 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_trap.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  {
-    USI opval = m32rbf_h_cr_get (current_cpu, ((UINT) 6));
-    m32rbf_h_cr_set (current_cpu, ((UINT) 14), opval);
-    TRACE_RESULT (current_cpu, abuf, "cr-14", 'x', opval);
-  }
-  {
-    USI opval = ADDSI (pc, 4);
-    m32rbf_h_cr_set (current_cpu, ((UINT) 6), opval);
-    TRACE_RESULT (current_cpu, abuf, "cr-6", 'x', opval);
-  }
-  {
-    UQI opval = CPU (h_bpsw);
-    CPU (h_bbpsw) = opval;
-    TRACE_RESULT (current_cpu, abuf, "bbpsw-0", 'x', opval);
-  }
-  {
-    UQI opval = m32rbf_h_psw_get (current_cpu);
-    CPU (h_bpsw) = opval;
-    TRACE_RESULT (current_cpu, abuf, "bpsw-0", 'x', opval);
-  }
-  {
-    UQI opval = ANDQI (m32rbf_h_psw_get (current_cpu), 128);
-    m32rbf_h_psw_set (current_cpu, opval);
-    TRACE_RESULT (current_cpu, abuf, "psw-0", 'x', opval);
-  }
-  {
-    SI opval = m32r_trap (current_cpu, pc, FLD (f_uimm4));
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-} while (0);
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_UNLOCK) : /* unlock $src1,@$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_unlock.f
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-if (CPU (h_lock)) {
-  {
-    SI opval = * FLD (i_src1);
-    SETMEMSI (current_cpu, pc, * FLD (i_src2), opval);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-}
-  {
-    BI opval = 0;
-    CPU (h_lock) = opval;
-    TRACE_RESULT (current_cpu, abuf, "lock-0", 'x', opval);
-  }
-} while (0);
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-
-    }
-  ENDSWITCH (sem) /* End of semantic switch.  */
-
-  /* At this point `vpc' contains the next insn to execute.  */
-}
-
-#undef DEFINE_SWITCH
-#endif /* DEFINE_SWITCH */
diff --git a/sim/m32r/sem.c b/sim/m32r/sem.c
deleted file mode 100644
index 93466c8..0000000
--- a/sim/m32r/sem.c
+++ /dev/null
@@ -1,2544 +0,0 @@
-/* Simulator instruction semantics for m32rbf.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
-
-This file is part of the GNU Simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#define WANT_CPU m32rbf
-#define WANT_CPU_M32RBF
-
-#include "sim-main.h"
-#include "cgen-mem.h"
-#include "cgen-ops.h"
-
-#undef GET_ATTR
-#define GET_ATTR(cpu, num, attr) CGEN_INSN_ATTR (abuf->idesc->opcode, CGEN_INSN_##attr)
-
-/* x-invalid: --invalid-- */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE
-    /* Update the recorded pc in the cpu state struct.  */
-    SET_H_PC (pc);
-#endif
-    sim_engine_invalid_insn (current_cpu, pc);
-    sim_io_error (CPU_STATE (current_cpu), "invalid insn not handled\n");
-    /* NOTREACHED */
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* x-after: --after-- */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,x_after) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_M32RBF
-    m32rbf_pbb_after (current_cpu, sem_arg);
-#endif
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* x-before: --before-- */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_M32RBF
-    m32rbf_pbb_before (current_cpu, sem_arg);
-#endif
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* x-cti-chain: --cti-chain-- */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_M32RBF
-#ifdef DEFINE_SWITCH
-    vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg,
-			       pbb_br_npc_ptr, pbb_br_npc);
-    BREAK (sem);
-#else
-    /* FIXME: Allow provision of explicit ifmt spec in insn spec.  */
-    vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg,
-			       CPU_PBB_BR_NPC_PTR (current_cpu),
-			       CPU_PBB_BR_NPC (current_cpu));
-#endif
-#endif
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* x-chain: --chain-- */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,x_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_M32RBF
-    vpc = m32rbf_pbb_chain (current_cpu, sem_arg);
-#ifdef DEFINE_SWITCH
-    BREAK (sem);
-#endif
-#endif
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* x-begin: --begin-- */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_M32RBF
-#ifdef DEFINE_SWITCH
-    /* In the switch case FAST_P is a constant, allowing several optimizations
-       in any called inline functions.  */
-    vpc = m32rbf_pbb_begin (current_cpu, FAST_P);
-#else
-    vpc = m32rbf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
-#endif
-#endif
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* add: add $dr,$sr */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,add) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ADDSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* add3: add3 $dr,$sr,$hash$slo16 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,add3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_add3.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = ADDSI (* FLD (i_sr), FLD (f_simm16));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* and: and $dr,$sr */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,and) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ANDSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* and3: and3 $dr,$sr,$uimm16 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,and3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_and3.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = ANDSI (* FLD (i_sr), FLD (f_uimm16));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* or: or $dr,$sr */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,or) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ORSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* or3: or3 $dr,$sr,$hash$ulo16 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,or3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_or3.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = ORSI (* FLD (i_sr), FLD (f_uimm16));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* xor: xor $dr,$sr */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,xor) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = XORSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* xor3: xor3 $dr,$sr,$uimm16 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,xor3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_and3.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = XORSI (* FLD (i_sr), FLD (f_uimm16));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* addi: addi $dr,$simm8 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,addi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_addi.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ADDSI (* FLD (i_dr), FLD (f_simm8));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* addv: addv $dr,$sr */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,addv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_addv.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  BI temp1;SI temp0;
-  temp0 = ADDSI (* FLD (i_dr), * FLD (i_sr));
-  temp1 = ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0);
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
-  }
-} while (0);
-
-  return vpc;
-#undef FLD
-}
-
-/* addv3: addv3 $dr,$sr,$simm16 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,addv3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_addv3.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-do {
-  BI temp1;SI temp0;
-  temp0 = ADDSI (* FLD (i_sr), FLD (f_simm16));
-  temp1 = ADDOFSI (* FLD (i_sr), FLD (f_simm16), 0);
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
-  }
-} while (0);
-
-  return vpc;
-#undef FLD
-}
-
-/* addx: addx $dr,$sr */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,addx) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_addx.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  BI temp1;SI temp0;
-  temp0 = ADDCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
-  temp1 = ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
-  }
-} while (0);
-
-  return vpc;
-#undef FLD
-}
-
-/* bc8: bc.s $disp8 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,bc8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (CPU (h_cond)) {
-  {
-    USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* bc24: bc.l $disp24 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,bc24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (CPU (h_cond)) {
-  {
-    USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* beq: beq $src1,$src2,$disp16 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,beq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_beq.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (EQSI (* FLD (i_src1), * FLD (i_src2))) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* beqz: beqz $src2,$disp16 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,beqz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (EQSI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* bgez: bgez $src2,$disp16 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,bgez) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (GESI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* bgtz: bgtz $src2,$disp16 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,bgtz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (GTSI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* blez: blez $src2,$disp16 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,blez) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (LESI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* bltz: bltz $src2,$disp16 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,bltz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (LTSI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* bnez: bnez $src2,$disp16 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,bnez) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* bl8: bl.s $disp8 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,bl8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_bl8.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  {
-    SI opval = ADDSI (ANDSI (pc, -4), 4);
-    CPU (h_gr[((UINT) 14)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
-  }
-  {
-    USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-} while (0);
-
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* bl24: bl.l $disp24 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,bl24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_bl24.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-do {
-  {
-    SI opval = ADDSI (pc, 4);
-    CPU (h_gr[((UINT) 14)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
-  }
-  {
-    USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-} while (0);
-
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* bnc8: bnc.s $disp8 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,bnc8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (CPU (h_cond))) {
-  {
-    USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* bnc24: bnc.l $disp24 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,bnc24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NOTBI (CPU (h_cond))) {
-  {
-    USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* bne: bne $src1,$src2,$disp16 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,bne) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_beq.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_src1), * FLD (i_src2))) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* bra8: bra.s $disp8 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,bra8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_bra8.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* bra24: bra.l $disp24 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,bra24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_bra24.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* cmp: cmp $src1,$src2 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,cmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_cmp.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = LTSI (* FLD (i_src1), * FLD (i_src2));
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* cmpi: cmpi $src2,$simm16 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,cmpi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_cmpi.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    BI opval = LTSI (* FLD (i_src2), FLD (f_simm16));
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* cmpu: cmpu $src1,$src2 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,cmpu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_cmp.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = LTUSI (* FLD (i_src1), * FLD (i_src2));
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* cmpui: cmpui $src2,$simm16 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,cmpui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_cmpi.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    BI opval = LTUSI (* FLD (i_src2), FLD (f_simm16));
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* div: div $dr,$sr */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,div) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_div.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_sr), 0)) {
-  {
-    SI opval = DIVSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* divu: divu $dr,$sr */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,divu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_div.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_sr), 0)) {
-  {
-    SI opval = UDIVSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* rem: rem $dr,$sr */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,rem) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_div.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_sr), 0)) {
-  {
-    SI opval = MODSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* remu: remu $dr,$sr */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,remu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_div.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_sr), 0)) {
-  {
-    SI opval = UMODSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* jl: jl $sr */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,jl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_jl.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  USI temp1;SI temp0;
-  temp0 = ADDSI (ANDSI (pc, -4), 4);
-  temp1 = ANDSI (* FLD (i_sr), -4);
-  {
-    SI opval = temp0;
-    CPU (h_gr[((UINT) 14)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
-  }
-  {
-    USI opval = temp1;
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-} while (0);
-
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* jmp: jmp $sr */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,jmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    USI opval = ANDSI (* FLD (i_sr), -4);
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* ld: ld $dr,@$sr */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,ld) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ld.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ld-d: ld $dr,@($slo16,$sr) */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,ld_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ld_d.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = GETMEMSI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ldb: ldb $dr,@$sr */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,ldb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ldb.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ldb-d: ldb $dr,@($slo16,$sr) */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,ldb_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ldb_d.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ldh: ldh $dr,@$sr */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,ldh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ldh.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ldh-d: ldh $dr,@($slo16,$sr) */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,ldh_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ldh_d.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ldub: ldub $dr,@$sr */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,ldub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ldb.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ldub-d: ldub $dr,@($slo16,$sr) */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,ldub_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ldb_d.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* lduh: lduh $dr,@$sr */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,lduh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ldh.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* lduh-d: lduh $dr,@($slo16,$sr) */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,lduh_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ldh_d.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ld-plus: ld $dr,@$sr+ */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,ld_plus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ld_plus.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  SI temp1;SI temp0;
-  temp0 = GETMEMSI (current_cpu, pc, * FLD (i_sr));
-  temp1 = ADDSI (* FLD (i_sr), 4);
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-  {
-    SI opval = temp1;
-    * FLD (i_sr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
-  }
-} while (0);
-
-  return vpc;
-#undef FLD
-}
-
-/* ld24: ld24 $dr,$uimm24 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,ld24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ld24.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = FLD (i_uimm24);
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ldi8: ldi8 $dr,$simm8 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,ldi8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ldi8.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = FLD (f_simm8);
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ldi16: ldi16 $dr,$hash$slo16 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,ldi16) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_ldi16.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = FLD (f_simm16);
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* lock: lock $dr,@$sr */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,lock) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_lock.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  {
-    BI opval = 1;
-    CPU (h_lock) = opval;
-    TRACE_RESULT (current_cpu, abuf, "lock-0", 'x', opval);
-  }
-  {
-    SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-} while (0);
-
-  return vpc;
-#undef FLD
-}
-
-/* machi: machi $src1,$src2 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,machi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_machi.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (ADDDI (m32rbf_h_accum_get (current_cpu), MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8);
-    m32rbf_h_accum_set (current_cpu, opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* maclo: maclo $src1,$src2 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,maclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_machi.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (ADDDI (m32rbf_h_accum_get (current_cpu), MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8);
-    m32rbf_h_accum_set (current_cpu, opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* macwhi: macwhi $src1,$src2 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,macwhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_machi.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (ADDDI (m32rbf_h_accum_get (current_cpu), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8);
-    m32rbf_h_accum_set (current_cpu, opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* macwlo: macwlo $src1,$src2 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,macwlo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_machi.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (ADDDI (m32rbf_h_accum_get (current_cpu), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8);
-    m32rbf_h_accum_set (current_cpu, opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* mul: mul $dr,$sr */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,mul) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = MULSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* mulhi: mulhi $src1,$src2 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,mulhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mulhi.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 16), 16);
-    m32rbf_h_accum_set (current_cpu, opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* mullo: mullo $src1,$src2 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,mullo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mulhi.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 16), 16);
-    m32rbf_h_accum_set (current_cpu, opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* mulwhi: mulwhi $src1,$src2 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,mulwhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mulhi.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 8), 8);
-    m32rbf_h_accum_set (current_cpu, opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* mulwlo: mulwlo $src1,$src2 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,mulwlo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mulhi.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 8), 8);
-    m32rbf_h_accum_set (current_cpu, opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* mv: mv $dr,$sr */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,mv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mv.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = * FLD (i_sr);
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* mvfachi: mvfachi $dr */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,mvfachi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mvfachi.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = TRUNCDISI (SRADI (m32rbf_h_accum_get (current_cpu), 32));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* mvfaclo: mvfaclo $dr */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,mvfaclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mvfachi.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = TRUNCDISI (m32rbf_h_accum_get (current_cpu));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* mvfacmi: mvfacmi $dr */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,mvfacmi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mvfachi.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = TRUNCDISI (SRADI (m32rbf_h_accum_get (current_cpu), 16));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* mvfc: mvfc $dr,$scr */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,mvfc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mvfc.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = m32rbf_h_cr_get (current_cpu, FLD (f_r2));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* mvtachi: mvtachi $src1 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,mvtachi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mvtachi.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ORDI (ANDDI (m32rbf_h_accum_get (current_cpu), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (i_src1)), 32));
-    m32rbf_h_accum_set (current_cpu, opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* mvtaclo: mvtaclo $src1 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,mvtaclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mvtachi.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ORDI (ANDDI (m32rbf_h_accum_get (current_cpu), MAKEDI (0xffffffff, 0)), ZEXTSIDI (* FLD (i_src1)));
-    m32rbf_h_accum_set (current_cpu, opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* mvtc: mvtc $sr,$dcr */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,mvtc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mvtc.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    USI opval = * FLD (i_sr);
-    m32rbf_h_cr_set (current_cpu, FLD (f_r1), opval);
-    TRACE_RESULT (current_cpu, abuf, "dcr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* neg: neg $dr,$sr */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,neg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mv.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = NEGSI (* FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* nop: nop */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,nop) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_nop.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
-
-  return vpc;
-#undef FLD
-}
-
-/* not: not $dr,$sr */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,not) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_mv.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = INVSI (* FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* rac: rac */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,rac) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_rac.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  DI tmp_tmp1;
-  tmp_tmp1 = SLLDI (m32rbf_h_accum_get (current_cpu), 1);
-  tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768));
-  {
-    DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000)));
-    m32rbf_h_accum_set (current_cpu, opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-} while (0);
-
-  return vpc;
-#undef FLD
-}
-
-/* rach: rach */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,rach) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_rac.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  DI tmp_tmp1;
-  tmp_tmp1 = ANDDI (m32rbf_h_accum_get (current_cpu), MAKEDI (16777215, 0xffffffff));
-if (ANDIF (GEDI (tmp_tmp1, MAKEDI (16383, 0x80000000)), LEDI (tmp_tmp1, MAKEDI (8388607, 0xffffffff)))) {
-  tmp_tmp1 = MAKEDI (16383, 0x80000000);
-} else {
-if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760832, 0)))) {
-  tmp_tmp1 = MAKEDI (16760832, 0);
-} else {
-  tmp_tmp1 = ANDDI (ADDDI (m32rbf_h_accum_get (current_cpu), MAKEDI (0, 1073741824)), MAKEDI (0xffffffff, 0x80000000));
-}
-}
-  tmp_tmp1 = SLLDI (tmp_tmp1, 1);
-  {
-    DI opval = SRADI (SLLDI (tmp_tmp1, 7), 7);
-    m32rbf_h_accum_set (current_cpu, opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-} while (0);
-
-  return vpc;
-#undef FLD
-}
-
-/* rte: rte */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,rte) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_rte.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  {
-    USI opval = ANDSI (m32rbf_h_cr_get (current_cpu, ((UINT) 6)), -4);
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-  {
-    USI opval = m32rbf_h_cr_get (current_cpu, ((UINT) 14));
-    m32rbf_h_cr_set (current_cpu, ((UINT) 6), opval);
-    TRACE_RESULT (current_cpu, abuf, "cr-6", 'x', opval);
-  }
-  {
-    UQI opval = CPU (h_bpsw);
-    m32rbf_h_psw_set (current_cpu, opval);
-    TRACE_RESULT (current_cpu, abuf, "psw-0", 'x', opval);
-  }
-  {
-    UQI opval = CPU (h_bbpsw);
-    CPU (h_bpsw) = opval;
-    TRACE_RESULT (current_cpu, abuf, "bpsw-0", 'x', opval);
-  }
-} while (0);
-
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* seth: seth $dr,$hash$hi16 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,seth) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_seth.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = SLLSI (FLD (f_hi16), 16);
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* sll: sll $dr,$sr */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,sll) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SLLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* sll3: sll3 $dr,$sr,$simm16 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,sll3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_sll3.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = SLLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* slli: slli $dr,$uimm5 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,slli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_slli.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SLLSI (* FLD (i_dr), FLD (f_uimm5));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* sra: sra $dr,$sr */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,sra) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRASI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* sra3: sra3 $dr,$sr,$simm16 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,sra3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_sll3.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = SRASI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* srai: srai $dr,$uimm5 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,srai) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_slli.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRASI (* FLD (i_dr), FLD (f_uimm5));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* srl: srl $dr,$sr */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,srl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* srl3: srl3 $dr,$sr,$simm16 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,srl3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_sll3.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = SRLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* srli: srli $dr,$uimm5 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,srli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_slli.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRLSI (* FLD (i_dr), FLD (f_uimm5));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* st: st $src1,@$src2 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,st) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_st.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = * FLD (i_src1);
-    SETMEMSI (current_cpu, pc, * FLD (i_src2), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* st-d: st $src1,@($slo16,$src2) */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,st_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_st_d.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = * FLD (i_src1);
-    SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* stb: stb $src1,@$src2 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,stb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_stb.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    QI opval = * FLD (i_src1);
-    SETMEMQI (current_cpu, pc, * FLD (i_src2), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* stb-d: stb $src1,@($slo16,$src2) */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,stb_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_stb_d.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    QI opval = * FLD (i_src1);
-    SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* sth: sth $src1,@$src2 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,sth) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_sth.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    HI opval = * FLD (i_src1);
-    SETMEMHI (current_cpu, pc, * FLD (i_src2), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* sth-d: sth $src1,@($slo16,$src2) */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,sth_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_sth_d.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    HI opval = * FLD (i_src1);
-    SETMEMHI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* st-plus: st $src1,@+$src2 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,st_plus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_st_plus.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  SI tmp_new_src2;
-  tmp_new_src2 = ADDSI (* FLD (i_src2), 4);
-  {
-    SI opval = * FLD (i_src1);
-    SETMEMSI (current_cpu, pc, tmp_new_src2, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  {
-    SI opval = tmp_new_src2;
-    * FLD (i_src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "src2", 'x', opval);
-  }
-} while (0);
-
-  return vpc;
-#undef FLD
-}
-
-/* st-minus: st $src1,@-$src2 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,st_minus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_st_plus.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  SI tmp_new_src2;
-  tmp_new_src2 = SUBSI (* FLD (i_src2), 4);
-  {
-    SI opval = * FLD (i_src1);
-    SETMEMSI (current_cpu, pc, tmp_new_src2, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  {
-    SI opval = tmp_new_src2;
-    * FLD (i_src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "src2", 'x', opval);
-  }
-} while (0);
-
-  return vpc;
-#undef FLD
-}
-
-/* sub: sub $dr,$sr */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,sub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SUBSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* subv: subv $dr,$sr */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,subv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_addv.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  BI temp1;SI temp0;
-  temp0 = SUBSI (* FLD (i_dr), * FLD (i_sr));
-  temp1 = SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0);
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
-  }
-} while (0);
-
-  return vpc;
-#undef FLD
-}
-
-/* subx: subx $dr,$sr */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,subx) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_addx.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  BI temp1;SI temp0;
-  temp0 = SUBCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
-  temp1 = SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
-  }
-} while (0);
-
-  return vpc;
-#undef FLD
-}
-
-/* trap: trap $uimm4 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,trap) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.cti.fields.fmt_trap.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  {
-    USI opval = m32rbf_h_cr_get (current_cpu, ((UINT) 6));
-    m32rbf_h_cr_set (current_cpu, ((UINT) 14), opval);
-    TRACE_RESULT (current_cpu, abuf, "cr-14", 'x', opval);
-  }
-  {
-    USI opval = ADDSI (pc, 4);
-    m32rbf_h_cr_set (current_cpu, ((UINT) 6), opval);
-    TRACE_RESULT (current_cpu, abuf, "cr-6", 'x', opval);
-  }
-  {
-    UQI opval = CPU (h_bpsw);
-    CPU (h_bbpsw) = opval;
-    TRACE_RESULT (current_cpu, abuf, "bbpsw-0", 'x', opval);
-  }
-  {
-    UQI opval = m32rbf_h_psw_get (current_cpu);
-    CPU (h_bpsw) = opval;
-    TRACE_RESULT (current_cpu, abuf, "bpsw-0", 'x', opval);
-  }
-  {
-    UQI opval = ANDQI (m32rbf_h_psw_get (current_cpu), 128);
-    m32rbf_h_psw_set (current_cpu, opval);
-    TRACE_RESULT (current_cpu, abuf, "psw-0", 'x', opval);
-  }
-  {
-    SI opval = m32r_trap (current_cpu, pc, FLD (f_uimm4));
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-} while (0);
-
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* unlock: unlock $src1,@$src2 */
-
-SEM_PC
-SEM_FN_NAME (m32rbf,unlock) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_unlock.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  PCADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-if (CPU (h_lock)) {
-  {
-    SI opval = * FLD (i_src1);
-    SETMEMSI (current_cpu, pc, * FLD (i_src2), opval);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-}
-  {
-    BI opval = 0;
-    CPU (h_lock) = opval;
-    TRACE_RESULT (current_cpu, abuf, "lock-0", 'x', opval);
-  }
-} while (0);
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
diff --git a/sim/m32r/semx-switch.c b/sim/m32r/semx-switch.c
deleted file mode 100644
index ef3c490..0000000
--- a/sim/m32r/semx-switch.c
+++ /dev/null
@@ -1,6274 +0,0 @@
-/* Simulator instruction semantics for m32rxf.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
-
-This file is part of the GNU Simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#ifdef DEFINE_LABELS
-
-  /* The labels have the case they have because the enum of insn types
-     is all uppercase and in the non-stdc case the insn symbol is built
-     into the enum name.  */
-
-  static struct {
-    int index;
-    void *label;
-  } labels[] = {
-    { M32RXF_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
-    { M32RXF_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
-    { M32RXF_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
-    { M32RXF_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
-    { M32RXF_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
-    { M32RXF_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
-    { M32RXF_INSN_ADD, && case_sem_INSN_ADD },
-    { M32RXF_INSN_ADD3, && case_sem_INSN_ADD3 },
-    { M32RXF_INSN_AND, && case_sem_INSN_AND },
-    { M32RXF_INSN_AND3, && case_sem_INSN_AND3 },
-    { M32RXF_INSN_OR, && case_sem_INSN_OR },
-    { M32RXF_INSN_OR3, && case_sem_INSN_OR3 },
-    { M32RXF_INSN_XOR, && case_sem_INSN_XOR },
-    { M32RXF_INSN_XOR3, && case_sem_INSN_XOR3 },
-    { M32RXF_INSN_ADDI, && case_sem_INSN_ADDI },
-    { M32RXF_INSN_ADDV, && case_sem_INSN_ADDV },
-    { M32RXF_INSN_ADDV3, && case_sem_INSN_ADDV3 },
-    { M32RXF_INSN_ADDX, && case_sem_INSN_ADDX },
-    { M32RXF_INSN_BC8, && case_sem_INSN_BC8 },
-    { M32RXF_INSN_BC24, && case_sem_INSN_BC24 },
-    { M32RXF_INSN_BEQ, && case_sem_INSN_BEQ },
-    { M32RXF_INSN_BEQZ, && case_sem_INSN_BEQZ },
-    { M32RXF_INSN_BGEZ, && case_sem_INSN_BGEZ },
-    { M32RXF_INSN_BGTZ, && case_sem_INSN_BGTZ },
-    { M32RXF_INSN_BLEZ, && case_sem_INSN_BLEZ },
-    { M32RXF_INSN_BLTZ, && case_sem_INSN_BLTZ },
-    { M32RXF_INSN_BNEZ, && case_sem_INSN_BNEZ },
-    { M32RXF_INSN_BL8, && case_sem_INSN_BL8 },
-    { M32RXF_INSN_BL24, && case_sem_INSN_BL24 },
-    { M32RXF_INSN_BCL8, && case_sem_INSN_BCL8 },
-    { M32RXF_INSN_BCL24, && case_sem_INSN_BCL24 },
-    { M32RXF_INSN_BNC8, && case_sem_INSN_BNC8 },
-    { M32RXF_INSN_BNC24, && case_sem_INSN_BNC24 },
-    { M32RXF_INSN_BNE, && case_sem_INSN_BNE },
-    { M32RXF_INSN_BRA8, && case_sem_INSN_BRA8 },
-    { M32RXF_INSN_BRA24, && case_sem_INSN_BRA24 },
-    { M32RXF_INSN_BNCL8, && case_sem_INSN_BNCL8 },
-    { M32RXF_INSN_BNCL24, && case_sem_INSN_BNCL24 },
-    { M32RXF_INSN_CMP, && case_sem_INSN_CMP },
-    { M32RXF_INSN_CMPI, && case_sem_INSN_CMPI },
-    { M32RXF_INSN_CMPU, && case_sem_INSN_CMPU },
-    { M32RXF_INSN_CMPUI, && case_sem_INSN_CMPUI },
-    { M32RXF_INSN_CMPEQ, && case_sem_INSN_CMPEQ },
-    { M32RXF_INSN_CMPZ, && case_sem_INSN_CMPZ },
-    { M32RXF_INSN_DIV, && case_sem_INSN_DIV },
-    { M32RXF_INSN_DIVU, && case_sem_INSN_DIVU },
-    { M32RXF_INSN_REM, && case_sem_INSN_REM },
-    { M32RXF_INSN_REMU, && case_sem_INSN_REMU },
-    { M32RXF_INSN_DIVH, && case_sem_INSN_DIVH },
-    { M32RXF_INSN_JC, && case_sem_INSN_JC },
-    { M32RXF_INSN_JNC, && case_sem_INSN_JNC },
-    { M32RXF_INSN_JL, && case_sem_INSN_JL },
-    { M32RXF_INSN_JMP, && case_sem_INSN_JMP },
-    { M32RXF_INSN_LD, && case_sem_INSN_LD },
-    { M32RXF_INSN_LD_D, && case_sem_INSN_LD_D },
-    { M32RXF_INSN_LDB, && case_sem_INSN_LDB },
-    { M32RXF_INSN_LDB_D, && case_sem_INSN_LDB_D },
-    { M32RXF_INSN_LDH, && case_sem_INSN_LDH },
-    { M32RXF_INSN_LDH_D, && case_sem_INSN_LDH_D },
-    { M32RXF_INSN_LDUB, && case_sem_INSN_LDUB },
-    { M32RXF_INSN_LDUB_D, && case_sem_INSN_LDUB_D },
-    { M32RXF_INSN_LDUH, && case_sem_INSN_LDUH },
-    { M32RXF_INSN_LDUH_D, && case_sem_INSN_LDUH_D },
-    { M32RXF_INSN_LD_PLUS, && case_sem_INSN_LD_PLUS },
-    { M32RXF_INSN_LD24, && case_sem_INSN_LD24 },
-    { M32RXF_INSN_LDI8, && case_sem_INSN_LDI8 },
-    { M32RXF_INSN_LDI16, && case_sem_INSN_LDI16 },
-    { M32RXF_INSN_LOCK, && case_sem_INSN_LOCK },
-    { M32RXF_INSN_MACHI_A, && case_sem_INSN_MACHI_A },
-    { M32RXF_INSN_MACLO_A, && case_sem_INSN_MACLO_A },
-    { M32RXF_INSN_MACWHI_A, && case_sem_INSN_MACWHI_A },
-    { M32RXF_INSN_MACWLO_A, && case_sem_INSN_MACWLO_A },
-    { M32RXF_INSN_MUL, && case_sem_INSN_MUL },
-    { M32RXF_INSN_MULHI_A, && case_sem_INSN_MULHI_A },
-    { M32RXF_INSN_MULLO_A, && case_sem_INSN_MULLO_A },
-    { M32RXF_INSN_MULWHI_A, && case_sem_INSN_MULWHI_A },
-    { M32RXF_INSN_MULWLO_A, && case_sem_INSN_MULWLO_A },
-    { M32RXF_INSN_MV, && case_sem_INSN_MV },
-    { M32RXF_INSN_MVFACHI_A, && case_sem_INSN_MVFACHI_A },
-    { M32RXF_INSN_MVFACLO_A, && case_sem_INSN_MVFACLO_A },
-    { M32RXF_INSN_MVFACMI_A, && case_sem_INSN_MVFACMI_A },
-    { M32RXF_INSN_MVFC, && case_sem_INSN_MVFC },
-    { M32RXF_INSN_MVTACHI_A, && case_sem_INSN_MVTACHI_A },
-    { M32RXF_INSN_MVTACLO_A, && case_sem_INSN_MVTACLO_A },
-    { M32RXF_INSN_MVTC, && case_sem_INSN_MVTC },
-    { M32RXF_INSN_NEG, && case_sem_INSN_NEG },
-    { M32RXF_INSN_NOP, && case_sem_INSN_NOP },
-    { M32RXF_INSN_NOT, && case_sem_INSN_NOT },
-    { M32RXF_INSN_RAC_DSI, && case_sem_INSN_RAC_DSI },
-    { M32RXF_INSN_RACH_DSI, && case_sem_INSN_RACH_DSI },
-    { M32RXF_INSN_RTE, && case_sem_INSN_RTE },
-    { M32RXF_INSN_SETH, && case_sem_INSN_SETH },
-    { M32RXF_INSN_SLL, && case_sem_INSN_SLL },
-    { M32RXF_INSN_SLL3, && case_sem_INSN_SLL3 },
-    { M32RXF_INSN_SLLI, && case_sem_INSN_SLLI },
-    { M32RXF_INSN_SRA, && case_sem_INSN_SRA },
-    { M32RXF_INSN_SRA3, && case_sem_INSN_SRA3 },
-    { M32RXF_INSN_SRAI, && case_sem_INSN_SRAI },
-    { M32RXF_INSN_SRL, && case_sem_INSN_SRL },
-    { M32RXF_INSN_SRL3, && case_sem_INSN_SRL3 },
-    { M32RXF_INSN_SRLI, && case_sem_INSN_SRLI },
-    { M32RXF_INSN_ST, && case_sem_INSN_ST },
-    { M32RXF_INSN_ST_D, && case_sem_INSN_ST_D },
-    { M32RXF_INSN_STB, && case_sem_INSN_STB },
-    { M32RXF_INSN_STB_D, && case_sem_INSN_STB_D },
-    { M32RXF_INSN_STH, && case_sem_INSN_STH },
-    { M32RXF_INSN_STH_D, && case_sem_INSN_STH_D },
-    { M32RXF_INSN_ST_PLUS, && case_sem_INSN_ST_PLUS },
-    { M32RXF_INSN_ST_MINUS, && case_sem_INSN_ST_MINUS },
-    { M32RXF_INSN_SUB, && case_sem_INSN_SUB },
-    { M32RXF_INSN_SUBV, && case_sem_INSN_SUBV },
-    { M32RXF_INSN_SUBX, && case_sem_INSN_SUBX },
-    { M32RXF_INSN_TRAP, && case_sem_INSN_TRAP },
-    { M32RXF_INSN_UNLOCK, && case_sem_INSN_UNLOCK },
-    { M32RXF_INSN_SATB, && case_sem_INSN_SATB },
-    { M32RXF_INSN_SATH, && case_sem_INSN_SATH },
-    { M32RXF_INSN_SAT, && case_sem_INSN_SAT },
-    { M32RXF_INSN_PCMPBZ, && case_sem_INSN_PCMPBZ },
-    { M32RXF_INSN_SADD, && case_sem_INSN_SADD },
-    { M32RXF_INSN_MACWU1, && case_sem_INSN_MACWU1 },
-    { M32RXF_INSN_MSBLO, && case_sem_INSN_MSBLO },
-    { M32RXF_INSN_MULWU1, && case_sem_INSN_MULWU1 },
-    { M32RXF_INSN_MACLH1, && case_sem_INSN_MACLH1 },
-    { M32RXF_INSN_SC, && case_sem_INSN_SC },
-    { M32RXF_INSN_SNC, && case_sem_INSN_SNC },
-    { M32RXF_INSN_PAR_ADD, && case_sem_INSN_PAR_ADD },
-    { M32RXF_INSN_WRITE_ADD, && case_sem_INSN_WRITE_ADD },
-    { M32RXF_INSN_PAR_AND, && case_sem_INSN_PAR_AND },
-    { M32RXF_INSN_WRITE_AND, && case_sem_INSN_WRITE_AND },
-    { M32RXF_INSN_PAR_OR, && case_sem_INSN_PAR_OR },
-    { M32RXF_INSN_WRITE_OR, && case_sem_INSN_WRITE_OR },
-    { M32RXF_INSN_PAR_XOR, && case_sem_INSN_PAR_XOR },
-    { M32RXF_INSN_WRITE_XOR, && case_sem_INSN_WRITE_XOR },
-    { M32RXF_INSN_PAR_ADDI, && case_sem_INSN_PAR_ADDI },
-    { M32RXF_INSN_WRITE_ADDI, && case_sem_INSN_WRITE_ADDI },
-    { M32RXF_INSN_PAR_ADDV, && case_sem_INSN_PAR_ADDV },
-    { M32RXF_INSN_WRITE_ADDV, && case_sem_INSN_WRITE_ADDV },
-    { M32RXF_INSN_PAR_ADDX, && case_sem_INSN_PAR_ADDX },
-    { M32RXF_INSN_WRITE_ADDX, && case_sem_INSN_WRITE_ADDX },
-    { M32RXF_INSN_PAR_BC8, && case_sem_INSN_PAR_BC8 },
-    { M32RXF_INSN_WRITE_BC8, && case_sem_INSN_WRITE_BC8 },
-    { M32RXF_INSN_PAR_BL8, && case_sem_INSN_PAR_BL8 },
-    { M32RXF_INSN_WRITE_BL8, && case_sem_INSN_WRITE_BL8 },
-    { M32RXF_INSN_PAR_BCL8, && case_sem_INSN_PAR_BCL8 },
-    { M32RXF_INSN_WRITE_BCL8, && case_sem_INSN_WRITE_BCL8 },
-    { M32RXF_INSN_PAR_BNC8, && case_sem_INSN_PAR_BNC8 },
-    { M32RXF_INSN_WRITE_BNC8, && case_sem_INSN_WRITE_BNC8 },
-    { M32RXF_INSN_PAR_BRA8, && case_sem_INSN_PAR_BRA8 },
-    { M32RXF_INSN_WRITE_BRA8, && case_sem_INSN_WRITE_BRA8 },
-    { M32RXF_INSN_PAR_BNCL8, && case_sem_INSN_PAR_BNCL8 },
-    { M32RXF_INSN_WRITE_BNCL8, && case_sem_INSN_WRITE_BNCL8 },
-    { M32RXF_INSN_PAR_CMP, && case_sem_INSN_PAR_CMP },
-    { M32RXF_INSN_WRITE_CMP, && case_sem_INSN_WRITE_CMP },
-    { M32RXF_INSN_PAR_CMPU, && case_sem_INSN_PAR_CMPU },
-    { M32RXF_INSN_WRITE_CMPU, && case_sem_INSN_WRITE_CMPU },
-    { M32RXF_INSN_PAR_CMPEQ, && case_sem_INSN_PAR_CMPEQ },
-    { M32RXF_INSN_WRITE_CMPEQ, && case_sem_INSN_WRITE_CMPEQ },
-    { M32RXF_INSN_PAR_CMPZ, && case_sem_INSN_PAR_CMPZ },
-    { M32RXF_INSN_WRITE_CMPZ, && case_sem_INSN_WRITE_CMPZ },
-    { M32RXF_INSN_PAR_JC, && case_sem_INSN_PAR_JC },
-    { M32RXF_INSN_WRITE_JC, && case_sem_INSN_WRITE_JC },
-    { M32RXF_INSN_PAR_JNC, && case_sem_INSN_PAR_JNC },
-    { M32RXF_INSN_WRITE_JNC, && case_sem_INSN_WRITE_JNC },
-    { M32RXF_INSN_PAR_JL, && case_sem_INSN_PAR_JL },
-    { M32RXF_INSN_WRITE_JL, && case_sem_INSN_WRITE_JL },
-    { M32RXF_INSN_PAR_JMP, && case_sem_INSN_PAR_JMP },
-    { M32RXF_INSN_WRITE_JMP, && case_sem_INSN_WRITE_JMP },
-    { M32RXF_INSN_PAR_LD, && case_sem_INSN_PAR_LD },
-    { M32RXF_INSN_WRITE_LD, && case_sem_INSN_WRITE_LD },
-    { M32RXF_INSN_PAR_LDB, && case_sem_INSN_PAR_LDB },
-    { M32RXF_INSN_WRITE_LDB, && case_sem_INSN_WRITE_LDB },
-    { M32RXF_INSN_PAR_LDH, && case_sem_INSN_PAR_LDH },
-    { M32RXF_INSN_WRITE_LDH, && case_sem_INSN_WRITE_LDH },
-    { M32RXF_INSN_PAR_LDUB, && case_sem_INSN_PAR_LDUB },
-    { M32RXF_INSN_WRITE_LDUB, && case_sem_INSN_WRITE_LDUB },
-    { M32RXF_INSN_PAR_LDUH, && case_sem_INSN_PAR_LDUH },
-    { M32RXF_INSN_WRITE_LDUH, && case_sem_INSN_WRITE_LDUH },
-    { M32RXF_INSN_PAR_LD_PLUS, && case_sem_INSN_PAR_LD_PLUS },
-    { M32RXF_INSN_WRITE_LD_PLUS, && case_sem_INSN_WRITE_LD_PLUS },
-    { M32RXF_INSN_PAR_LDI8, && case_sem_INSN_PAR_LDI8 },
-    { M32RXF_INSN_WRITE_LDI8, && case_sem_INSN_WRITE_LDI8 },
-    { M32RXF_INSN_PAR_LOCK, && case_sem_INSN_PAR_LOCK },
-    { M32RXF_INSN_WRITE_LOCK, && case_sem_INSN_WRITE_LOCK },
-    { M32RXF_INSN_PAR_MACHI_A, && case_sem_INSN_PAR_MACHI_A },
-    { M32RXF_INSN_WRITE_MACHI_A, && case_sem_INSN_WRITE_MACHI_A },
-    { M32RXF_INSN_PAR_MACLO_A, && case_sem_INSN_PAR_MACLO_A },
-    { M32RXF_INSN_WRITE_MACLO_A, && case_sem_INSN_WRITE_MACLO_A },
-    { M32RXF_INSN_PAR_MACWHI_A, && case_sem_INSN_PAR_MACWHI_A },
-    { M32RXF_INSN_WRITE_MACWHI_A, && case_sem_INSN_WRITE_MACWHI_A },
-    { M32RXF_INSN_PAR_MACWLO_A, && case_sem_INSN_PAR_MACWLO_A },
-    { M32RXF_INSN_WRITE_MACWLO_A, && case_sem_INSN_WRITE_MACWLO_A },
-    { M32RXF_INSN_PAR_MUL, && case_sem_INSN_PAR_MUL },
-    { M32RXF_INSN_WRITE_MUL, && case_sem_INSN_WRITE_MUL },
-    { M32RXF_INSN_PAR_MULHI_A, && case_sem_INSN_PAR_MULHI_A },
-    { M32RXF_INSN_WRITE_MULHI_A, && case_sem_INSN_WRITE_MULHI_A },
-    { M32RXF_INSN_PAR_MULLO_A, && case_sem_INSN_PAR_MULLO_A },
-    { M32RXF_INSN_WRITE_MULLO_A, && case_sem_INSN_WRITE_MULLO_A },
-    { M32RXF_INSN_PAR_MULWHI_A, && case_sem_INSN_PAR_MULWHI_A },
-    { M32RXF_INSN_WRITE_MULWHI_A, && case_sem_INSN_WRITE_MULWHI_A },
-    { M32RXF_INSN_PAR_MULWLO_A, && case_sem_INSN_PAR_MULWLO_A },
-    { M32RXF_INSN_WRITE_MULWLO_A, && case_sem_INSN_WRITE_MULWLO_A },
-    { M32RXF_INSN_PAR_MV, && case_sem_INSN_PAR_MV },
-    { M32RXF_INSN_WRITE_MV, && case_sem_INSN_WRITE_MV },
-    { M32RXF_INSN_PAR_MVFACHI_A, && case_sem_INSN_PAR_MVFACHI_A },
-    { M32RXF_INSN_WRITE_MVFACHI_A, && case_sem_INSN_WRITE_MVFACHI_A },
-    { M32RXF_INSN_PAR_MVFACLO_A, && case_sem_INSN_PAR_MVFACLO_A },
-    { M32RXF_INSN_WRITE_MVFACLO_A, && case_sem_INSN_WRITE_MVFACLO_A },
-    { M32RXF_INSN_PAR_MVFACMI_A, && case_sem_INSN_PAR_MVFACMI_A },
-    { M32RXF_INSN_WRITE_MVFACMI_A, && case_sem_INSN_WRITE_MVFACMI_A },
-    { M32RXF_INSN_PAR_MVFC, && case_sem_INSN_PAR_MVFC },
-    { M32RXF_INSN_WRITE_MVFC, && case_sem_INSN_WRITE_MVFC },
-    { M32RXF_INSN_PAR_MVTACHI_A, && case_sem_INSN_PAR_MVTACHI_A },
-    { M32RXF_INSN_WRITE_MVTACHI_A, && case_sem_INSN_WRITE_MVTACHI_A },
-    { M32RXF_INSN_PAR_MVTACLO_A, && case_sem_INSN_PAR_MVTACLO_A },
-    { M32RXF_INSN_WRITE_MVTACLO_A, && case_sem_INSN_WRITE_MVTACLO_A },
-    { M32RXF_INSN_PAR_MVTC, && case_sem_INSN_PAR_MVTC },
-    { M32RXF_INSN_WRITE_MVTC, && case_sem_INSN_WRITE_MVTC },
-    { M32RXF_INSN_PAR_NEG, && case_sem_INSN_PAR_NEG },
-    { M32RXF_INSN_WRITE_NEG, && case_sem_INSN_WRITE_NEG },
-    { M32RXF_INSN_PAR_NOP, && case_sem_INSN_PAR_NOP },
-    { M32RXF_INSN_WRITE_NOP, && case_sem_INSN_WRITE_NOP },
-    { M32RXF_INSN_PAR_NOT, && case_sem_INSN_PAR_NOT },
-    { M32RXF_INSN_WRITE_NOT, && case_sem_INSN_WRITE_NOT },
-    { M32RXF_INSN_PAR_RAC_DSI, && case_sem_INSN_PAR_RAC_DSI },
-    { M32RXF_INSN_WRITE_RAC_DSI, && case_sem_INSN_WRITE_RAC_DSI },
-    { M32RXF_INSN_PAR_RACH_DSI, && case_sem_INSN_PAR_RACH_DSI },
-    { M32RXF_INSN_WRITE_RACH_DSI, && case_sem_INSN_WRITE_RACH_DSI },
-    { M32RXF_INSN_PAR_RTE, && case_sem_INSN_PAR_RTE },
-    { M32RXF_INSN_WRITE_RTE, && case_sem_INSN_WRITE_RTE },
-    { M32RXF_INSN_PAR_SLL, && case_sem_INSN_PAR_SLL },
-    { M32RXF_INSN_WRITE_SLL, && case_sem_INSN_WRITE_SLL },
-    { M32RXF_INSN_PAR_SLLI, && case_sem_INSN_PAR_SLLI },
-    { M32RXF_INSN_WRITE_SLLI, && case_sem_INSN_WRITE_SLLI },
-    { M32RXF_INSN_PAR_SRA, && case_sem_INSN_PAR_SRA },
-    { M32RXF_INSN_WRITE_SRA, && case_sem_INSN_WRITE_SRA },
-    { M32RXF_INSN_PAR_SRAI, && case_sem_INSN_PAR_SRAI },
-    { M32RXF_INSN_WRITE_SRAI, && case_sem_INSN_WRITE_SRAI },
-    { M32RXF_INSN_PAR_SRL, && case_sem_INSN_PAR_SRL },
-    { M32RXF_INSN_WRITE_SRL, && case_sem_INSN_WRITE_SRL },
-    { M32RXF_INSN_PAR_SRLI, && case_sem_INSN_PAR_SRLI },
-    { M32RXF_INSN_WRITE_SRLI, && case_sem_INSN_WRITE_SRLI },
-    { M32RXF_INSN_PAR_ST, && case_sem_INSN_PAR_ST },
-    { M32RXF_INSN_WRITE_ST, && case_sem_INSN_WRITE_ST },
-    { M32RXF_INSN_PAR_STB, && case_sem_INSN_PAR_STB },
-    { M32RXF_INSN_WRITE_STB, && case_sem_INSN_WRITE_STB },
-    { M32RXF_INSN_PAR_STH, && case_sem_INSN_PAR_STH },
-    { M32RXF_INSN_WRITE_STH, && case_sem_INSN_WRITE_STH },
-    { M32RXF_INSN_PAR_ST_PLUS, && case_sem_INSN_PAR_ST_PLUS },
-    { M32RXF_INSN_WRITE_ST_PLUS, && case_sem_INSN_WRITE_ST_PLUS },
-    { M32RXF_INSN_PAR_ST_MINUS, && case_sem_INSN_PAR_ST_MINUS },
-    { M32RXF_INSN_WRITE_ST_MINUS, && case_sem_INSN_WRITE_ST_MINUS },
-    { M32RXF_INSN_PAR_SUB, && case_sem_INSN_PAR_SUB },
-    { M32RXF_INSN_WRITE_SUB, && case_sem_INSN_WRITE_SUB },
-    { M32RXF_INSN_PAR_SUBV, && case_sem_INSN_PAR_SUBV },
-    { M32RXF_INSN_WRITE_SUBV, && case_sem_INSN_WRITE_SUBV },
-    { M32RXF_INSN_PAR_SUBX, && case_sem_INSN_PAR_SUBX },
-    { M32RXF_INSN_WRITE_SUBX, && case_sem_INSN_WRITE_SUBX },
-    { M32RXF_INSN_PAR_TRAP, && case_sem_INSN_PAR_TRAP },
-    { M32RXF_INSN_WRITE_TRAP, && case_sem_INSN_WRITE_TRAP },
-    { M32RXF_INSN_PAR_UNLOCK, && case_sem_INSN_PAR_UNLOCK },
-    { M32RXF_INSN_WRITE_UNLOCK, && case_sem_INSN_WRITE_UNLOCK },
-    { M32RXF_INSN_PAR_PCMPBZ, && case_sem_INSN_PAR_PCMPBZ },
-    { M32RXF_INSN_WRITE_PCMPBZ, && case_sem_INSN_WRITE_PCMPBZ },
-    { M32RXF_INSN_PAR_SADD, && case_sem_INSN_PAR_SADD },
-    { M32RXF_INSN_WRITE_SADD, && case_sem_INSN_WRITE_SADD },
-    { M32RXF_INSN_PAR_MACWU1, && case_sem_INSN_PAR_MACWU1 },
-    { M32RXF_INSN_WRITE_MACWU1, && case_sem_INSN_WRITE_MACWU1 },
-    { M32RXF_INSN_PAR_MSBLO, && case_sem_INSN_PAR_MSBLO },
-    { M32RXF_INSN_WRITE_MSBLO, && case_sem_INSN_WRITE_MSBLO },
-    { M32RXF_INSN_PAR_MULWU1, && case_sem_INSN_PAR_MULWU1 },
-    { M32RXF_INSN_WRITE_MULWU1, && case_sem_INSN_WRITE_MULWU1 },
-    { M32RXF_INSN_PAR_MACLH1, && case_sem_INSN_PAR_MACLH1 },
-    { M32RXF_INSN_WRITE_MACLH1, && case_sem_INSN_WRITE_MACLH1 },
-    { M32RXF_INSN_PAR_SC, && case_sem_INSN_PAR_SC },
-    { M32RXF_INSN_WRITE_SC, && case_sem_INSN_WRITE_SC },
-    { M32RXF_INSN_PAR_SNC, && case_sem_INSN_PAR_SNC },
-    { M32RXF_INSN_WRITE_SNC, && case_sem_INSN_WRITE_SNC },
-    { 0, 0 }
-  };
-  int i;
-
-  for (i = 0; labels[i].label != 0; ++i)
-#if FAST_P
-    CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
-#else
-    CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
-#endif
-
-#undef DEFINE_LABELS
-#endif /* DEFINE_LABELS */
-
-#ifdef DEFINE_SWITCH
-
-/* If hyper-fast [well not unnecessarily slow] execution is selected, turn
-   off frills like tracing and profiling.  */
-/* FIXME: A better way would be to have TRACE_RESULT check for something
-   that can cause it to be optimized out.  Another way would be to emit
-   special handlers into the instruction "stream".  */
-
-#if FAST_P
-#undef TRACE_RESULT
-#define TRACE_RESULT(cpu, abuf, name, type, val)
-#endif
-
-#undef GET_ATTR
-#define GET_ATTR(cpu, num, attr) CGEN_INSN_ATTR (abuf->idesc->opcode, CGEN_INSN_##attr)
-
-{
-
-#if WITH_SCACHE_PBB
-
-/* Branch to next handler without going around main loop.  */
-#define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
-SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
-
-#else /* ! WITH_SCACHE_PBB */
-
-#define NEXT(vpc) BREAK (sem)
-#ifdef __GNUC__
-#if FAST_P
-  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
-#else
-  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
-#endif
-#else
-  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
-#endif
-
-#endif /* ! WITH_SCACHE_PBB */
-
-    {
-
-  CASE (sem, INSN_X_INVALID) : /* --invalid-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE
-    /* Update the recorded pc in the cpu state struct.  */
-    SET_H_PC (pc);
-#endif
-    sim_engine_invalid_insn (current_cpu, pc);
-    sim_io_error (CPU_STATE (current_cpu), "invalid insn not handled\n");
-    /* NOTREACHED */
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_X_AFTER) : /* --after-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_M32RXF
-    m32rxf_pbb_after (current_cpu, sem_arg);
-#endif
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_X_BEFORE) : /* --before-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_M32RXF
-    m32rxf_pbb_before (current_cpu, sem_arg);
-#endif
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_M32RXF
-#ifdef DEFINE_SWITCH
-    vpc = m32rxf_pbb_cti_chain (current_cpu, sem_arg,
-			       pbb_br_npc_ptr, pbb_br_npc);
-    BREAK (sem);
-#else
-    /* FIXME: Allow provision of explicit ifmt spec in insn spec.  */
-    vpc = m32rxf_pbb_cti_chain (current_cpu, sem_arg,
-			       CPU_PBB_BR_NPC_PTR (current_cpu),
-			       CPU_PBB_BR_NPC (current_cpu));
-#endif
-#endif
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_X_CHAIN) : /* --chain-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_M32RXF
-    vpc = m32rxf_pbb_chain (current_cpu, sem_arg);
-#ifdef DEFINE_SWITCH
-    BREAK (sem);
-#endif
-#endif
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_X_BEGIN) : /* --begin-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_M32RXF
-#ifdef DEFINE_SWITCH
-    /* In the switch case FAST_P is a constant, allowing several optimizations
-       in any called inline functions.  */
-    vpc = m32rxf_pbb_begin (current_cpu, FAST_P);
-#else
-    vpc = m32rxf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
-#endif
-#endif
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ADD) : /* add $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ADDSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ADD3) : /* add3 $dr,$sr,$hash$slo16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_add3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = ADDSI (* FLD (i_sr), FLD (f_simm16));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_AND) : /* and $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ANDSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_AND3) : /* and3 $dr,$sr,$uimm16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_and3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = ANDSI (* FLD (i_sr), FLD (f_uimm16));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_OR) : /* or $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ORSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_OR3) : /* or3 $dr,$sr,$hash$ulo16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_or3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = ORSI (* FLD (i_sr), FLD (f_uimm16));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_XOR) : /* xor $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = XORSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_XOR3) : /* xor3 $dr,$sr,$uimm16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_and3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = XORSI (* FLD (i_sr), FLD (f_uimm16));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ADDI) : /* addi $dr,$simm8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_addi.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ADDSI (* FLD (i_dr), FLD (f_simm8));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ADDV) : /* addv $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_addv.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  BI temp1;SI temp0;
-  temp0 = ADDSI (* FLD (i_dr), * FLD (i_sr));
-  temp1 = ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0);
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
-  }
-} while (0);
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ADDV3) : /* addv3 $dr,$sr,$simm16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_addv3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-do {
-  BI temp1;SI temp0;
-  temp0 = ADDSI (* FLD (i_sr), FLD (f_simm16));
-  temp1 = ADDOFSI (* FLD (i_sr), FLD (f_simm16), 0);
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
-  }
-} while (0);
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ADDX) : /* addx $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_addx.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  BI temp1;SI temp0;
-  temp0 = ADDCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
-  temp1 = ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
-  }
-} while (0);
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BC8) : /* bc.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (CPU (h_cond)) {
-  {
-    USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BC24) : /* bc.l $disp24 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (CPU (h_cond)) {
-  {
-    USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BEQ) : /* beq $src1,$src2,$disp16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_beq.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (EQSI (* FLD (i_src1), * FLD (i_src2))) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BEQZ) : /* beqz $src2,$disp16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (EQSI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BGEZ) : /* bgez $src2,$disp16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (GESI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BGTZ) : /* bgtz $src2,$disp16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (GTSI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BLEZ) : /* blez $src2,$disp16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (LESI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BLTZ) : /* bltz $src2,$disp16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (LTSI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BNEZ) : /* bnez $src2,$disp16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BL8) : /* bl.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_bl8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  {
-    SI opval = ADDSI (ANDSI (pc, -4), 4);
-    CPU (h_gr[((UINT) 14)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
-  }
-  {
-    USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-} while (0);
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BL24) : /* bl.l $disp24 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_bl24.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-do {
-  {
-    SI opval = ADDSI (pc, 4);
-    CPU (h_gr[((UINT) 14)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
-  }
-  {
-    USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-} while (0);
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BCL8) : /* bcl.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_bcl8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (CPU (h_cond)) {
-do {
-  {
-    SI opval = ADDSI (ANDSI (pc, -4), 4);
-    CPU (h_gr[((UINT) 14)]) = opval;
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
-  }
-  {
-    USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-} while (0);
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BCL24) : /* bcl.l $disp24 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_bcl24.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (CPU (h_cond)) {
-do {
-  {
-    SI opval = ADDSI (pc, 4);
-    CPU (h_gr[((UINT) 14)]) = opval;
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
-  }
-  {
-    USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-} while (0);
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BNC8) : /* bnc.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (CPU (h_cond))) {
-  {
-    USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BNC24) : /* bnc.l $disp24 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NOTBI (CPU (h_cond))) {
-  {
-    USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BNE) : /* bne $src1,$src2,$disp16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_beq.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_src1), * FLD (i_src2))) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BRA8) : /* bra.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_bra8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BRA24) : /* bra.l $disp24 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_bra24.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BNCL8) : /* bncl.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_bcl8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (CPU (h_cond))) {
-do {
-  {
-    SI opval = ADDSI (ANDSI (pc, -4), 4);
-    CPU (h_gr[((UINT) 14)]) = opval;
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
-  }
-  {
-    USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-} while (0);
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BNCL24) : /* bncl.l $disp24 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_bcl24.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NOTBI (CPU (h_cond))) {
-do {
-  {
-    SI opval = ADDSI (pc, 4);
-    CPU (h_gr[((UINT) 14)]) = opval;
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
-  }
-  {
-    USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-} while (0);
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CMP) : /* cmp $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_cmp.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = LTSI (* FLD (i_src1), * FLD (i_src2));
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CMPI) : /* cmpi $src2,$simm16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_cmpi.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    BI opval = LTSI (* FLD (i_src2), FLD (f_simm16));
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CMPU) : /* cmpu $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_cmp.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = LTUSI (* FLD (i_src1), * FLD (i_src2));
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CMPUI) : /* cmpui $src2,$simm16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_cmpi.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    BI opval = LTUSI (* FLD (i_src2), FLD (f_simm16));
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CMPEQ) : /* cmpeq $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_cmp.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = EQSI (* FLD (i_src1), * FLD (i_src2));
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CMPZ) : /* cmpz $src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_cmpz.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = EQSI (* FLD (i_src2), 0);
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_DIV) : /* div $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_div.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_sr), 0)) {
-  {
-    SI opval = DIVSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_DIVU) : /* divu $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_div.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_sr), 0)) {
-  {
-    SI opval = UDIVSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_REM) : /* rem $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_div.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_sr), 0)) {
-  {
-    SI opval = MODSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_REMU) : /* remu $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_div.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_sr), 0)) {
-  {
-    SI opval = UMODSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_DIVH) : /* divh $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_div.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_sr), 0)) {
-  {
-    SI opval = DIVSI (EXTHISI (TRUNCSIHI (* FLD (i_dr))), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_JC) : /* jc $sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_jc.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (CPU (h_cond)) {
-  {
-    USI opval = ANDSI (* FLD (i_sr), -4);
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_JNC) : /* jnc $sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_jc.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (CPU (h_cond))) {
-  {
-    USI opval = ANDSI (* FLD (i_sr), -4);
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_JL) : /* jl $sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_jl.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  USI temp1;SI temp0;
-  temp0 = ADDSI (ANDSI (pc, -4), 4);
-  temp1 = ANDSI (* FLD (i_sr), -4);
-  {
-    SI opval = temp0;
-    CPU (h_gr[((UINT) 14)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
-  }
-  {
-    USI opval = temp1;
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-} while (0);
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_JMP) : /* jmp $sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    USI opval = ANDSI (* FLD (i_sr), -4);
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LD) : /* ld $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ld.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LD_D) : /* ld $dr,@($slo16,$sr) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ld_d.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = GETMEMSI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDB) : /* ldb $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ldb.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDB_D) : /* ldb $dr,@($slo16,$sr) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ldb_d.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDH) : /* ldh $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ldh.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDH_D) : /* ldh $dr,@($slo16,$sr) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ldh_d.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDUB) : /* ldub $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ldb.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDUB_D) : /* ldub $dr,@($slo16,$sr) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ldb_d.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDUH) : /* lduh $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ldh.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDUH_D) : /* lduh $dr,@($slo16,$sr) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ldh_d.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LD_PLUS) : /* ld $dr,@$sr+ */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  SI temp1;SI temp0;
-  temp0 = GETMEMSI (current_cpu, pc, * FLD (i_sr));
-  temp1 = ADDSI (* FLD (i_sr), 4);
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-  {
-    SI opval = temp1;
-    * FLD (i_sr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
-  }
-} while (0);
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LD24) : /* ld24 $dr,$uimm24 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ld24.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = FLD (i_uimm24);
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDI8) : /* ldi8 $dr,$simm8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ldi8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = FLD (f_simm8);
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDI16) : /* ldi16 $dr,$hash$slo16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ldi16.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = FLD (f_simm16);
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LOCK) : /* lock $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_lock.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  {
-    BI opval = 1;
-    CPU (h_lock) = opval;
-    TRACE_RESULT (current_cpu, abuf, "lock-0", 'x', opval);
-  }
-  {
-    SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-} while (0);
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MACHI_A) : /* machi $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_machi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8);
-    SET_H_ACCUMS (FLD (f_acc), opval);
-    TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MACLO_A) : /* maclo $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_machi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8);
-    SET_H_ACCUMS (FLD (f_acc), opval);
-    TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MACWHI_A) : /* macwhi $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_machi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))));
-    SET_H_ACCUMS (FLD (f_acc), opval);
-    TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MACWLO_A) : /* macwlo $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_machi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))));
-    SET_H_ACCUMS (FLD (f_acc), opval);
-    TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MUL) : /* mul $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = MULSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MULHI_A) : /* mulhi $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mulhi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 16), 16);
-    SET_H_ACCUMS (FLD (f_acc), opval);
-    TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MULLO_A) : /* mullo $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mulhi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 16), 16);
-    SET_H_ACCUMS (FLD (f_acc), opval);
-    TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MULWHI_A) : /* mulwhi $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mulhi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))));
-    SET_H_ACCUMS (FLD (f_acc), opval);
-    TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MULWLO_A) : /* mulwlo $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mulhi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))));
-    SET_H_ACCUMS (FLD (f_acc), opval);
-    TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MV) : /* mv $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mv.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = * FLD (i_sr);
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MVFACHI_A) : /* mvfachi $dr,$accs */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mvfachi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = TRUNCDISI (SRADI (GET_H_ACCUMS (FLD (f_accs)), 32));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MVFACLO_A) : /* mvfaclo $dr,$accs */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mvfachi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = TRUNCDISI (GET_H_ACCUMS (FLD (f_accs)));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MVFACMI_A) : /* mvfacmi $dr,$accs */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mvfachi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = TRUNCDISI (SRADI (GET_H_ACCUMS (FLD (f_accs)), 16));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MVFC) : /* mvfc $dr,$scr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mvfc.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GET_H_CR (FLD (f_r2));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MVTACHI_A) : /* mvtachi $src1,$accs */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mvtachi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ORDI (ANDDI (GET_H_ACCUMS (FLD (f_accs)), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (i_src1)), 32));
-    SET_H_ACCUMS (FLD (f_accs), opval);
-    TRACE_RESULT (current_cpu, abuf, "accs", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MVTACLO_A) : /* mvtaclo $src1,$accs */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mvtachi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ORDI (ANDDI (GET_H_ACCUMS (FLD (f_accs)), MAKEDI (0xffffffff, 0)), ZEXTSIDI (* FLD (i_src1)));
-    SET_H_ACCUMS (FLD (f_accs), opval);
-    TRACE_RESULT (current_cpu, abuf, "accs", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MVTC) : /* mvtc $sr,$dcr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mvtc.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    USI opval = * FLD (i_sr);
-    SET_H_CR (FLD (f_r1), opval);
-    TRACE_RESULT (current_cpu, abuf, "dcr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_NEG) : /* neg $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mv.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = NEGSI (* FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_NOP) : /* nop */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_nop.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_NOT) : /* not $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mv.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = INVSI (* FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_RAC_DSI) : /* rac $accd,$accs,$imm1 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_rac_dsi.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  DI tmp_tmp1;
-  tmp_tmp1 = SLLDI (GET_H_ACCUMS (FLD (f_accs)), FLD (f_imm1));
-  tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768));
-  {
-    DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000)));
-    SET_H_ACCUMS (FLD (f_accd), opval);
-    TRACE_RESULT (current_cpu, abuf, "accd", 'D', opval);
-  }
-} while (0);
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_RACH_DSI) : /* rach $accd,$accs,$imm1 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_rac_dsi.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  DI tmp_tmp1;
-  tmp_tmp1 = SLLDI (GET_H_ACCUMS (FLD (f_accs)), FLD (f_imm1));
-  tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 0x80000000));
-  {
-    DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0))) ? (MAKEDI (32767, 0)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0)));
-    SET_H_ACCUMS (FLD (f_accd), opval);
-    TRACE_RESULT (current_cpu, abuf, "accd", 'D', opval);
-  }
-} while (0);
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_RTE) : /* rte */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_rte.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  {
-    USI opval = ANDSI (GET_H_CR (((UINT) 6)), -4);
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-  {
-    USI opval = GET_H_CR (((UINT) 14));
-    SET_H_CR (((UINT) 6), opval);
-    TRACE_RESULT (current_cpu, abuf, "cr-6", 'x', opval);
-  }
-  {
-    UQI opval = CPU (h_bpsw);
-    SET_H_PSW (opval);
-    TRACE_RESULT (current_cpu, abuf, "psw-0", 'x', opval);
-  }
-  {
-    UQI opval = CPU (h_bbpsw);
-    CPU (h_bpsw) = opval;
-    TRACE_RESULT (current_cpu, abuf, "bpsw-0", 'x', opval);
-  }
-} while (0);
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SETH) : /* seth $dr,$hash$hi16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_seth.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = SLLSI (FLD (f_hi16), 16);
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SLL) : /* sll $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SLLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SLL3) : /* sll3 $dr,$sr,$simm16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_sll3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = SLLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SLLI) : /* slli $dr,$uimm5 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_slli.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SLLSI (* FLD (i_dr), FLD (f_uimm5));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SRA) : /* sra $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRASI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SRA3) : /* sra3 $dr,$sr,$simm16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_sll3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = SRASI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SRAI) : /* srai $dr,$uimm5 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_slli.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRASI (* FLD (i_dr), FLD (f_uimm5));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SRL) : /* srl $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SRL3) : /* srl3 $dr,$sr,$simm16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_sll3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = SRLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SRLI) : /* srli $dr,$uimm5 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_slli.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRLSI (* FLD (i_dr), FLD (f_uimm5));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ST) : /* st $src1,@$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_st.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = * FLD (i_src1);
-    SETMEMSI (current_cpu, pc, * FLD (i_src2), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ST_D) : /* st $src1,@($slo16,$src2) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_st_d.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = * FLD (i_src1);
-    SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STB) : /* stb $src1,@$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_stb.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    QI opval = * FLD (i_src1);
-    SETMEMQI (current_cpu, pc, * FLD (i_src2), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STB_D) : /* stb $src1,@($slo16,$src2) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_stb_d.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    QI opval = * FLD (i_src1);
-    SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STH) : /* sth $src1,@$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_sth.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    HI opval = * FLD (i_src1);
-    SETMEMHI (current_cpu, pc, * FLD (i_src2), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STH_D) : /* sth $src1,@($slo16,$src2) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_sth_d.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    HI opval = * FLD (i_src1);
-    SETMEMHI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ST_PLUS) : /* st $src1,@+$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  SI tmp_new_src2;
-  tmp_new_src2 = ADDSI (* FLD (i_src2), 4);
-  {
-    SI opval = * FLD (i_src1);
-    SETMEMSI (current_cpu, pc, tmp_new_src2, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  {
-    SI opval = tmp_new_src2;
-    * FLD (i_src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "src2", 'x', opval);
-  }
-} while (0);
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ST_MINUS) : /* st $src1,@-$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  SI tmp_new_src2;
-  tmp_new_src2 = SUBSI (* FLD (i_src2), 4);
-  {
-    SI opval = * FLD (i_src1);
-    SETMEMSI (current_cpu, pc, tmp_new_src2, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  {
-    SI opval = tmp_new_src2;
-    * FLD (i_src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "src2", 'x', opval);
-  }
-} while (0);
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SUB) : /* sub $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SUBSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SUBV) : /* subv $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_addv.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  BI temp1;SI temp0;
-  temp0 = SUBSI (* FLD (i_dr), * FLD (i_sr));
-  temp1 = SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0);
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
-  }
-} while (0);
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SUBX) : /* subx $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_addx.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  BI temp1;SI temp0;
-  temp0 = SUBCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
-  temp1 = SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
-  }
-} while (0);
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_TRAP) : /* trap $uimm4 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_trap.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  {
-    USI opval = GET_H_CR (((UINT) 6));
-    SET_H_CR (((UINT) 14), opval);
-    TRACE_RESULT (current_cpu, abuf, "cr-14", 'x', opval);
-  }
-  {
-    USI opval = ADDSI (pc, 4);
-    SET_H_CR (((UINT) 6), opval);
-    TRACE_RESULT (current_cpu, abuf, "cr-6", 'x', opval);
-  }
-  {
-    UQI opval = CPU (h_bpsw);
-    CPU (h_bbpsw) = opval;
-    TRACE_RESULT (current_cpu, abuf, "bbpsw-0", 'x', opval);
-  }
-  {
-    UQI opval = GET_H_PSW ();
-    CPU (h_bpsw) = opval;
-    TRACE_RESULT (current_cpu, abuf, "bpsw-0", 'x', opval);
-  }
-  {
-    UQI opval = ANDQI (GET_H_PSW (), 128);
-    SET_H_PSW (opval);
-    TRACE_RESULT (current_cpu, abuf, "psw-0", 'x', opval);
-  }
-  {
-    SI opval = m32r_trap (current_cpu, pc, FLD (f_uimm4));
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-} while (0);
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_UNLOCK) : /* unlock $src1,@$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_unlock.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-if (CPU (h_lock)) {
-  {
-    SI opval = * FLD (i_src1);
-    SETMEMSI (current_cpu, pc, * FLD (i_src2), opval);
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-}
-  {
-    BI opval = 0;
-    CPU (h_lock) = opval;
-    TRACE_RESULT (current_cpu, abuf, "lock-0", 'x', opval);
-  }
-} while (0);
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SATB) : /* satb $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_satb.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = (GESI (* FLD (i_sr), 127)) ? (127) : (LESI (* FLD (i_sr), -128)) ? (-128) : (* FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SATH) : /* sath $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_satb.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = (GESI (* FLD (i_sr), 32767)) ? (32767) : (LESI (* FLD (i_sr), -32768)) ? (-32768) : (* FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SAT) : /* sat $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_sat.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = ((CPU (h_cond)) ? (((LTSI (* FLD (i_sr), 0)) ? (2147483647) : (0x80000000))) : (* FLD (i_sr)));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PCMPBZ) : /* pcmpbz $src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_cmpz.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = (EQSI (ANDSI (* FLD (i_src2), 255), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 65280), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 16711680), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 0xff000000), 0)) ? (1) : (0);
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SADD) : /* sadd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_sadd.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ADDDI (SRADI (GET_H_ACCUMS (((UINT) 1)), 16), GET_H_ACCUMS (((UINT) 0)));
-    SET_H_ACCUMS (((UINT) 0), opval);
-    TRACE_RESULT (current_cpu, abuf, "accums-0", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MACWU1) : /* macwu1 $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_macwu1.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535)))), 8), 8);
-    SET_H_ACCUMS (((UINT) 1), opval);
-    TRACE_RESULT (current_cpu, abuf, "accums-1", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MSBLO) : /* msblo $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_msblo.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (SUBDI (GET_H_ACCUM (), SRADI (SLLDI (MULDI (EXTHIDI (TRUNCSIHI (* FLD (i_src1))), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 32), 16)), 8), 8);
-    SET_H_ACCUM (opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MULWU1) : /* mulwu1 $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mulwu1.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535))), 16), 16);
-    SET_H_ACCUMS (((UINT) 1), opval);
-    TRACE_RESULT (current_cpu, abuf, "accums-1", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MACLH1) : /* maclh1 $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_macwu1.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), SLLDI (EXTSIDI (MULSI (EXTHISI (TRUNCSIHI (* FLD (i_src1))), SRASI (* FLD (i_src2), 16))), 16)), 8), 8);
-    SET_H_ACCUMS (((UINT) 1), opval);
-    TRACE_RESULT (current_cpu, abuf, "accums-1", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SC) : /* sc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_sc.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (CPU (h_cond)) {
-SEM_SKIP_INSN (current_cpu, 1);
-}
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SNC) : /* snc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_sc.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (CPU (h_cond))) {
-SEM_SKIP_INSN (current_cpu, 1);
-}
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_ADD) : /* add $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_add.f
-#define OPRND(f) par_exec->operands.fmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ADDSI (* FLD (i_dr), * FLD (i_sr));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_ADD) : /* add $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_add.f
-#define OPRND(f) par_exec->operands.fmt_add.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_AND) : /* and $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_add.f
-#define OPRND(f) par_exec->operands.fmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ANDSI (* FLD (i_dr), * FLD (i_sr));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_AND) : /* and $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_add.f
-#define OPRND(f) par_exec->operands.fmt_add.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_OR) : /* or $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_add.f
-#define OPRND(f) par_exec->operands.fmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ORSI (* FLD (i_dr), * FLD (i_sr));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_OR) : /* or $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_add.f
-#define OPRND(f) par_exec->operands.fmt_add.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_XOR) : /* xor $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_add.f
-#define OPRND(f) par_exec->operands.fmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = XORSI (* FLD (i_dr), * FLD (i_sr));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_XOR) : /* xor $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_add.f
-#define OPRND(f) par_exec->operands.fmt_add.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_ADDI) : /* addi $dr,$simm8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_addi.f
-#define OPRND(f) par_exec->operands.fmt_addi.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ADDSI (* FLD (i_dr), FLD (f_simm8));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_ADDI) : /* addi $dr,$simm8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_addi.f
-#define OPRND(f) par_exec->operands.fmt_addi.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_ADDV) : /* addv $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_addv.f
-#define OPRND(f) par_exec->operands.fmt_addv.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  BI temp1;SI temp0;
-  temp0 = ADDSI (* FLD (i_dr), * FLD (i_sr));
-  temp1 = ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0);
-  {
-    SI opval = temp0;
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    OPRND (condbit) = opval;
-    TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
-  }
-} while (0);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_ADDV) : /* addv $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_addv.f
-#define OPRND(f) par_exec->operands.fmt_addv.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_cond) = OPRND (condbit);
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_ADDX) : /* addx $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_addx.f
-#define OPRND(f) par_exec->operands.fmt_addx.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  BI temp1;SI temp0;
-  temp0 = ADDCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
-  temp1 = ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
-  {
-    SI opval = temp0;
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    OPRND (condbit) = opval;
-    TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
-  }
-} while (0);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_ADDX) : /* addx $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_addx.f
-#define OPRND(f) par_exec->operands.fmt_addx.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_cond) = OPRND (condbit);
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_BC8) : /* bc.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
-#define OPRND(f) par_exec->operands.fmt_bc8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (CPU (h_cond)) {
-  {
-    USI opval = FLD (i_disp8);
-    OPRND (pc) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_BC8) : /* bc.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
-#define OPRND(f) par_exec->operands.fmt_bc8.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  if (written & (1 << 2))
-    {
-      SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
-    }
-
-  SEM_BRANCH_FINI (vpc);
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_BL8) : /* bl.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_bl8.f
-#define OPRND(f) par_exec->operands.fmt_bl8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  {
-    SI opval = ADDSI (ANDSI (pc, -4), 4);
-    OPRND (h_gr_14) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
-  }
-  {
-    USI opval = FLD (i_disp8);
-    OPRND (pc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-} while (0);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_BL8) : /* bl.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.cti.fields.fmt_bl8.f
-#define OPRND(f) par_exec->operands.fmt_bl8.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_14);
-  SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
-
-  SEM_BRANCH_FINI (vpc);
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_BCL8) : /* bcl.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_bcl8.f
-#define OPRND(f) par_exec->operands.fmt_bcl8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (CPU (h_cond)) {
-do {
-  {
-    SI opval = ADDSI (ANDSI (pc, -4), 4);
-    OPRND (h_gr_14) = opval;
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
-  }
-  {
-    USI opval = FLD (i_disp8);
-    OPRND (pc) = opval;
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-} while (0);
-}
-
-  abuf->written = written;
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_BCL8) : /* bcl.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.cti.fields.fmt_bcl8.f
-#define OPRND(f) par_exec->operands.fmt_bcl8.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  if (written & (1 << 3))
-    {
-      CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_14);
-    }
-  if (written & (1 << 4))
-    {
-      SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
-    }
-
-  SEM_BRANCH_FINI (vpc);
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_BNC8) : /* bnc.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
-#define OPRND(f) par_exec->operands.fmt_bc8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (CPU (h_cond))) {
-  {
-    USI opval = FLD (i_disp8);
-    OPRND (pc) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_BNC8) : /* bnc.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
-#define OPRND(f) par_exec->operands.fmt_bc8.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  if (written & (1 << 2))
-    {
-      SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
-    }
-
-  SEM_BRANCH_FINI (vpc);
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_BRA8) : /* bra.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_bra8.f
-#define OPRND(f) par_exec->operands.fmt_bra8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    USI opval = FLD (i_disp8);
-    OPRND (pc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_BRA8) : /* bra.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.cti.fields.fmt_bra8.f
-#define OPRND(f) par_exec->operands.fmt_bra8.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
-
-  SEM_BRANCH_FINI (vpc);
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_BNCL8) : /* bncl.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_bcl8.f
-#define OPRND(f) par_exec->operands.fmt_bcl8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (CPU (h_cond))) {
-do {
-  {
-    SI opval = ADDSI (ANDSI (pc, -4), 4);
-    OPRND (h_gr_14) = opval;
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
-  }
-  {
-    USI opval = FLD (i_disp8);
-    OPRND (pc) = opval;
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-} while (0);
-}
-
-  abuf->written = written;
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_BNCL8) : /* bncl.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.cti.fields.fmt_bcl8.f
-#define OPRND(f) par_exec->operands.fmt_bcl8.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  if (written & (1 << 3))
-    {
-      CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_14);
-    }
-  if (written & (1 << 4))
-    {
-      SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
-    }
-
-  SEM_BRANCH_FINI (vpc);
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_CMP) : /* cmp $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_cmp.f
-#define OPRND(f) par_exec->operands.fmt_cmp.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = LTSI (* FLD (i_src1), * FLD (i_src2));
-    OPRND (condbit) = opval;
-    TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_CMP) : /* cmp $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_cmp.f
-#define OPRND(f) par_exec->operands.fmt_cmp.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_cond) = OPRND (condbit);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_CMPU) : /* cmpu $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_cmp.f
-#define OPRND(f) par_exec->operands.fmt_cmp.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = LTUSI (* FLD (i_src1), * FLD (i_src2));
-    OPRND (condbit) = opval;
-    TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_CMPU) : /* cmpu $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_cmp.f
-#define OPRND(f) par_exec->operands.fmt_cmp.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_cond) = OPRND (condbit);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_CMPEQ) : /* cmpeq $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_cmp.f
-#define OPRND(f) par_exec->operands.fmt_cmp.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = EQSI (* FLD (i_src1), * FLD (i_src2));
-    OPRND (condbit) = opval;
-    TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_CMPEQ) : /* cmpeq $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_cmp.f
-#define OPRND(f) par_exec->operands.fmt_cmp.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_cond) = OPRND (condbit);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_CMPZ) : /* cmpz $src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_cmpz.f
-#define OPRND(f) par_exec->operands.fmt_cmpz.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = EQSI (* FLD (i_src2), 0);
-    OPRND (condbit) = opval;
-    TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_CMPZ) : /* cmpz $src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_cmpz.f
-#define OPRND(f) par_exec->operands.fmt_cmpz.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_cond) = OPRND (condbit);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_JC) : /* jc $sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_jc.f
-#define OPRND(f) par_exec->operands.fmt_jc.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (CPU (h_cond)) {
-  {
-    USI opval = ANDSI (* FLD (i_sr), -4);
-    OPRND (pc) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_JC) : /* jc $sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.cti.fields.fmt_jc.f
-#define OPRND(f) par_exec->operands.fmt_jc.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  if (written & (1 << 2))
-    {
-      SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
-    }
-
-  SEM_BRANCH_FINI (vpc);
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_JNC) : /* jnc $sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_jc.f
-#define OPRND(f) par_exec->operands.fmt_jc.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (CPU (h_cond))) {
-  {
-    USI opval = ANDSI (* FLD (i_sr), -4);
-    OPRND (pc) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_JNC) : /* jnc $sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.cti.fields.fmt_jc.f
-#define OPRND(f) par_exec->operands.fmt_jc.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  if (written & (1 << 2))
-    {
-      SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
-    }
-
-  SEM_BRANCH_FINI (vpc);
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_JL) : /* jl $sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_jl.f
-#define OPRND(f) par_exec->operands.fmt_jl.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  USI temp1;SI temp0;
-  temp0 = ADDSI (ANDSI (pc, -4), 4);
-  temp1 = ANDSI (* FLD (i_sr), -4);
-  {
-    SI opval = temp0;
-    OPRND (h_gr_14) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
-  }
-  {
-    USI opval = temp1;
-    OPRND (pc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-} while (0);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_JL) : /* jl $sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.cti.fields.fmt_jl.f
-#define OPRND(f) par_exec->operands.fmt_jl.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_14);
-  SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
-
-  SEM_BRANCH_FINI (vpc);
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_JMP) : /* jmp $sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
-#define OPRND(f) par_exec->operands.fmt_jmp.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    USI opval = ANDSI (* FLD (i_sr), -4);
-    OPRND (pc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_JMP) : /* jmp $sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
-#define OPRND(f) par_exec->operands.fmt_jmp.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
-
-  SEM_BRANCH_FINI (vpc);
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_LD) : /* ld $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ld.f
-#define OPRND(f) par_exec->operands.fmt_ld.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_LD) : /* ld $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_ld.f
-#define OPRND(f) par_exec->operands.fmt_ld.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_LDB) : /* ldb $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ldb.f
-#define OPRND(f) par_exec->operands.fmt_ldb.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_LDB) : /* ldb $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_ldb.f
-#define OPRND(f) par_exec->operands.fmt_ldb.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_LDH) : /* ldh $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ldh.f
-#define OPRND(f) par_exec->operands.fmt_ldh.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_LDH) : /* ldh $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_ldh.f
-#define OPRND(f) par_exec->operands.fmt_ldh.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_LDUB) : /* ldub $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ldb.f
-#define OPRND(f) par_exec->operands.fmt_ldb.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_LDUB) : /* ldub $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_ldb.f
-#define OPRND(f) par_exec->operands.fmt_ldb.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_LDUH) : /* lduh $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ldh.f
-#define OPRND(f) par_exec->operands.fmt_ldh.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_LDUH) : /* lduh $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_ldh.f
-#define OPRND(f) par_exec->operands.fmt_ldh.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_LD_PLUS) : /* ld $dr,@$sr+ */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ld_plus.f
-#define OPRND(f) par_exec->operands.fmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  SI temp1;SI temp0;
-  temp0 = GETMEMSI (current_cpu, pc, * FLD (i_sr));
-  temp1 = ADDSI (* FLD (i_sr), 4);
-  {
-    SI opval = temp0;
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-  {
-    SI opval = temp1;
-    OPRND (sr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
-  }
-} while (0);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_LD_PLUS) : /* ld $dr,@$sr+ */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_ld_plus.f
-#define OPRND(f) par_exec->operands.fmt_ld_plus.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-  * FLD (i_sr) = OPRND (sr);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_LDI8) : /* ldi8 $dr,$simm8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ldi8.f
-#define OPRND(f) par_exec->operands.fmt_ldi8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = FLD (f_simm8);
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_LDI8) : /* ldi8 $dr,$simm8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_ldi8.f
-#define OPRND(f) par_exec->operands.fmt_ldi8.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_LOCK) : /* lock $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_lock.f
-#define OPRND(f) par_exec->operands.fmt_lock.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  {
-    BI opval = 1;
-    OPRND (h_lock_0) = opval;
-    TRACE_RESULT (current_cpu, abuf, "lock-0", 'x', opval);
-  }
-  {
-    SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-} while (0);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_LOCK) : /* lock $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_lock.f
-#define OPRND(f) par_exec->operands.fmt_lock.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-  CPU (h_lock) = OPRND (h_lock_0);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MACHI_A) : /* machi $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_machi_a.f
-#define OPRND(f) par_exec->operands.fmt_machi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8);
-    OPRND (acc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_MACHI_A) : /* machi $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_machi_a.f
-#define OPRND(f) par_exec->operands.fmt_machi_a.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MACLO_A) : /* maclo $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_machi_a.f
-#define OPRND(f) par_exec->operands.fmt_machi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8);
-    OPRND (acc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_MACLO_A) : /* maclo $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_machi_a.f
-#define OPRND(f) par_exec->operands.fmt_machi_a.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MACWHI_A) : /* macwhi $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_machi_a.f
-#define OPRND(f) par_exec->operands.fmt_machi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))));
-    OPRND (acc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_MACWHI_A) : /* macwhi $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_machi_a.f
-#define OPRND(f) par_exec->operands.fmt_machi_a.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MACWLO_A) : /* macwlo $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_machi_a.f
-#define OPRND(f) par_exec->operands.fmt_machi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))));
-    OPRND (acc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_MACWLO_A) : /* macwlo $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_machi_a.f
-#define OPRND(f) par_exec->operands.fmt_machi_a.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MUL) : /* mul $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_add.f
-#define OPRND(f) par_exec->operands.fmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = MULSI (* FLD (i_dr), * FLD (i_sr));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_MUL) : /* mul $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_add.f
-#define OPRND(f) par_exec->operands.fmt_add.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MULHI_A) : /* mulhi $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mulhi_a.f
-#define OPRND(f) par_exec->operands.fmt_mulhi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 16), 16);
-    OPRND (acc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_MULHI_A) : /* mulhi $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_mulhi_a.f
-#define OPRND(f) par_exec->operands.fmt_mulhi_a.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MULLO_A) : /* mullo $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mulhi_a.f
-#define OPRND(f) par_exec->operands.fmt_mulhi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 16), 16);
-    OPRND (acc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_MULLO_A) : /* mullo $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_mulhi_a.f
-#define OPRND(f) par_exec->operands.fmt_mulhi_a.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MULWHI_A) : /* mulwhi $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mulhi_a.f
-#define OPRND(f) par_exec->operands.fmt_mulhi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))));
-    OPRND (acc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_MULWHI_A) : /* mulwhi $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_mulhi_a.f
-#define OPRND(f) par_exec->operands.fmt_mulhi_a.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MULWLO_A) : /* mulwlo $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mulhi_a.f
-#define OPRND(f) par_exec->operands.fmt_mulhi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))));
-    OPRND (acc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_MULWLO_A) : /* mulwlo $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_mulhi_a.f
-#define OPRND(f) par_exec->operands.fmt_mulhi_a.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MV) : /* mv $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mv.f
-#define OPRND(f) par_exec->operands.fmt_mv.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = * FLD (i_sr);
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_MV) : /* mv $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_mv.f
-#define OPRND(f) par_exec->operands.fmt_mv.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MVFACHI_A) : /* mvfachi $dr,$accs */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mvfachi_a.f
-#define OPRND(f) par_exec->operands.fmt_mvfachi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = TRUNCDISI (SRADI (GET_H_ACCUMS (FLD (f_accs)), 32));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_MVFACHI_A) : /* mvfachi $dr,$accs */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_mvfachi_a.f
-#define OPRND(f) par_exec->operands.fmt_mvfachi_a.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MVFACLO_A) : /* mvfaclo $dr,$accs */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mvfachi_a.f
-#define OPRND(f) par_exec->operands.fmt_mvfachi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = TRUNCDISI (GET_H_ACCUMS (FLD (f_accs)));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_MVFACLO_A) : /* mvfaclo $dr,$accs */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_mvfachi_a.f
-#define OPRND(f) par_exec->operands.fmt_mvfachi_a.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MVFACMI_A) : /* mvfacmi $dr,$accs */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mvfachi_a.f
-#define OPRND(f) par_exec->operands.fmt_mvfachi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = TRUNCDISI (SRADI (GET_H_ACCUMS (FLD (f_accs)), 16));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_MVFACMI_A) : /* mvfacmi $dr,$accs */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_mvfachi_a.f
-#define OPRND(f) par_exec->operands.fmt_mvfachi_a.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MVFC) : /* mvfc $dr,$scr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mvfc.f
-#define OPRND(f) par_exec->operands.fmt_mvfc.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GET_H_CR (FLD (f_r2));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_MVFC) : /* mvfc $dr,$scr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_mvfc.f
-#define OPRND(f) par_exec->operands.fmt_mvfc.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MVTACHI_A) : /* mvtachi $src1,$accs */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mvtachi_a.f
-#define OPRND(f) par_exec->operands.fmt_mvtachi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ORDI (ANDDI (GET_H_ACCUMS (FLD (f_accs)), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (i_src1)), 32));
-    OPRND (accs) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accs", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_MVTACHI_A) : /* mvtachi $src1,$accs */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_mvtachi_a.f
-#define OPRND(f) par_exec->operands.fmt_mvtachi_a.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (FLD (f_accs), OPRND (accs));
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MVTACLO_A) : /* mvtaclo $src1,$accs */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mvtachi_a.f
-#define OPRND(f) par_exec->operands.fmt_mvtachi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ORDI (ANDDI (GET_H_ACCUMS (FLD (f_accs)), MAKEDI (0xffffffff, 0)), ZEXTSIDI (* FLD (i_src1)));
-    OPRND (accs) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accs", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_MVTACLO_A) : /* mvtaclo $src1,$accs */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_mvtachi_a.f
-#define OPRND(f) par_exec->operands.fmt_mvtachi_a.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (FLD (f_accs), OPRND (accs));
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MVTC) : /* mvtc $sr,$dcr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mvtc.f
-#define OPRND(f) par_exec->operands.fmt_mvtc.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    USI opval = * FLD (i_sr);
-    OPRND (dcr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dcr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_MVTC) : /* mvtc $sr,$dcr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_mvtc.f
-#define OPRND(f) par_exec->operands.fmt_mvtc.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_CR (FLD (f_r1), OPRND (dcr));
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_NEG) : /* neg $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mv.f
-#define OPRND(f) par_exec->operands.fmt_mv.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = NEGSI (* FLD (i_sr));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_NEG) : /* neg $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_mv.f
-#define OPRND(f) par_exec->operands.fmt_mv.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_NOP) : /* nop */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_nop.f
-#define OPRND(f) par_exec->operands.fmt_nop.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_NOP) : /* nop */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_nop.f
-#define OPRND(f) par_exec->operands.fmt_nop.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_NOT) : /* not $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mv.f
-#define OPRND(f) par_exec->operands.fmt_mv.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = INVSI (* FLD (i_sr));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_NOT) : /* not $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_mv.f
-#define OPRND(f) par_exec->operands.fmt_mv.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_RAC_DSI) : /* rac $accd,$accs,$imm1 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_rac_dsi.f
-#define OPRND(f) par_exec->operands.fmt_rac_dsi.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  DI tmp_tmp1;
-  tmp_tmp1 = SLLDI (GET_H_ACCUMS (FLD (f_accs)), FLD (f_imm1));
-  tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768));
-  {
-    DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000)));
-    OPRND (accd) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accd", 'D', opval);
-  }
-} while (0);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_RAC_DSI) : /* rac $accd,$accs,$imm1 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_rac_dsi.f
-#define OPRND(f) par_exec->operands.fmt_rac_dsi.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (FLD (f_accd), OPRND (accd));
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_RACH_DSI) : /* rach $accd,$accs,$imm1 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_rac_dsi.f
-#define OPRND(f) par_exec->operands.fmt_rac_dsi.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  DI tmp_tmp1;
-  tmp_tmp1 = SLLDI (GET_H_ACCUMS (FLD (f_accs)), FLD (f_imm1));
-  tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 0x80000000));
-  {
-    DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0))) ? (MAKEDI (32767, 0)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0)));
-    OPRND (accd) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accd", 'D', opval);
-  }
-} while (0);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_RACH_DSI) : /* rach $accd,$accs,$imm1 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_rac_dsi.f
-#define OPRND(f) par_exec->operands.fmt_rac_dsi.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (FLD (f_accd), OPRND (accd));
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_RTE) : /* rte */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_rte.f
-#define OPRND(f) par_exec->operands.fmt_rte.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  {
-    USI opval = ANDSI (GET_H_CR (((UINT) 6)), -4);
-    OPRND (pc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-  {
-    USI opval = GET_H_CR (((UINT) 14));
-    OPRND (h_cr_6) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cr-6", 'x', opval);
-  }
-  {
-    UQI opval = CPU (h_bpsw);
-    OPRND (h_psw_0) = opval;
-    TRACE_RESULT (current_cpu, abuf, "psw-0", 'x', opval);
-  }
-  {
-    UQI opval = CPU (h_bbpsw);
-    OPRND (h_bpsw_0) = opval;
-    TRACE_RESULT (current_cpu, abuf, "bpsw-0", 'x', opval);
-  }
-} while (0);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_RTE) : /* rte */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.cti.fields.fmt_rte.f
-#define OPRND(f) par_exec->operands.fmt_rte.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_bpsw) = OPRND (h_bpsw_0);
-  SET_H_CR (((UINT) 6), OPRND (h_cr_6));
-  SET_H_PSW (OPRND (h_psw_0));
-  SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
-
-  SEM_BRANCH_FINI (vpc);
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_SLL) : /* sll $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_add.f
-#define OPRND(f) par_exec->operands.fmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SLLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_SLL) : /* sll $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_add.f
-#define OPRND(f) par_exec->operands.fmt_add.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_SLLI) : /* slli $dr,$uimm5 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_slli.f
-#define OPRND(f) par_exec->operands.fmt_slli.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SLLSI (* FLD (i_dr), FLD (f_uimm5));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_SLLI) : /* slli $dr,$uimm5 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_slli.f
-#define OPRND(f) par_exec->operands.fmt_slli.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_SRA) : /* sra $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_add.f
-#define OPRND(f) par_exec->operands.fmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRASI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_SRA) : /* sra $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_add.f
-#define OPRND(f) par_exec->operands.fmt_add.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_SRAI) : /* srai $dr,$uimm5 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_slli.f
-#define OPRND(f) par_exec->operands.fmt_slli.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRASI (* FLD (i_dr), FLD (f_uimm5));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_SRAI) : /* srai $dr,$uimm5 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_slli.f
-#define OPRND(f) par_exec->operands.fmt_slli.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_SRL) : /* srl $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_add.f
-#define OPRND(f) par_exec->operands.fmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_SRL) : /* srl $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_add.f
-#define OPRND(f) par_exec->operands.fmt_add.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_SRLI) : /* srli $dr,$uimm5 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_slli.f
-#define OPRND(f) par_exec->operands.fmt_slli.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRLSI (* FLD (i_dr), FLD (f_uimm5));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_SRLI) : /* srli $dr,$uimm5 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_slli.f
-#define OPRND(f) par_exec->operands.fmt_slli.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_ST) : /* st $src1,@$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_st.f
-#define OPRND(f) par_exec->operands.fmt_st.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = * FLD (i_src1);
-    OPRND (h_memory_src2_idx) = * FLD (i_src2);
-    OPRND (h_memory_src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_ST) : /* st $src1,@$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_st.f
-#define OPRND(f) par_exec->operands.fmt_st.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SETMEMSI (current_cpu, pc, OPRND (h_memory_src2_idx), OPRND (h_memory_src2));
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_STB) : /* stb $src1,@$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_stb.f
-#define OPRND(f) par_exec->operands.fmt_stb.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    QI opval = * FLD (i_src1);
-    OPRND (h_memory_src2_idx) = * FLD (i_src2);
-    OPRND (h_memory_src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_STB) : /* stb $src1,@$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_stb.f
-#define OPRND(f) par_exec->operands.fmt_stb.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SETMEMQI (current_cpu, pc, OPRND (h_memory_src2_idx), OPRND (h_memory_src2));
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_STH) : /* sth $src1,@$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_sth.f
-#define OPRND(f) par_exec->operands.fmt_sth.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    HI opval = * FLD (i_src1);
-    OPRND (h_memory_src2_idx) = * FLD (i_src2);
-    OPRND (h_memory_src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_STH) : /* sth $src1,@$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_sth.f
-#define OPRND(f) par_exec->operands.fmt_sth.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SETMEMHI (current_cpu, pc, OPRND (h_memory_src2_idx), OPRND (h_memory_src2));
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_ST_PLUS) : /* st $src1,@+$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_st_plus.f
-#define OPRND(f) par_exec->operands.fmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  SI tmp_new_src2;
-  tmp_new_src2 = ADDSI (* FLD (i_src2), 4);
-  {
-    SI opval = * FLD (i_src1);
-    OPRND (h_memory_new_src2_idx) = tmp_new_src2;
-    OPRND (h_memory_new_src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  {
-    SI opval = tmp_new_src2;
-    OPRND (src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "src2", 'x', opval);
-  }
-} while (0);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_ST_PLUS) : /* st $src1,@+$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_st_plus.f
-#define OPRND(f) par_exec->operands.fmt_st_plus.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SETMEMSI (current_cpu, pc, OPRND (h_memory_new_src2_idx), OPRND (h_memory_new_src2));
-  * FLD (i_src2) = OPRND (src2);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_ST_MINUS) : /* st $src1,@-$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_st_plus.f
-#define OPRND(f) par_exec->operands.fmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  SI tmp_new_src2;
-  tmp_new_src2 = SUBSI (* FLD (i_src2), 4);
-  {
-    SI opval = * FLD (i_src1);
-    OPRND (h_memory_new_src2_idx) = tmp_new_src2;
-    OPRND (h_memory_new_src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  {
-    SI opval = tmp_new_src2;
-    OPRND (src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "src2", 'x', opval);
-  }
-} while (0);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_ST_MINUS) : /* st $src1,@-$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_st_plus.f
-#define OPRND(f) par_exec->operands.fmt_st_plus.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SETMEMSI (current_cpu, pc, OPRND (h_memory_new_src2_idx), OPRND (h_memory_new_src2));
-  * FLD (i_src2) = OPRND (src2);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_SUB) : /* sub $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_add.f
-#define OPRND(f) par_exec->operands.fmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SUBSI (* FLD (i_dr), * FLD (i_sr));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_SUB) : /* sub $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_add.f
-#define OPRND(f) par_exec->operands.fmt_add.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_SUBV) : /* subv $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_addv.f
-#define OPRND(f) par_exec->operands.fmt_addv.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  BI temp1;SI temp0;
-  temp0 = SUBSI (* FLD (i_dr), * FLD (i_sr));
-  temp1 = SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0);
-  {
-    SI opval = temp0;
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    OPRND (condbit) = opval;
-    TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
-  }
-} while (0);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_SUBV) : /* subv $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_addv.f
-#define OPRND(f) par_exec->operands.fmt_addv.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_cond) = OPRND (condbit);
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_SUBX) : /* subx $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_addx.f
-#define OPRND(f) par_exec->operands.fmt_addx.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  BI temp1;SI temp0;
-  temp0 = SUBCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
-  temp1 = SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
-  {
-    SI opval = temp0;
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    OPRND (condbit) = opval;
-    TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
-  }
-} while (0);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_SUBX) : /* subx $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_addx.f
-#define OPRND(f) par_exec->operands.fmt_addx.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_cond) = OPRND (condbit);
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_TRAP) : /* trap $uimm4 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_trap.f
-#define OPRND(f) par_exec->operands.fmt_trap.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-  {
-    USI opval = GET_H_CR (((UINT) 6));
-    OPRND (h_cr_14) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cr-14", 'x', opval);
-  }
-  {
-    USI opval = ADDSI (pc, 4);
-    OPRND (h_cr_6) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cr-6", 'x', opval);
-  }
-  {
-    UQI opval = CPU (h_bpsw);
-    OPRND (h_bbpsw_0) = opval;
-    TRACE_RESULT (current_cpu, abuf, "bbpsw-0", 'x', opval);
-  }
-  {
-    UQI opval = GET_H_PSW ();
-    OPRND (h_bpsw_0) = opval;
-    TRACE_RESULT (current_cpu, abuf, "bpsw-0", 'x', opval);
-  }
-  {
-    UQI opval = ANDQI (GET_H_PSW (), 128);
-    OPRND (h_psw_0) = opval;
-    TRACE_RESULT (current_cpu, abuf, "psw-0", 'x', opval);
-  }
-  {
-    SI opval = m32r_trap (current_cpu, pc, FLD (f_uimm4));
-    OPRND (pc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-} while (0);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_TRAP) : /* trap $uimm4 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.cti.fields.fmt_trap.f
-#define OPRND(f) par_exec->operands.fmt_trap.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_bbpsw) = OPRND (h_bbpsw_0);
-  CPU (h_bpsw) = OPRND (h_bpsw_0);
-  SET_H_CR (((UINT) 14), OPRND (h_cr_14));
-  SET_H_CR (((UINT) 6), OPRND (h_cr_6));
-  SET_H_PSW (OPRND (h_psw_0));
-  SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
-
-  SEM_BRANCH_FINI (vpc);
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_UNLOCK) : /* unlock $src1,@$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_unlock.f
-#define OPRND(f) par_exec->operands.fmt_unlock.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-do {
-if (CPU (h_lock)) {
-  {
-    SI opval = * FLD (i_src1);
-    OPRND (h_memory_src2_idx) = * FLD (i_src2);
-    OPRND (h_memory_src2) = opval;
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-}
-  {
-    BI opval = 0;
-    OPRND (h_lock_0) = opval;
-    TRACE_RESULT (current_cpu, abuf, "lock-0", 'x', opval);
-  }
-} while (0);
-
-  abuf->written = written;
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_UNLOCK) : /* unlock $src1,@$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_unlock.f
-#define OPRND(f) par_exec->operands.fmt_unlock.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_lock) = OPRND (h_lock_0);
-  if (written & (1 << 4))
-    {
-      SETMEMSI (current_cpu, pc, OPRND (h_memory_src2_idx), OPRND (h_memory_src2));
-    }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_PCMPBZ) : /* pcmpbz $src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_cmpz.f
-#define OPRND(f) par_exec->operands.fmt_cmpz.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = (EQSI (ANDSI (* FLD (i_src2), 255), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 65280), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 16711680), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 0xff000000), 0)) ? (1) : (0);
-    OPRND (condbit) = opval;
-    TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_PCMPBZ) : /* pcmpbz $src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_cmpz.f
-#define OPRND(f) par_exec->operands.fmt_cmpz.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_cond) = OPRND (condbit);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_SADD) : /* sadd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_sadd.f
-#define OPRND(f) par_exec->operands.fmt_sadd.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ADDDI (SRADI (GET_H_ACCUMS (((UINT) 1)), 16), GET_H_ACCUMS (((UINT) 0)));
-    OPRND (h_accums_0) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accums-0", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_SADD) : /* sadd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_sadd.f
-#define OPRND(f) par_exec->operands.fmt_sadd.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (((UINT) 0), OPRND (h_accums_0));
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MACWU1) : /* macwu1 $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_macwu1.f
-#define OPRND(f) par_exec->operands.fmt_macwu1.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535)))), 8), 8);
-    OPRND (h_accums_1) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accums-1", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_MACWU1) : /* macwu1 $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_macwu1.f
-#define OPRND(f) par_exec->operands.fmt_macwu1.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (((UINT) 1), OPRND (h_accums_1));
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MSBLO) : /* msblo $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_msblo.f
-#define OPRND(f) par_exec->operands.fmt_msblo.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (SUBDI (GET_H_ACCUM (), SRADI (SLLDI (MULDI (EXTHIDI (TRUNCSIHI (* FLD (i_src1))), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 32), 16)), 8), 8);
-    OPRND (accum) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_MSBLO) : /* msblo $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_msblo.f
-#define OPRND(f) par_exec->operands.fmt_msblo.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUM (OPRND (accum));
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MULWU1) : /* mulwu1 $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mulwu1.f
-#define OPRND(f) par_exec->operands.fmt_mulwu1.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535))), 16), 16);
-    OPRND (h_accums_1) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accums-1", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_MULWU1) : /* mulwu1 $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_mulwu1.f
-#define OPRND(f) par_exec->operands.fmt_mulwu1.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (((UINT) 1), OPRND (h_accums_1));
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MACLH1) : /* maclh1 $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_macwu1.f
-#define OPRND(f) par_exec->operands.fmt_macwu1.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), SLLDI (EXTSIDI (MULSI (EXTHISI (TRUNCSIHI (* FLD (i_src1))), SRASI (* FLD (i_src2), 16))), 16)), 8), 8);
-    OPRND (h_accums_1) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accums-1", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_MACLH1) : /* maclh1 $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_macwu1.f
-#define OPRND(f) par_exec->operands.fmt_macwu1.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (((UINT) 1), OPRND (h_accums_1));
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_SC) : /* sc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_sc.f
-#define OPRND(f) par_exec->operands.fmt_sc.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (CPU (h_cond)) {
-SEM_SKIP_INSN (current_cpu, 1);
-}
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_SC) : /* sc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.cti.fields.fmt_sc.f
-#define OPRND(f) par_exec->operands.fmt_sc.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-
-  SEM_BRANCH_FINI (vpc);
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_SNC) : /* snc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_sc.f
-#define OPRND(f) par_exec->operands.fmt_sc.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (CPU (h_cond))) {
-SEM_SKIP_INSN (current_cpu, 1);
-}
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_WRITE_SNC) : /* snc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.cti.fields.fmt_sc.f
-#define OPRND(f) par_exec->operands.fmt_sc.f
-  int UNUSED written = abuf->written;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-
-  SEM_BRANCH_FINI (vpc);
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-
-    }
-  ENDSWITCH (sem) /* End of semantic switch.  */
-
-  /* At this point `vpc' contains the next insn to execute.  */
-}
-
-#undef DEFINE_SWITCH
-#endif /* DEFINE_SWITCH */
diff --git a/sim/m32r/sim-if.c b/sim/m32r/sim-if.c
deleted file mode 100644
index 1224d60..0000000
--- a/sim/m32r/sim-if.c
+++ /dev/null
@@ -1,286 +0,0 @@
-/* Main simulator entry points specific to the M32R.
-   Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
-   Contributed by Cygnus Support.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
-
-#include "sim-main.h"
-#include "sim-options.h"
-#include "libiberty.h"
-#include "bfd.h"
-
-#ifdef HAVE_STRING_H
-#include <string.h>
-#else
-#ifdef HAVE_STRINGS_H
-#include <strings.h>
-#endif
-#endif
-#ifdef HAVE_STDLIB_H
-#include <stdlib.h>
-#endif
-
-static void free_state (SIM_DESC);
-static void print_m32r_misc_cpu (SIM_CPU *cpu, int verbose);
-
-/* Records simulator descriptor so utilities like m32r_dump_regs can be
-   called from gdb.  */
-SIM_DESC current_state;
-
-/* Cover function of sim_state_free to free the cpu buffers as well.  */
-
-static void
-free_state (SIM_DESC sd)
-{
-  if (STATE_MODULES (sd) != NULL)
-    sim_module_uninstall (sd);
-  sim_cpu_free_all (sd);
-  sim_state_free (sd);
-}
-
-/* Create an instance of the simulator.  */
-
-SIM_DESC
-sim_open (kind, callback, abfd, argv)
-     SIM_OPEN_KIND kind;
-     host_callback *callback;
-     struct _bfd *abfd;
-     char **argv;
-{
-  SIM_DESC sd = sim_state_alloc (kind, callback);
-  char c;
-
-  /* The cpu data is kept in a separately allocated chunk of memory.  */
-  if (sim_cpu_alloc_all (sd, 1, cgen_cpu_max_extra_bytes ()) != SIM_RC_OK)
-    {
-      free_state (sd);
-      return 0;
-    }
-
-#if 0 /* FIXME: pc is in mach-specific struct */
-  /* FIXME: watchpoints code shouldn't need this */
-  {
-    SIM_CPU *current_cpu = STATE_CPU (sd, 0);
-    STATE_WATCHPOINTS (sd)->pc = &(PC);
-    STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
-  }
-#endif
-
-  if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
-    {
-      free_state (sd);
-      return 0;
-    }
-
-#ifdef HAVE_DV_SOCKSER /* FIXME: was done differently before */
-  if (dv_sockser_install (sd) != SIM_RC_OK)
-    {
-      free_state (sd);
-      return 0;
-    }
-#endif
-
-#if 0 /* FIXME: 'twould be nice if we could do this */
-  /* These options override any module options.
-     Obviously ambiguity should be avoided, however the caller may wish to
-     augment the meaning of an option.  */
-  if (extra_options != NULL)
-    sim_add_option_table (sd, extra_options);
-#endif
-
-  /* getopt will print the error message so we just have to exit if this fails.
-     FIXME: Hmmm...  in the case of gdb we need getopt to call
-     print_filtered.  */
-  if (sim_parse_args (sd, argv) != SIM_RC_OK)
-    {
-      free_state (sd);
-      return 0;
-    }
-
-  /* Allocate a handler for the control registers and other devices
-     if no memory for that range has been allocated by the user.
-     All are allocated in one chunk to keep things from being
-     unnecessarily complicated.  */
-  if (sim_core_read_buffer (sd, NULL, read_map, &c, M32R_DEVICE_ADDR, 1) == 0)
-    sim_core_attach (sd, NULL,
-		     0 /*level*/,
-		     access_read_write,
-		     0 /*space ???*/,
-		     M32R_DEVICE_ADDR, M32R_DEVICE_LEN /*nr_bytes*/,
-		     0 /*modulo*/,
-		     &m32r_devices,
-		     NULL /*buffer*/);
-
-  /* Allocate core managed memory if none specified by user.
-     Use address 4 here in case the user wanted address 0 unmapped.  */
-  if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0)
-    sim_do_commandf (sd, "memory region 0,0x%x", M32R_DEFAULT_MEM_SIZE);
-
-  /* check for/establish the reference program image */
-  if (sim_analyze_program (sd,
-			   (STATE_PROG_ARGV (sd) != NULL
-			    ? *STATE_PROG_ARGV (sd)
-			    : NULL),
-			   abfd) != SIM_RC_OK)
-    {
-      free_state (sd);
-      return 0;
-    }
-
-  /* Establish any remaining configuration options.  */
-  if (sim_config (sd) != SIM_RC_OK)
-    {
-      free_state (sd);
-      return 0;
-    }
-
-  if (sim_post_argv_init (sd) != SIM_RC_OK)
-    {
-      free_state (sd);
-      return 0;
-    }
-
-  /* Initialize various cgen things not done by common framework.  */
-  cgen_init (sd);
-
-  /* Open a copy of the opcode table.  */
-  STATE_OPCODE_TABLE (sd) = m32r_cgen_opcode_open (STATE_ARCHITECTURE (sd)->mach,
-						   CGEN_ENDIAN_BIG);
-  m32r_cgen_init_dis (STATE_OPCODE_TABLE (sd));
-
-  {
-    int c;
-
-    for (c = 0; c < MAX_NR_PROCESSORS; ++c)
-      {
-	/* Only needed for profiling, but the structure member is small.  */
-	memset (CPU_M32R_MISC_PROFILE (STATE_CPU (sd, c)), 0,
-		sizeof (* CPU_M32R_MISC_PROFILE (STATE_CPU (sd, c))));
-	/* Hook in callback for reporting these stats */
-	PROFILE_INFO_CPU_CALLBACK (CPU_PROFILE_DATA (STATE_CPU (sd, c)))
-	  = print_m32r_misc_cpu;
-      }
-  }
-
-  /* Store in a global so things like sparc32_dump_regs can be invoked
-     from the gdb command line.  */
-  current_state = sd;
-
-  return sd;
-}
-
-void
-sim_close (sd, quitting)
-     SIM_DESC sd;
-     int quitting;
-{
-  m32r_cgen_opcode_close (STATE_OPCODE_TABLE (sd));
-  sim_module_uninstall (sd);
-}
-
-SIM_RC
-sim_create_inferior (sd, abfd, argv, envp)
-     SIM_DESC sd;
-     struct _bfd *abfd;
-     char **argv;
-     char **envp;
-{
-  SIM_CPU *current_cpu = STATE_CPU (sd, 0);
-  SIM_ADDR addr;
-
-  if (abfd != NULL)
-    addr = bfd_get_start_address (abfd);
-  else
-    addr = 0;
-  sim_pc_set (current_cpu, addr);
-
-#if 0
-  STATE_ARGV (sd) = sim_copy_argv (argv);
-  STATE_ENVP (sd) = sim_copy_argv (envp);
-#endif
-
-  return SIM_RC_OK;
-}
-
-/* PROFILE_CPU_CALLBACK */
-
-static void
-print_m32r_misc_cpu (SIM_CPU *cpu, int verbose)
-{
-  SIM_DESC sd = CPU_STATE (cpu);
-  char buf[20];
-
-  if (CPU_PROFILE_FLAGS (cpu) [PROFILE_INSN_IDX])
-    {
-      sim_io_printf (sd, "Miscellaneous Statistics\n\n");
-      sim_io_printf (sd, "  %-*s %s\n\n",
-		     PROFILE_LABEL_WIDTH, "Fill nops:",
-		     sim_add_commas (buf, sizeof (buf),
-				     CPU_M32R_MISC_PROFILE (cpu)->fillnop_count));
-      if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_m32rx)
-	sim_io_printf (sd, "  %-*s %s\n\n",
-		       PROFILE_LABEL_WIDTH, "Parallel insns:",
-		       sim_add_commas (buf, sizeof (buf),
-				       CPU_M32R_MISC_PROFILE (cpu)->parallel_count));
-    }
-}
-
-void
-sim_do_command (sd, cmd)
-     SIM_DESC sd;
-     char *cmd;
-{ 
-  char **argv;
-
-  if (cmd == NULL)
-    return;
-
-  argv = buildargv (cmd);
-
-  if (argv[0] != NULL
-      && strcasecmp (argv[0], "info") == 0
-      && argv[1] != NULL
-      && strncasecmp (argv[1], "reg", 3) == 0)
-    {
-      SI val;
-
-      /* We only support printing bbpsw,bbpc here as there is no equivalent
-	 functionality in gdb.  */
-      if (argv[2] == NULL)
-	sim_io_eprintf (sd, "Missing register in `%s'\n", cmd);
-      else if (argv[3] != NULL)
-	sim_io_eprintf (sd, "Too many arguments in `%s'\n", cmd);
-      else if (strcasecmp (argv[2], "bbpsw") == 0)
-	{
-	  val = a_m32r_h_cr_get (STATE_CPU (sd, 0), H_CR_BBPSW);
-	  sim_io_printf (sd, "bbpsw 0x%x %d\n", val, val);
-	}
-      else if (strcasecmp (argv[2], "bbpc") == 0)
-	{
-	  val = a_m32r_h_cr_get (STATE_CPU (sd, 0), H_CR_BBPC);
-	  sim_io_printf (sd, "bbpc 0x%x %d\n", val, val);
-	}
-      else
-	sim_io_eprintf (sd, "Printing of register `%s' not supported with `sim info'\n",
-			argv[2]);
-    }
-  else
-    {
-      if (sim_args_command (sd, cmd) != SIM_RC_OK)
-	sim_io_eprintf (sd, "Unknown sim command `%s'\n", cmd);
-    }
-
-  freeargv (argv);
-}
diff --git a/sim/m32r/sim-main.h b/sim/m32r/sim-main.h
deleted file mode 100644
index 03f06b9..0000000
--- a/sim/m32r/sim-main.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/* Main header for the m32r.  */
-
-#ifndef SIM_MAIN_H
-#define SIM_MAIN_H
-
-#define USING_SIM_BASE_H /* FIXME: quick hack */
-
-struct _sim_cpu; /* FIXME: should be in sim-basics.h */
-typedef struct _sim_cpu SIM_CPU;
-
-#include "ansidecl.h"
-#include "symcat.h"
-#include "sim-basics.h"
-#include "cgen-types.h"
-#include "cpu-opc.h"
-#include "arch.h"
-
-/* These must be defined before sim-base.h.  */
-typedef USI sim_cia;
-
-#define CIA_GET(cpu)     CPU_PC_GET (cpu)
-#define CIA_SET(cpu,val) CPU_PC_SET ((cpu), (val))
-
-#include "sim-base.h"
-#include "cgen-sim.h"
-#include "cpu-sim.h"
-
-/* The _sim_cpu struct.  */
-
-struct _sim_cpu {
-  /* sim/common cpu base.  */
-  sim_cpu_base base;
-
-  /* Static parts of cgen.  */
-  CGEN_CPU cgen_cpu;
-
-  M32R_MISC_PROFILE m32r_misc_profile;
-#define CPU_M32R_MISC_PROFILE(cpu) (& (cpu)->m32r_misc_profile)
-
-  /* CPU specific parts go here.
-     Note that in files that don't need to access these pieces WANT_CPU_FOO
-     won't be defined and thus these parts won't appear.  This is ok in the
-     sense that things work.  It is a source of bugs though.
-     One has to of course be careful to not take the size of this
-     struct and no structure members accessed in non-cpu specific files can
-     go after here.  Oh for a better language.  */
-#if defined (WANT_CPU_M32RBF)
-  M32RBF_CPU_DATA cpu_data;
-/* start-sanitize-m32rx */
-#elif defined (WANT_CPU_M32RXF)
-  M32RXF_CPU_DATA cpu_data;
-/* end-sanitize-m32rx */
-#endif
-};
-
-/* The sim_state struct.  */
-
-struct sim_state {
-  sim_cpu *cpu;
-#define STATE_CPU(sd, n) (/*&*/ (sd)->cpu)
-
-  CGEN_STATE cgen_state;
-
-  sim_state_base base;
-};
-
-/* Misc.  */
-
-/* Catch address exceptions.  */
-extern SIM_CORE_SIGNAL_FN m32r_core_signal;
-#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
-m32r_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
-		  (TRANSFER), (ERROR))
-
-/* Default memory size.  */
-#define M32R_DEFAULT_MEM_SIZE 0x800000 /* 8M */
-
-#endif /* SIM_MAIN_H */
diff --git a/sim/m32r/tconfig.in b/sim/m32r/tconfig.in
deleted file mode 100644
index ddeafd4..0000000
--- a/sim/m32r/tconfig.in
+++ /dev/null
@@ -1,47 +0,0 @@
-/* M32R target configuration file.  -*- C -*- */
-
-#ifndef M32R_TCONFIG_H
-#define M32R_TCONFIG_H
-
-/* Define this if the simulator can vary the size of memory.
-   See the xxx simulator for an example.
-   This enables the `-m size' option.
-   The memory size is stored in STATE_MEM_SIZE.  */
-/* Not used for M32R since we use the memory module.  */
-/* #define SIM_HAVE_MEM_SIZE */
-
-/* See sim-hload.c.  We properly handle LMA.  */
-#define SIM_HANDLES_LMA 1
-
-/* For MSPR support.  FIXME: revisit.  */
-#define WITH_DEVICES 1
-
-/* FIXME: Revisit.  */
-#ifdef HAVE_DV_SOCKSER
-MODULE_INSTALL_FN dv_sockser_install;
-#define MODULE_LIST dv_sockser_install,
-#endif
-
-#if 0
-/* Enable watchpoints.  */
-#define WITH_WATCHPOINTS 1
-#endif
-
-/* ??? Temporary hack until model support unified.  */
-#define SIM_HAVE_MODEL
-
-/* Define this to enable the intrinsic breakpoint mechanism. */
-/* FIXME: may be able to remove SIM_HAVE_BREAKPOINT since it essentially
-   duplicates ifdef SIM_BREAKPOINT (right?) */
-#if 0
-#define SIM_HAVE_BREAKPOINTS
-#define SIM_BREAKPOINT { 0x10, 0xf1 }
-#define SIM_BREAKPOINT_SIZE 2
-#endif
-
-/* This is a global setting.  Different cpu families can't mix-n-match -scache
-   and -bb.  However some cpu families may use -simple while others use
-   one of -scache/-bb.  */
-#define WITH_SCACHE_PBB 1
-
-#endif /* M32R_TCONFIG_H */
diff --git a/sim/m32r/traps.c b/sim/m32r/traps.c
deleted file mode 100644
index 4d2eae6..0000000
--- a/sim/m32r/traps.c
+++ /dev/null
@@ -1,173 +0,0 @@
-/* m32r exception, interrupt, and trap (EIT) support
-   Copyright (C) 1998 Free Software Foundation, Inc.
-   Contributed by Cygnus Solutions.
-
-This file is part of GDB, the GNU debugger.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
-
-#include "sim-main.h"
-#include "targ-vals.h"
-
-/* The semantic code invokes this for illegal (unrecognized) instructions.  */
-
-void
-sim_engine_illegal_insn (SIM_CPU *current_cpu, PCADDR cia)
-{
-  SIM_DESC sd = CPU_STATE (current_cpu);
-
-#if 0
-  if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
-    {
-      h_bsm_set (current_cpu, h_sm_get (current_cpu));
-      h_bie_set (current_cpu, h_ie_get (current_cpu));
-      h_bcond_set (current_cpu, h_cond_get (current_cpu));
-      /* sm not changed */
-      h_ie_set (current_cpu, 0);
-      h_cond_set (current_cpu, 0);
-
-      h_bpc_set (current_cpu, cia);
-
-      sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
-			  EIT_RSVD_INSN_ADDR);
-    }
-  else
-#endif
-    sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL);
-}
-
-/* Process an address exception.  */
-
-void
-m32r_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia,
-		  unsigned int map, int nr_bytes, address_word addr,
-		  transfer_type transfer, sim_core_signals sig)
-{
-#if 0
-  if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
-    {
-      h_bsm_set (current_cpu, h_sm_get (current_cpu));
-      h_bie_set (current_cpu, h_ie_get (current_cpu));
-      h_bcond_set (current_cpu, h_cond_get (current_cpu));
-      /* sm not changed */
-      h_ie_set (current_cpu, 0);
-      h_cond_set (current_cpu, 0);
-
-      h_bpc_set (current_cpu, cia);
-
-      sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
-			  EIT_ADDR_EXCP_ADDR);
-    }
-  else
-#endif
-    sim_core_signal (sd, current_cpu, cia, map, nr_bytes, addr,
-		     transfer, sig);
-}
-
-/* Read/write functions for system call interface.  */
-
-static int
-syscall_read_mem (host_callback *cb, struct cb_syscall *sc,
-		  unsigned long taddr, char *buf, int bytes)
-{
-  SIM_DESC sd = (SIM_DESC) sc->p1;
-  SIM_CPU *cpu = (SIM_CPU *) sc->p2;
-
-  return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes);
-}
-
-static int
-syscall_write_mem (host_callback *cb, struct cb_syscall *sc,
-		   unsigned long taddr, const char *buf, int bytes)
-{
-  SIM_DESC sd = (SIM_DESC) sc->p1;
-  SIM_CPU *cpu = (SIM_CPU *) sc->p2;
-
-  return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes);
-}
-
-/* Trap support.
-   The result is the pc address to continue at.
-   Preprocessing like saving the various registers has already been done.  */
-
-USI
-m32r_trap (SIM_CPU *current_cpu, PCADDR pc, int num)
-{
-  SIM_DESC sd = CPU_STATE (current_cpu);
-  host_callback *cb = STATE_CALLBACK (sd);
-
-#ifdef SIM_HAVE_BREAKPOINTS
-  /* Check for breakpoints "owned" by the simulator first, regardless
-     of --environment.  */
-  if (num == TRAP_BREAKPOINT)
-    {
-      /* First try sim-break.c.  If it's a breakpoint the simulator "owns"
-	 it doesn't return.  Otherwise it returns and let's us try.  */
-      sim_handle_breakpoint (sd, current_cpu, pc);
-      /* Fall through.  */
-    }
-#endif
-
-  if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
-    {
-      /* The new pc is the trap vector entry.
-	 We assume there's a branch there to some handler.  */
-      USI new_pc = EIT_TRAP_BASE_ADDR + num * 4;
-      return new_pc;
-    }
-
-  switch (num)
-    {
-    case TRAP_SYSCALL :
-      {
-	CB_SYSCALL s;
-
-	CB_SYSCALL_INIT (&s);
-	s.func = a_m32r_h_gr_get (current_cpu, 0);
-	s.arg1 = a_m32r_h_gr_get (current_cpu, 1);
-	s.arg2 = a_m32r_h_gr_get (current_cpu, 2);
-	s.arg3 = a_m32r_h_gr_get (current_cpu, 3);
-
-	if (s.func == TARGET_SYS_exit)
-	  {
-	    sim_engine_halt (sd, current_cpu, NULL, pc, sim_exited, s.arg1);
-	  }
-
-	s.p1 = (PTR) sd;
-	s.p2 = (PTR) current_cpu;
-	s.read_mem = syscall_read_mem;
-	s.write_mem = syscall_write_mem;
-	cb_syscall (cb, &s);
-	a_m32r_h_gr_set (current_cpu, 2, s.errcode);
-	a_m32r_h_gr_set (current_cpu, 0, s.result);
-	a_m32r_h_gr_set (current_cpu, 1, s.result2);
-	break;
-      }
-
-    case TRAP_BREAKPOINT:
-      sim_engine_halt (sd, current_cpu, NULL, NULL_CIA,
-		       sim_stopped, SIM_SIGTRAP);
-      break;
-
-    default :
-      {
-	USI new_pc = EIT_TRAP_BASE_ADDR + num * 4;
-	return new_pc;
-      }
-    }
-
-  /* Fake an "rte" insn.  */
-  return (pc & -4) + 4;
-}