diff options
| author | Andrew Cagney <cagney@redhat.com> | 2003-12-07 02:27:45 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 2003-12-07 02:27:45 +0000 |
| commit | 3c041444b57e94d5415b31409e80e25b1333a52b (patch) | |
| tree | d342a95a84b8824edcc21e5d0e8f2786518dd17e /sim/m32r/traps.c | |
| parent | 48ecb30c92a29b12766e9b1b0bac69aba01bd9ea (diff) | |
| download | gdb-3c041444b57e94d5415b31409e80e25b1333a52b.zip gdb-3c041444b57e94d5415b31409e80e25b1333a52b.tar.gz gdb-3c041444b57e94d5415b31409e80e25b1333a52b.tar.bz2 | |
2003-12-02 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
* Makefile.in : Add new machine m32r2.
* m32r2.c : New file for m32r2.
* mloop2.in : Ditto
* model2.c : Ditto
* sem2-switch.c : Ditto
* m32r-sim.h : Add EVB register.
* sim-if.h : Ditto
* sim-main.h : Ditto
* traps.c : Ditto
Diffstat (limited to 'sim/m32r/traps.c')
| -rw-r--r-- | sim/m32r/traps.c | 23 |
1 files changed, 19 insertions, 4 deletions
diff --git a/sim/m32r/traps.c b/sim/m32r/traps.c index 2721ad8..0500407 100644 --- a/sim/m32r/traps.c +++ b/sim/m32r/traps.c @@ -21,6 +21,7 @@ with this program; if not, write to the Free Software Foundation, Inc., #include "sim-main.h" #include "targ-vals.h" +#define TRAP_FLUSH_CACHE 12 /* The semantic code invokes this for invalid (unrecognized) instructions. CIA is the address with the invalid insn. VPC is the virtual pc of the following insn. */ @@ -68,12 +69,18 @@ m32r_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia, /* sm not changed */ m32rbf_h_psw_set (current_cpu, m32rbf_h_psw_get (current_cpu) & 0x80); } - else + else if (MACH_NUM (CPU_MACH (current_cpu)) == MACH_M32RX) { m32rxf_h_bpsw_set (current_cpu, m32rxf_h_psw_get (current_cpu)); /* sm not changed */ m32rxf_h_psw_set (current_cpu, m32rxf_h_psw_get (current_cpu) & 0x80); } + else + { + m32r2f_h_bpsw_set (current_cpu, m32r2f_h_psw_get (current_cpu)); + /* sm not changed */ + m32r2f_h_psw_set (current_cpu, m32r2f_h_psw_get (current_cpu) & 0x80); + } a_m32r_h_cr_set (current_cpu, H_CR_BPC, cia); sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL, @@ -131,8 +138,10 @@ m32r_trap (SIM_CPU *current_cpu, PCADDR pc, int num) if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT) { /* The new pc is the trap vector entry. - We assume there's a branch there to some handler. */ - USI new_pc = EIT_TRAP_BASE_ADDR + num * 4; + We assume there's a branch there to some handler. + Use cr5 as EVB (EIT Vector Base) register. */ + /* USI new_pc = EIT_TRAP_BASE_ADDR + num * 4; */ + USI new_pc = a_m32r_h_cr_get (current_cpu, 5) + 0x40 + num * 4; return new_pc; } @@ -169,9 +178,15 @@ m32r_trap (SIM_CPU *current_cpu, PCADDR pc, int num) sim_stopped, SIM_SIGTRAP); break; + case TRAP_FLUSH_CACHE: + /* Do nothing. */ + break; + default : { - USI new_pc = EIT_TRAP_BASE_ADDR + num * 4; + /* USI new_pc = EIT_TRAP_BASE_ADDR + num * 4; */ + /* Use cr5 as EVB (EIT Vector Base) register. */ + USI new_pc = a_m32r_h_cr_get (current_cpu, 5) + 0x40 + num * 4; return new_pc; } } |