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| author | Andrew Cagney <cagney@redhat.com> | 2003-12-07 16:13:06 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 2003-12-07 16:13:06 +0000 |
| commit | 0b2e03b491aa6793bbeb5775e483dfefd1679e92 (patch) | |
| tree | d88dc590bffb94a1997038310a9b2b8e0664d204 /sim/m32r/traps.c | |
| parent | cd886a95bfd21de111e87f1788a977d4c0ce885d (diff) | |
| download | gdb-0b2e03b491aa6793bbeb5775e483dfefd1679e92.zip gdb-0b2e03b491aa6793bbeb5775e483dfefd1679e92.tar.gz gdb-0b2e03b491aa6793bbeb5775e483dfefd1679e92.tar.bz2 | |
More reversion of incomplete m32r changes. Should be back to normal.
Diffstat (limited to 'sim/m32r/traps.c')
| -rw-r--r-- | sim/m32r/traps.c | 24 |
1 files changed, 6 insertions, 18 deletions
diff --git a/sim/m32r/traps.c b/sim/m32r/traps.c index 2721ad8..c81a862 100644 --- a/sim/m32r/traps.c +++ b/sim/m32r/traps.c @@ -21,12 +21,10 @@ with this program; if not, write to the Free Software Foundation, Inc., #include "sim-main.h" #include "targ-vals.h" -/* The semantic code invokes this for invalid (unrecognized) instructions. - CIA is the address with the invalid insn. - VPC is the virtual pc of the following insn. */ +/* The semantic code invokes this for invalid (unrecognized) instructions. */ -SEM_PC -sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC vpc) +void +sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia) { SIM_DESC sd = CPU_STATE (current_cpu); @@ -48,7 +46,6 @@ sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC vpc) else #endif sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL); - return vpc; } /* Process an address exception. */ @@ -62,18 +59,9 @@ m32r_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia, { a_m32r_h_cr_set (current_cpu, H_CR_BBPC, a_m32r_h_cr_get (current_cpu, H_CR_BPC)); - if (MACH_NUM (CPU_MACH (current_cpu)) == MACH_M32R) - { - m32rbf_h_bpsw_set (current_cpu, m32rbf_h_psw_get (current_cpu)); - /* sm not changed */ - m32rbf_h_psw_set (current_cpu, m32rbf_h_psw_get (current_cpu) & 0x80); - } - else - { - m32rxf_h_bpsw_set (current_cpu, m32rxf_h_psw_get (current_cpu)); - /* sm not changed */ - m32rxf_h_psw_set (current_cpu, m32rxf_h_psw_get (current_cpu) & 0x80); - } + a_m32r_h_bpsw_set (current_cpu, a_m32r_h_psw_get (current_cpu)); + /* sm not changed */ + a_m32r_h_psw_set (current_cpu, a_m32r_h_psw_get (current_cpu) & 0x80); a_m32r_h_cr_set (current_cpu, H_CR_BPC, cia); sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL, |