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| author | Doug Evans <dje@google.com> | 1998-11-05 07:56:02 +0000 |
|---|---|---|
| committer | Doug Evans <dje@google.com> | 1998-11-05 07:56:02 +0000 |
| commit | 8de434bf89b6c5fbb4aed0a201d182f3637852c3 (patch) | |
| tree | 26c0eeeb80f1f3cc9e12645ed8ef7b82775b1fc9 /sim/m32r/tconfig.in | |
| parent | 8c7dc9ffc8cd8586b10d29ab6df43565c5a2b3ff (diff) | |
| download | gdb-8de434bf89b6c5fbb4aed0a201d182f3637852c3.zip gdb-8de434bf89b6c5fbb4aed0a201d182f3637852c3.tar.gz gdb-8de434bf89b6c5fbb4aed0a201d182f3637852c3.tar.bz2 | |
* sim-main.h: Delete inclusion of config.h, include sim-basics.h
before cgen-types.h.
* tconfig.in: Guard against multiple inclusion.
* cpu.h: Delete decls moved to genmloop.sh.
* cpux.h: Ditto.
Diffstat (limited to 'sim/m32r/tconfig.in')
| -rw-r--r-- | sim/m32r/tconfig.in | 46 |
1 files changed, 29 insertions, 17 deletions
diff --git a/sim/m32r/tconfig.in b/sim/m32r/tconfig.in index b6f03d7..ddeafd4 100644 --- a/sim/m32r/tconfig.in +++ b/sim/m32r/tconfig.in @@ -1,5 +1,8 @@ /* M32R target configuration file. -*- C -*- */ +#ifndef M32R_TCONFIG_H +#define M32R_TCONFIG_H + /* Define this if the simulator can vary the size of memory. See the xxx simulator for an example. This enables the `-m size' option. @@ -7,29 +10,38 @@ /* Not used for M32R since we use the memory module. */ /* #define SIM_HAVE_MEM_SIZE */ +/* See sim-hload.c. We properly handle LMA. */ +#define SIM_HANDLES_LMA 1 + /* For MSPR support. FIXME: revisit. */ #define WITH_DEVICES 1 -/* The semantic code should probably always use a switch(). - However, in case that's not possible in some circumstance, we allow - the target to choose. Perhaps this can be autoconf'd on whether the - switch is too big? I can't (yet) think of a reason for allowing the - user to choose, though the developer may certainly wish to. */ -#ifdef WANT_CPU_M32R -#define WITH_FAST 1 -#define WITH_SEM_SWITCH_FULL 0 -#define WITH_SEM_SWITCH_FAST 1 +/* FIXME: Revisit. */ +#ifdef HAVE_DV_SOCKSER +MODULE_INSTALL_FN dv_sockser_install; +#define MODULE_LIST dv_sockser_install, #endif -#ifdef WANT_CPU_M32RX -#define HAVE_PARALLEL_EXEC -#define WITH_FAST 0 -#define WITH_SEM_SWITCH_FULL 1 -#define WITH_SEM_SWITCH_FAST 0 -/* The m32rx currently never uses the scache. So hardcode this off. */ -#undef WITH_SCACHE -#define WITH_SCACHE 0 +#if 0 +/* Enable watchpoints. */ +#define WITH_WATCHPOINTS 1 #endif /* ??? Temporary hack until model support unified. */ #define SIM_HAVE_MODEL + +/* Define this to enable the intrinsic breakpoint mechanism. */ +/* FIXME: may be able to remove SIM_HAVE_BREAKPOINT since it essentially + duplicates ifdef SIM_BREAKPOINT (right?) */ +#if 0 +#define SIM_HAVE_BREAKPOINTS +#define SIM_BREAKPOINT { 0x10, 0xf1 } +#define SIM_BREAKPOINT_SIZE 2 +#endif + +/* This is a global setting. Different cpu families can't mix-n-match -scache + and -bb. However some cpu families may use -simple while others use + one of -scache/-bb. */ +#define WITH_SCACHE_PBB 1 + +#endif /* M32R_TCONFIG_H */ |