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| author | Doug Evans <dje@google.com> | 1998-02-20 00:45:47 +0000 |
|---|---|---|
| committer | Doug Evans <dje@google.com> | 1998-02-20 00:45:47 +0000 |
| commit | cab581557e08db9079cff43cda6f312ea404fc0c (patch) | |
| tree | ebe678cf7a0db147378806e36284602de85229b6 /sim/m32r/model.c | |
| parent | a94cefa164a3f0984fd9991e94e0815bfb954eb9 (diff) | |
| download | gdb-cab581557e08db9079cff43cda6f312ea404fc0c.zip gdb-cab581557e08db9079cff43cda6f312ea404fc0c.tar.gz gdb-cab581557e08db9079cff43cda6f312ea404fc0c.tar.bz2 | |
* m32r.c (do_lock,do_unlock): Delete.
* cpu.[ch],decode.[ch],extract.c,model.c: Regenerate.
* sem.c,sem-switch.c: Regenerate.
* cpux.[ch],decodex.[ch],readx.c,semx.c: Regenerate.
Diffstat (limited to 'sim/m32r/model.c')
| -rw-r--r-- | sim/m32r/model.c | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/sim/m32r/model.c b/sim/m32r/model.c index 8efca7e..f6dbfc6 100644 --- a/sim/m32r/model.c +++ b/sim/m32r/model.c @@ -169,10 +169,9 @@ static const INSN_TIMING m32r_d_timing[] = { { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* cmpui */ { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* cmpui.a */ { { (UQI) UNIT_M32R_D_U_EXEC, 37, 37 } }, /* div */ - { { (UQI) UNIT_M32R_D_U_EXEC, 27, 27 } }, /* divu */ + { { (UQI) UNIT_M32R_D_U_EXEC, 37, 37 } }, /* divu */ { { (UQI) UNIT_M32R_D_U_EXEC, 37, 37 } }, /* rem */ - { { (UQI) UNIT_M32R_D_U_EXEC, 27, 27 } }, /* remu */ - { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* divh */ + { { (UQI) UNIT_M32R_D_U_EXEC, 37, 37 } }, /* remu */ { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* jl */ { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* jmp */ { { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* ld */ @@ -215,9 +214,9 @@ static const INSN_TIMING m32r_d_timing[] = { { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mulwhi */ { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mulwlo */ { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mv */ - { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mvfachi */ - { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mvfaclo */ - { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mvfacmi */ + { { (UQI) UNIT_M32R_D_U_EXEC, 2, 2 } }, /* mvfachi */ + { { (UQI) UNIT_M32R_D_U_EXEC, 2, 2 } }, /* mvfaclo */ + { { (UQI) UNIT_M32R_D_U_EXEC, 2, 2 } }, /* mvfacmi */ { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mvfc */ { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mvtachi */ { { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mvtaclo */ @@ -325,7 +324,6 @@ static const INSN_TIMING test_timing[] = { { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* divu */ { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* rem */ { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* remu */ - { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* divh */ { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* jl */ { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* jmp */ { { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ld */ |