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| author | Jason Molenda <jmolenda@apple.com> | 1999-10-12 04:37:53 +0000 |
|---|---|---|
| committer | Jason Molenda <jmolenda@apple.com> | 1999-10-12 04:37:53 +0000 |
| commit | 2df3850c7bfea139c5baf6c2911c11456a1b32e9 (patch) | |
| tree | a7b20a626e29e423c610ac0eef23fbe9591684e4 /sim/m32r/m32r-sim.h | |
| parent | 50a6e31f5835fc707a0c3ca6e0d56680befb645b (diff) | |
| download | gdb-2df3850c7bfea139c5baf6c2911c11456a1b32e9.zip gdb-2df3850c7bfea139c5baf6c2911c11456a1b32e9.tar.gz gdb-2df3850c7bfea139c5baf6c2911c11456a1b32e9.tar.bz2 | |
import gdb-1999-10-11 snapshot
Diffstat (limited to 'sim/m32r/m32r-sim.h')
| -rw-r--r-- | sim/m32r/m32r-sim.h | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/sim/m32r/m32r-sim.h b/sim/m32r/m32r-sim.h index d0fae5e..b1c2410 100644 --- a/sim/m32r/m32r-sim.h +++ b/sim/m32r/m32r-sim.h @@ -55,6 +55,15 @@ extern void m32rbf_h_psw_set_handler (SIM_CPU *, UQI); extern DI m32rbf_h_accum_get_handler (SIM_CPU *); extern void m32rbf_h_accum_set_handler (SIM_CPU *, DI); +extern USI m32rxf_h_cr_get_handler (SIM_CPU *, UINT); +extern void m32rxf_h_cr_set_handler (SIM_CPU *, UINT, USI); +extern UQI m32rxf_h_psw_get_handler (SIM_CPU *); +extern void m32rxf_h_psw_set_handler (SIM_CPU *, UQI); +extern DI m32rxf_h_accum_get_handler (SIM_CPU *); +extern void m32rxf_h_accum_set_handler (SIM_CPU *, DI); + +extern DI m32rxf_h_accums_get_handler (SIM_CPU *, UINT); +extern void m32rxf_h_accums_set_handler (SIM_CPU *, UINT, DI); /* Misc. profile data. */ @@ -121,6 +130,32 @@ do { \ /* Additional execution support. */ +/* Result of semantic function is one of + - next address, branch only + - NEW_PC_SKIP, sc/snc insn + - NEW_PC_2, 2 byte non-branch non-sc/snc insn + - NEW_PC_4, 4 byte non-branch insn + The special values have bit 1 set so it's cheap to distinguish them. + This works because all cti's are defined to zero the bottom two bits + Note that the m32rx no longer doesn't implement its semantics with + functions, so this isn't used. It's kept around should it be needed + again. */ +/* FIXME: replace 0xffff0001 with 1? */ +#define NEW_PC_BASE 0xffff0001 +#define NEW_PC_SKIP NEW_PC_BASE +#define NEW_PC_2 (NEW_PC_BASE + 2) +#define NEW_PC_4 (NEW_PC_BASE + 4) +#define NEW_PC_BRANCH_P(addr) (((addr) & 1) == 0) + +/* Modify "next pc" support to handle parallel execution. + This is for the non-pbb case. The m32rx no longer implements this. + It's kept around should it be needed again. */ +#if defined (WANT_CPU_M32RXF) && ! WITH_SCACHE_PBB_M32RXF +#undef SEM_NEXT_VPC +#define SEM_NEXT_VPC(abuf, len) (NEW_PC_BASE + (len)) +#undef SEM_SKIP_INSN +#define SEM_SKIP_INSN(cpu, sc, vpcvar, yes) FIXME +#endif /* Hardware/device support. ??? Will eventually want to move device stuff to config files. */ |