* Makefile.in (MAIN_INCLUDE_DEPS): Delete.

	(INCLUDE_DEPS,OPS_INCLUDE_DEPS): Delete.
	(sim-if.o): Use SIM_MAIN_DEPS.
	(arch.o,traps.o,devices.o): Ditto.
	(M32RBF_INCLUDE_DEPS): Use CGEN_MAIN_CPU_DEPS.
	(m32r.o,mloop.o,cpu.o,decode.o,sem.o,model.o): Simplify dependencies.
	(m32rx.o,mloopx.o,cpux.o,decodex.o,semx.o,modelx.o): Ditto.
	(stamp-arch): Pass mach=all to cgen-arch.
	* cpu.c,cpu.h,decode.c,model.c,sem-switch.c,sem.c: Regenerate.
	* m32r-sim.h (fr30bf_h_cr_[gs]et_handler): Declare.
	([GS]ET_H_CR): Define.
	(fr30bf_h_psw_[gs]et_handler): Declare.
	([GS]ET_H_PSW): Define.
	(fr30bf_h_accum_[gs]et_handler): Declare.
	([GS]ET_H_ACCUM): Define.
	(fr30xf_h_{cr,psw,accum}_[gs]et_handler): Declare.
	(fr30bf_h_accums_[gs]et_handler): Declare.
	([GS]ET_H_ACCUMS): Define.
	* sim-if.c (sim_open): Model probing code moved to sim-model.c.
	* m32r.c (WANT_CPU): Define as m32rbf.
	(all register access fns): Rename to ..._handler.
	* cpux.c,cpux.h,decodex.c,modelx.c,semx.c: Regenerate.
	* m32rx.c (WANT_CPU): Define as m32rxf.
	(all register access fns): Rename to ..._handler.

1 files changed, 196 insertions, 0 deletions

diff --git a/sim/m32r/cpux.c b/sim/m32r/cpux.c
new file mode 100644
index 0000000..e28c072
--- /dev/null
+++ b/sim/m32r/cpux.c
@@ -0,0 +1,196 @@
+/* Misc. support for CPU family m32rxf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#define WANT_CPU m32rxf
+#define WANT_CPU_M32RXF
+
+#include "sim-main.h"
+
+/* Get the value of h-pc.  */
+
+USI
+m32rxf_h_pc_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_pc);
+}
+
+/* Set a value for h-pc.  */
+
+void
+m32rxf_h_pc_set (SIM_CPU *current_cpu, USI newval)
+{
+  CPU (h_pc) = newval;
+}
+
+/* Get the value of h-gr.  */
+
+SI
+m32rxf_h_gr_get (SIM_CPU *current_cpu, UINT regno)
+{
+  return CPU (h_gr[regno]);
+}
+
+/* Set a value for h-gr.  */
+
+void
+m32rxf_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+  CPU (h_gr[regno]) = newval;
+}
+
+/* Get the value of h-cr.  */
+
+USI
+m32rxf_h_cr_get (SIM_CPU *current_cpu, UINT regno)
+{
+  return GET_H_CR (regno);
+}
+
+/* Set a value for h-cr.  */
+
+void
+m32rxf_h_cr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
+{
+  SET_H_CR (regno, newval);
+}
+
+/* Get the value of h-accum.  */
+
+DI
+m32rxf_h_accum_get (SIM_CPU *current_cpu)
+{
+  return GET_H_ACCUM ();
+}
+
+/* Set a value for h-accum.  */
+
+void
+m32rxf_h_accum_set (SIM_CPU *current_cpu, DI newval)
+{
+  SET_H_ACCUM (newval);
+}
+
+/* Get the value of h-accums.  */
+
+DI
+m32rxf_h_accums_get (SIM_CPU *current_cpu, UINT regno)
+{
+  return GET_H_ACCUMS (regno);
+}
+
+/* Set a value for h-accums.  */
+
+void
+m32rxf_h_accums_set (SIM_CPU *current_cpu, UINT regno, DI newval)
+{
+  SET_H_ACCUMS (regno, newval);
+}
+
+/* Get the value of h-cond.  */
+
+BI
+m32rxf_h_cond_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_cond);
+}
+
+/* Set a value for h-cond.  */
+
+void
+m32rxf_h_cond_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_cond) = newval;
+}
+
+/* Get the value of h-psw.  */
+
+UQI
+m32rxf_h_psw_get (SIM_CPU *current_cpu)
+{
+  return GET_H_PSW ();
+}
+
+/* Set a value for h-psw.  */
+
+void
+m32rxf_h_psw_set (SIM_CPU *current_cpu, UQI newval)
+{
+  SET_H_PSW (newval);
+}
+
+/* Get the value of h-bpsw.  */
+
+UQI
+m32rxf_h_bpsw_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_bpsw);
+}
+
+/* Set a value for h-bpsw.  */
+
+void
+m32rxf_h_bpsw_set (SIM_CPU *current_cpu, UQI newval)
+{
+  CPU (h_bpsw) = newval;
+}
+
+/* Get the value of h-bbpsw.  */
+
+UQI
+m32rxf_h_bbpsw_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_bbpsw);
+}
+
+/* Set a value for h-bbpsw.  */
+
+void
+m32rxf_h_bbpsw_set (SIM_CPU *current_cpu, UQI newval)
+{
+  CPU (h_bbpsw) = newval;
+}
+
+/* Get the value of h-lock.  */
+
+BI
+m32rxf_h_lock_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_lock);
+}
+
+/* Set a value for h-lock.  */
+
+void
+m32rxf_h_lock_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_lock) = newval;
+}
+
+/* Record trace results for INSN.  */
+
+void
+m32rxf_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,
+			    int *indices, TRACE_RECORD *tr)
+{
+}