* arch.c, arch.h, cpuall.h: New files.

	* arch-defs.h: Deleted.
	* mloop.in: Renamed from mainloop.in.
	* sem.c: Renamed from semantics.c.
	* Makefile.in: Update.
	* sem-ops.h: Deleted.
	* mem-ops.h: Deleted.
start-sanitize-cygnus
	Add cgen support for generating files.
end-sanitize-cygnus
	(arch): Renamed from CPU.
	* decode.c: Redone.
	* decode.h: Redone.
	* extract.c: Redone.
	* model.c: Redone.
	* sem-switch.c: Redone.
	* sem.c: Renamed from semantics.c, and redone.
	* m32r-sim.h (PROFILE_COUNT_FILLNOPS): Update.
	(GETTWI,SETTWI,BRANCH_NEW_PC): Define.
	* m32r.c (WANT_CPU,WANT_CPU_M32R): Define.
	(m32r_{fetch,store}_register): New functions.
	(model_mark_{get,set}_h_gr): Prefix with m32r_.
	(m32r_model_mark_{busy,unbusy}_reg): Prefix with m32r_.
	(h_cr_{get,set}): Prefix with m32r_.
	(do_trap): Fetch state from current_cpu, not current_state.
	Call sim_engine_halt instead of engine_halt.
	* sim-if.c (alloc_cpu): New function.
	(free_state): New function.
	(sim_open): Call sim_state_alloc, and malloc space for selected cpu
	type.  Call sim_analyze_program.
	(sim_create_inferior): Handle selected cpu type when setting PC.
start-sanitize-m32rx
	(sim_resume): Handle m32rx.
end-sanitize-m32rx
	(sim_stop_reason): Deleted.
	(print_m32r_misc_cpu): Update.
start-sanitize-m32rx
	(sim_{fetch,store}_register): Handle m32rx.
end-sanitize-m32rx
	(sim_{read,write}): Deleted.
	(sim_engine_illegal_insn): New function.
	* sim-main.h: Don't include arch-defs.h,sim-core.h,sim-events.h.
	Include arch.h,cpuall.h.  Include cpu.h,decode.h if m32r.
start-sanitize-m32rx
	Include cpux.h,decodex.h if m32rx.
end-sanitize-m32rx
	(_sim_cpu): Include member appropriate cpu_data member for the cpu.
	(M32R_MISC_PROFILE): Renamed from M32R_PROFILE.
	(sim_state): Delete members core,events,halt_jmp_buf.
	Change `cpu' member to be a pointer to the cpu's struct, rather than
	record inside the state struct.
	* tconfig.in (WITH_DEVICES): Define here.
	(WITH_FAST,WITH_SEM_SWITCH_{FULL,FAST}): Define for the cpu.

1 files changed, 72 insertions, 0 deletions

diff --git a/sim/m32r/cpuall.h b/sim/m32r/cpuall.h
new file mode 100644
index 0000000..75ee8fa
--- /dev/null
+++ b/sim/m32r/cpuall.h
@@ -0,0 +1,72 @@
+/* Simulator CPU header for m32r.
+
+Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef M32R_CPUALL_H
+#define M32R_CPUALL_H
+
+extern const IMP_PROPERTIES m32r_imp_properties;
+
+extern const MODEL m32r_models[];
+
+#ifndef WANT_CPU
+/* The ARGBUF struct.  */
+struct argbuf {
+  /* These are the baseclass definitions.  */
+  unsigned int length;
+  PCADDR addr;
+  const struct cgen_insn *opcode;
+  /* unsigned long insn; - no longer needed */
+  /* cpu specific data follows */
+};
+#endif
+
+#ifndef WANT_CPU
+/* A cached insn.
+   This is also used in the non-scache case.  In this situation we assume
+   the cache size is 1, and do a few things a little differently.  */
+
+struct scache {
+  IADDR next;
+  union {
+#if ! WITH_SEM_SWITCH_FULL
+    SEMANTIC_FN *sem_fn;
+#endif
+#if ! WITH_SEM_SWITCH_FAST
+#if WITH_SCACHE
+    SEMANTIC_CACHE_FN *sem_fast_fn;
+#else
+    SEMANTIC_FN *sem_fast_fn;
+#endif
+#endif
+#if WITH_SEM_SWITCH_FULL || WITH_SEM_SWITCH_FAST
+#ifdef __GNUC__
+    void *sem_case;
+#else
+    int sem_case;
+#endif
+#endif
+  } semantic;
+  struct argbuf argbuf;
+};
+#endif
+
+#endif /* M32R_CPUALL_H */