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author | Doug Evans <dje@google.com> | 1999-01-06 03:04:25 +0000 |
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committer | Doug Evans <dje@google.com> | 1999-01-06 03:04:25 +0000 |
commit | 368fc7dba80399d03f2310a7288ab1690694fc80 (patch) | |
tree | 932c7541c893896647550927919b13af4dbe26c9 /sim/m32r/cpu.h | |
parent | d9455383f97d305d38e582bc305b0d88a5c6e13e (diff) | |
download | gdb-368fc7dba80399d03f2310a7288ab1690694fc80.zip gdb-368fc7dba80399d03f2310a7288ab1690694fc80.tar.gz gdb-368fc7dba80399d03f2310a7288ab1690694fc80.tar.bz2 |
* Makefile.in (MAIN_INCLUDE_DEPS): Delete.
(INCLUDE_DEPS,OPS_INCLUDE_DEPS): Delete.
(sim-if.o): Use SIM_MAIN_DEPS.
(arch.o,traps.o,devices.o): Ditto.
(M32RBF_INCLUDE_DEPS): Use CGEN_MAIN_CPU_DEPS.
(m32r.o,mloop.o,cpu.o,decode.o,sem.o,model.o): Simplify dependencies.
(m32rx.o,mloopx.o,cpux.o,decodex.o,semx.o,modelx.o): Ditto.
(stamp-arch): Pass mach=all to cgen-arch.
* cpu.c,cpu.h,decode.c,model.c,sem-switch.c,sem.c: Regenerate.
* m32r-sim.h (fr30bf_h_cr_[gs]et_handler): Declare.
([GS]ET_H_CR): Define.
(fr30bf_h_psw_[gs]et_handler): Declare.
([GS]ET_H_PSW): Define.
(fr30bf_h_accum_[gs]et_handler): Declare.
([GS]ET_H_ACCUM): Define.
(fr30xf_h_{cr,psw,accum}_[gs]et_handler): Declare.
(fr30bf_h_accums_[gs]et_handler): Declare.
([GS]ET_H_ACCUMS): Define.
* sim-if.c (sim_open): Model probing code moved to sim-model.c.
* m32r.c (WANT_CPU): Define as m32rbf.
(all register access fns): Rename to ..._handler.
* cpux.c,cpux.h,decodex.c,modelx.c,semx.c: Regenerate.
* m32rx.c (WANT_CPU): Define as m32rxf.
(all register access fns): Rename to ..._handler.
Diffstat (limited to 'sim/m32r/cpu.h')
-rw-r--r-- | sim/m32r/cpu.h | 93 |
1 files changed, 47 insertions, 46 deletions
diff --git a/sim/m32r/cpu.h b/sim/m32r/cpu.h index 7fa50ce..bd07264 100644 --- a/sim/m32r/cpu.h +++ b/sim/m32r/cpu.h @@ -46,26 +46,18 @@ typedef struct { #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x)) /* control registers */ USI h_cr[16]; -#define GET_H_CR(a1) CPU (h_cr)[a1] -#define SET_H_CR(a1, x) (CPU (h_cr)[a1] = (x)) /* accumulator */ DI h_accum; -#define GET_H_ACCUM() CPU (h_accum) -#define SET_H_ACCUM(x) (CPU (h_accum) = (x)) /* start-sanitize-m32rx */ /* accumulators */ DI h_accums[2]; /* end-sanitize-m32rx */ -#define GET_H_ACCUMS(a1) CPU (h_accums)[a1] -#define SET_H_ACCUMS(a1, x) (CPU (h_accums)[a1] = (x)) /* condition bit */ BI h_cond; #define GET_H_COND() CPU (h_cond) #define SET_H_COND(x) (CPU (h_cond) = (x)) /* psw part of psw */ UQI h_psw; -#define GET_H_PSW() CPU (h_psw) -#define SET_H_PSW(x) (CPU (h_psw) = (x)) /* backup psw */ UQI h_bpsw; #define GET_H_BPSW() CPU (h_bpsw) @@ -127,6 +119,9 @@ struct argbuf { union sem semantic; int written; union { + struct { /* empty format for unspecified field list */ + int empty; + } fmt_empty; struct { /* e.g. add $dr,$sr */ SI * i_dr; SI * i_sr; @@ -135,29 +130,29 @@ struct argbuf { unsigned char out_dr; } fmt_add; struct { /* e.g. add3 $dr,$sr,$hash$slo16 */ + INT f_simm16; SI * i_sr; - HI f_simm16; SI * i_dr; unsigned char in_sr; unsigned char out_dr; } fmt_add3; struct { /* e.g. and3 $dr,$sr,$uimm16 */ + UINT f_uimm16; SI * i_sr; - USI f_uimm16; SI * i_dr; unsigned char in_sr; unsigned char out_dr; } fmt_and3; struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */ + UINT f_uimm16; SI * i_sr; - UHI f_uimm16; SI * i_dr; unsigned char in_sr; unsigned char out_dr; } fmt_or3; struct { /* e.g. addi $dr,$simm8 */ + INT f_simm8; SI * i_dr; - SI f_simm8; unsigned char in_dr; unsigned char out_dr; } fmt_addi; @@ -169,8 +164,8 @@ struct argbuf { unsigned char out_dr; } fmt_addv; struct { /* e.g. addv3 $dr,$sr,$simm16 */ + INT f_simm16; SI * i_sr; - SI f_simm16; SI * i_dr; unsigned char in_sr; unsigned char out_dr; @@ -189,8 +184,8 @@ struct argbuf { unsigned char in_src2; } fmt_cmp; struct { /* e.g. cmpi $src2,$simm16 */ + INT f_simm16; SI * i_src2; - SI f_simm16; unsigned char in_src2; } fmt_cmpi; struct { /* e.g. div $dr,$sr */ @@ -207,8 +202,8 @@ struct argbuf { unsigned char out_dr; } fmt_ld; struct { /* e.g. ld $dr,@($slo16,$sr) */ + INT f_simm16; SI * i_sr; - HI f_simm16; SI * i_dr; unsigned char in_sr; unsigned char out_dr; @@ -220,8 +215,8 @@ struct argbuf { unsigned char out_dr; } fmt_ldb; struct { /* e.g. ldb $dr,@($slo16,$sr) */ + INT f_simm16; SI * i_sr; - HI f_simm16; SI * i_dr; unsigned char in_sr; unsigned char out_dr; @@ -233,8 +228,8 @@ struct argbuf { unsigned char out_dr; } fmt_ldh; struct { /* e.g. ldh $dr,@($slo16,$sr) */ + INT f_simm16; SI * i_sr; - HI f_simm16; SI * i_dr; unsigned char in_sr; unsigned char out_dr; @@ -247,17 +242,17 @@ struct argbuf { unsigned char out_sr; } fmt_ld_plus; struct { /* e.g. ld24 $dr,$uimm24 */ - ADDR f_uimm24; + ADDR i_uimm24; SI * i_dr; unsigned char out_dr; } fmt_ld24; struct { /* e.g. ldi8 $dr,$simm8 */ - SI f_simm8; + INT f_simm8; SI * i_dr; unsigned char out_dr; } fmt_ldi8; struct { /* e.g. ldi16 $dr,$hash$slo16 */ - HI f_simm16; + INT f_simm16; SI * i_dr; unsigned char out_dr; } fmt_ldi16; @@ -299,8 +294,8 @@ struct argbuf { unsigned char in_src1; } fmt_mvtachi; struct { /* e.g. mvtc $sr,$dcr */ - SI * i_sr; UINT f_r1; + SI * i_sr; unsigned char in_sr; } fmt_mvtc; struct { /* e.g. nop */ @@ -310,20 +305,20 @@ struct argbuf { int empty; } fmt_rac; struct { /* e.g. seth $dr,$hash$hi16 */ - UHI f_hi16; + UINT f_hi16; SI * i_dr; unsigned char out_dr; } fmt_seth; struct { /* e.g. sll3 $dr,$sr,$simm16 */ + INT f_simm16; SI * i_sr; - SI f_simm16; SI * i_dr; unsigned char in_sr; unsigned char out_dr; } fmt_sll3; struct { /* e.g. slli $dr,$uimm5 */ + UINT f_uimm5; SI * i_dr; - USI f_uimm5; unsigned char in_dr; unsigned char out_dr; } fmt_slli; @@ -334,8 +329,8 @@ struct argbuf { unsigned char in_src1; } fmt_st; struct { /* e.g. st $src1,@($slo16,$src2) */ + INT f_simm16; SI * i_src2; - HI f_simm16; SI * i_src1; unsigned char in_src2; unsigned char in_src1; @@ -347,8 +342,8 @@ struct argbuf { unsigned char in_src1; } fmt_stb; struct { /* e.g. stb $src1,@($slo16,$src2) */ + INT f_simm16; SI * i_src2; - HI f_simm16; SI * i_src1; unsigned char in_src2; unsigned char in_src1; @@ -360,8 +355,8 @@ struct argbuf { unsigned char in_src1; } fmt_sth; struct { /* e.g. sth $src1,@($slo16,$src2) */ + INT f_simm16; SI * i_src2; - HI f_simm16; SI * i_src1; unsigned char in_src2; unsigned char in_src1; @@ -383,36 +378,36 @@ struct argbuf { struct { union { struct { /* e.g. bc.s $disp8 */ - IADDR f_disp8; + IADDR i_disp8; } fmt_bc8; struct { /* e.g. bc.l $disp24 */ - IADDR f_disp24; + IADDR i_disp24; } fmt_bc24; struct { /* e.g. beq $src1,$src2,$disp16 */ SI * i_src1; SI * i_src2; - IADDR f_disp16; + IADDR i_disp16; unsigned char in_src1; unsigned char in_src2; } fmt_beq; struct { /* e.g. beqz $src2,$disp16 */ SI * i_src2; - IADDR f_disp16; + IADDR i_disp16; unsigned char in_src2; } fmt_beqz; struct { /* e.g. bl.s $disp8 */ - IADDR f_disp8; + IADDR i_disp8; unsigned char out_h_gr_14; } fmt_bl8; struct { /* e.g. bl.l $disp24 */ - IADDR f_disp24; + IADDR i_disp24; unsigned char out_h_gr_14; } fmt_bl24; struct { /* e.g. bra.s $disp8 */ - IADDR f_disp8; + IADDR i_disp8; } fmt_bra8; struct { /* e.g. bra.l $disp24 */ - IADDR f_disp24; + IADDR i_disp24; } fmt_bra24; struct { /* e.g. jl $sr */ SI * i_sr; @@ -427,14 +422,14 @@ struct argbuf { int empty; } fmt_rte; struct { /* e.g. trap $uimm4 */ - USI f_uimm4; + UINT f_uimm4; } fmt_trap; } fields; -#if WITH_SCACHE_PBB_M32RBF +#if WITH_SCACHE_PBB SEM_PC addr_cache; #endif } cti; -#if WITH_SCACHE_PBB_M32RBF +#if WITH_SCACHE_PBB /* Writeback handler. */ struct { /* Pointer to argbuf entry for insn whose results need writing back. */ @@ -473,6 +468,12 @@ struct scache { /* Macros to simplify extraction, reading and semantic code. These define and assign the local vars that contain the insn's fields. */ +#define EXTRACT_FMT_EMPTY_VARS \ + /* Instruction fields. */ \ + unsigned int length; +#define EXTRACT_FMT_EMPTY_CODE \ + length = 0; \ + #define EXTRACT_FMT_ADD_VARS \ /* Instruction fields. */ \ UINT f_op1; \ @@ -595,7 +596,7 @@ struct scache { /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ - INT f_disp8; \ + SI f_disp8; \ unsigned int length; #define EXTRACT_FMT_BC8_CODE \ length = 2; \ @@ -607,7 +608,7 @@ struct scache { /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ - INT f_disp24; \ + SI f_disp24; \ unsigned int length; #define EXTRACT_FMT_BC24_CODE \ length = 4; \ @@ -621,7 +622,7 @@ struct scache { UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ - INT f_disp16; \ + SI f_disp16; \ unsigned int length; #define EXTRACT_FMT_BEQ_CODE \ length = 4; \ @@ -637,7 +638,7 @@ struct scache { UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ - INT f_disp16; \ + SI f_disp16; \ unsigned int length; #define EXTRACT_FMT_BEQZ_CODE \ length = 4; \ @@ -651,7 +652,7 @@ struct scache { /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ - INT f_disp8; \ + SI f_disp8; \ unsigned int length; #define EXTRACT_FMT_BL8_CODE \ length = 2; \ @@ -663,7 +664,7 @@ struct scache { /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ - INT f_disp24; \ + SI f_disp24; \ unsigned int length; #define EXTRACT_FMT_BL24_CODE \ length = 4; \ @@ -675,7 +676,7 @@ struct scache { /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ - INT f_disp8; \ + SI f_disp8; \ unsigned int length; #define EXTRACT_FMT_BRA8_CODE \ length = 2; \ @@ -687,7 +688,7 @@ struct scache { /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ - INT f_disp24; \ + SI f_disp24; \ unsigned int length; #define EXTRACT_FMT_BRA24_CODE \ length = 4; \ |