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| author | Andrew Burgess <andrew.burgess@embecosm.com> | 2020-11-11 11:55:08 +0000 |
|---|---|---|
| committer | Andrew Burgess <andrew.burgess@embecosm.com> | 2020-11-11 11:55:08 +0000 |
| commit | 550820e16d0a1f44ee63086b1a2d931e04839ffa (patch) | |
| tree | 8cab9812e2a3868d92c1b5cce445ee0dc8299344 /sim/m32c/m32c.opc | |
| parent | 81fdd7acec68476bc23dd1ed4b2c6288aebe4343 (diff) | |
| download | gdb-550820e16d0a1f44ee63086b1a2d931e04839ffa.zip gdb-550820e16d0a1f44ee63086b1a2d931e04839ffa.tar.gz gdb-550820e16d0a1f44ee63086b1a2d931e04839ffa.tar.bz2 | |
gdb/riscv: add ability to decode dwarf CSR numbers
Extends riscv_dwarf_reg_to_regnum to add the ability to convert the
DWARF register numbers for CSRs into GDB's internal numbers.
gdb/ChangeLog:
* riscv-tdep.c (riscv_dwarf_reg_to_regnum): Decode DWARF CSR
numbers.
* riscv-tdep.h (RISCV_DWARF_FIRST_CSR, RISCV_DWARF_LAST_CSR): New
enum values.
Diffstat (limited to 'sim/m32c/m32c.opc')
0 files changed, 0 insertions, 0 deletions