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author | Andrew Cagney <cagney@redhat.com> | 1997-05-16 03:27:40 +0000 |
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committer | Andrew Cagney <cagney@redhat.com> | 1997-05-16 03:27:40 +0000 |
commit | 37a684b84d5c722848ebdc7203052d65c6b35e30 (patch) | |
tree | 3d7fa5b15efab746e9b8cc87449fa8664b6ed359 /sim/igen/gen-semantics.c | |
parent | 77bd8dfa1f3678ea3c3d05f40de29a36802d21f5 (diff) | |
download | gdb-37a684b84d5c722848ebdc7203052d65c6b35e30.zip gdb-37a684b84d5c722848ebdc7203052d65c6b35e30.tar.gz gdb-37a684b84d5c722848ebdc7203052d65c6b35e30.tar.bz2 |
o Make tic80 insn file more `cache ready'
o Have igen always zero r0 instead of constantly checking if
the designated register is r0.
Diffstat (limited to 'sim/igen/gen-semantics.c')
-rw-r--r-- | sim/igen/gen-semantics.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/sim/igen/gen-semantics.c b/sim/igen/gen-semantics.c index 0ffcf78..35b247f 100644 --- a/sim/igen/gen-semantics.c +++ b/sim/igen/gen-semantics.c @@ -173,6 +173,15 @@ print_semantic_body(lf *file, /* FIXME - need to log a conditional failure */ } + /* Architecture expects r0 to be zero. Instead of having to check + every read to see if it is refering to r0 just zap the r0 + register */ + if ((code & generate_with_semantic_delayed_branch)) + { + lf_printf (file, "\n"); + lf_printf (file, "GPR(0) = 0;\n"); + } + /* generate the code (or at least something */ lf_printf(file, "\n"); lf_printf(file, "/* semantics: */\n"); |