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| author | Andrew Cagney <cagney@redhat.com> | 1997-05-16 03:27:40 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 1997-05-16 03:27:40 +0000 |
| commit | 37a684b84d5c722848ebdc7203052d65c6b35e30 (patch) | |
| tree | 3d7fa5b15efab746e9b8cc87449fa8664b6ed359 /sim/igen/ChangeLog | |
| parent | 77bd8dfa1f3678ea3c3d05f40de29a36802d21f5 (diff) | |
| download | gdb-37a684b84d5c722848ebdc7203052d65c6b35e30.zip gdb-37a684b84d5c722848ebdc7203052d65c6b35e30.tar.gz gdb-37a684b84d5c722848ebdc7203052d65c6b35e30.tar.bz2 | |
o Make tic80 insn file more `cache ready'
o Have igen always zero r0 instead of constantly checking if
the designated register is r0.
Diffstat (limited to 'sim/igen/ChangeLog')
| -rw-r--r-- | sim/igen/ChangeLog | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/sim/igen/ChangeLog b/sim/igen/ChangeLog index df837dc..a9f790a 100644 --- a/sim/igen/ChangeLog +++ b/sim/igen/ChangeLog @@ -1,3 +1,10 @@ +Fri May 16 11:48:30 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * gen-semantics.c (print_semantic_body): Add code to clear r0. + + * igen.c (main): Add new option zero-r0, which adds code to clear + GPR(0) each cycle. + Wed May 7 12:31:30 1997 Andrew Cagney <cagney@b1.cygnus.com> * igen.c (print_itrace): Fix so line-nr is passed to trace |