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authorStan Shebs <shebs@codesourcery.com>1999-04-26 18:34:20 +0000
committerStan Shebs <shebs@codesourcery.com>1999-04-26 18:34:20 +0000
commit7a292a7adf506b866905b06b3024c0fd411c4583 (patch)
tree5b208bb48269b8a82d5c3a5f19c87b45a62a22f4 /sim/i960
parent1996fae84682e8ddd146215dd2959ad1ec924c09 (diff)
downloadgdb-7a292a7adf506b866905b06b3024c0fd411c4583.zip
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import gdb-19990422 snapshot
Diffstat (limited to 'sim/i960')
-rw-r--r--sim/i960/ChangeLog48
-rw-r--r--sim/i960/README11
-rw-r--r--sim/i960/TODO73
-rw-r--r--sim/i960/arch.c126
-rw-r--r--sim/i960/arch.h8
-rw-r--r--sim/i960/cpu.c1
-rw-r--r--sim/i960/cpu.h264
-rw-r--r--sim/i960/decode.c3474
-rw-r--r--sim/i960/decode.h14
-rw-r--r--sim/i960/devices.c13
-rw-r--r--sim/i960/i960-desc.c1089
-rw-r--r--sim/i960/i960-desc.h101
-rw-r--r--sim/i960/i960-opc.h18
-rw-r--r--sim/i960/i960-sim.h5
-rw-r--r--sim/i960/i960.c64
-rw-r--r--sim/i960/model.c340
-rw-r--r--sim/i960/sem-switch.c678
-rw-r--r--sim/i960/sem.c686
-rw-r--r--sim/i960/sim-if.c10
19 files changed, 3889 insertions, 3134 deletions
diff --git a/sim/i960/ChangeLog b/sim/i960/ChangeLog
index 5a87da5..837233c 100644
--- a/sim/i960/ChangeLog
+++ b/sim/i960/ChangeLog
@@ -1,3 +1,51 @@
+Fri Apr 16 16:50:31 1999 Doug Evans <devans@charmed.cygnus.com>
+
+ * devices.c (device_io_read_buffer): New arg `sd'.
+ (device_io_write_buffer): New arg `sd'.
+ (device_error): Give proper arg spec.
+
+1999-04-14 Doug Evans <devans@casey.cygnus.com>
+
+ * i960-desc.c,i960-desc.h: Rebuild.
+
+Sun Apr 11 00:25:17 1999 Jim Wilson <wilson@cygnus.com>
+
+ * TODO: Document more toolchain problems.
+ * cpu.h, decode.c, model.c, sem-switch.c, sem.c: Rebuild.
+
+1999-04-10 Doug Evans <devans@casey.cygnus.com>
+
+ * cpu.h,decode.c,sem-switch.c,sem.c: Rebuild.
+
+Fri Apr 9 19:30:05 1999 Jim Wilson <wilson@cygnus.com>
+
+ * README, TODO: Clean up and update.
+ * sim-if.c: s/m32r/i960. s/sparc32/i960.
+ * decode.c, decode.h, i960-desc.c, i960-desc.h, i960-opc.h, model.c,
+ sem-switch.c, sem.c: Rebuild.
+
+1999-03-27 Doug Evans <devans@casey.cygnus.com>
+
+ * decode.c: Rebuild.
+
+1999-03-22 Doug Evans <devans@casey.cygnus.com>
+
+ * arch.c,arch.h,model.c,i960-desc.c,i960-desc.h,i960-opc.h: Rebuild.
+ * i960-sim.h (a_i960_h_gr_get,a_i960_h_gr_set): Declare.
+ (a_i960_h_pc_get,a_i960_h_pc_set): Declare.
+ * i960.c (a_i960_h_gr_get,a_i960_h_gr_set): New functions.
+ (a_i960_h_pc_get,a_i960_h_pc_set): Ditto.
+ * sim-if.c (sim_open): Update call to i960_cgen_cpu_open.
+
+1999-03-11 Doug Evans <devans@casey.cygnus.com>
+
+ * arch.c,arch.h,cpu.c,i960-desc.c,i960-desc.h: Rebuild.
+ * sim-if.c (sim_open): Update call to i960_cgen_cpu_open.
+
+1999-02-25 Doug Evans <devans@casey.cygnus.com>
+
+ * i960-desc.c,i960-desc.h: Rebuild.
+
1999-02-09 Doug Evans <devans@casey.cygnus.com>
* Makefile.in (I960_OBJS): Add i960-desc.o.
diff --git a/sim/i960/README b/sim/i960/README
index f337558..6d38a40 100644
--- a/sim/i960/README
+++ b/sim/i960/README
@@ -1,9 +1,18 @@
This is the i960 simulator directory.
-It is still work-in-progress. The current sources are reasonably
+It is still a work in progress. The current sources are reasonably
well tested and lots of features are in. However, there's lots
more yet to come.
+---
+
+The simulator only supports the i960KA currently. Not all instructions
+are supported yet, only those instructions needed by the gcc/g++ testsuites
+have been added so far. There is no profiling support as yet. There is
+no pipeline or timing support as yet.
+
+---
+
There are lots of machine generated files in the source directory!
They are only generated if you configure with --enable-cgen-maint,
similar in behaviour to Makefile.in, configure under automake/autoconf.
diff --git a/sim/i960/TODO b/sim/i960/TODO
index 263daac..5e156b1 100644
--- a/sim/i960/TODO
+++ b/sim/i960/TODO
@@ -1,9 +1,64 @@
-- header file dependencies revisit
-- hooks cleanup
-- testsuites
-- FIXME's
-- memory accesses still test if profiling is on even in fast mode
-- fill nop counting done even in fast mode
-- have semantic code use G/SET_H_FOO if not default [incl fun-access]
-- have G/SET_H_FOO macros call function if fun-access
-- --> can always use G/S_H_FOO macros
+See ??? comments here and in cgen, and in libgloss/i960.
+
+Simulator:
+
+Update sim/i960 directory from sim/m32r directory. sim/i960 dir was created
+by copying the sim/m32r in September 1998, and is missing all sim/m32r updates
+since then.
+
+Review, clean up, finish, etc simulator files that are not cgen generated.
+This includes devices.c, i960-sim.h, mloop.in, sim-if.c, sim-main.h,
+tconfig.in, and traps.c.
+
+Some functions do not show up in trace output. This occasionally happens
+for main.
+
+Gdb core dumps if compile without -mka. Apparently a problem with recognizing
+"core" machine type.
+
+Get profiling working.
+
+Add pipelining, execution unit, timing, etc info.
+
+Add support for other models, besides KA.
+
+Add support for newer architectures, e.g. v1.1 instructions.
+
+Compiler:
+
+Running gcc gives nm warning from collect about missing a.out file.
+The output file is b.out, not a.out. Collect is probably looking for
+the wrong file name.
+
+Use of -mca gives lots of linker warnings for ka/ca architecture conflicts,
+but the two architectures are compatible.
+
+Need 96 bit long double support in fp-bit.c, otherwise any testcase using
+long double arithmetic hits an abort and runtime.
+
+Compiler takes far too much time to compile PlumHall testcases at high
+optimization levels.
+
+r2 seems to be an available call-clobbered registers, since it isn't used
+until a call occurs, and is dead when the call returns.
+
+BSP:
+
+Libgloss does not check for syscall error returns, which means errno never
+gets set.
+
+Libgloss does not use the syscall.h file.
+
+Binutils:
+
+Objdump -d fails on 64-bit host, specifically irix6.
+
+Gdb:
+
+Gdb sometimes prints messages about trace/breakpoint trap when hitting a
+breakpoint.
+
+Frame, up, down and related commands don't work.
+
+Gdb fails when next'ing over a leaf function compiled with -mleaf-procedure.
+Gdb fails when step'ing over a return from such a leaf function.
diff --git a/sim/i960/arch.c b/sim/i960/arch.c
index 5d3ab84..74833b0 100644
--- a/sim/i960/arch.c
+++ b/sim/i960/arch.c
@@ -36,129 +36,3 @@ const MACH *sim_machs[] =
0
};
-/* Get the value of h-pc. */
-
-USI
-a_i960_h_pc_get (SIM_CPU *current_cpu)
-{
- switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
- {
-#ifdef HAVE_CPU_I960BASE
- case bfd_mach_i960_ka_sa :
- return i960base_h_pc_get (current_cpu);
-#endif
-#ifdef HAVE_CPU_I960BASE
- case bfd_mach_i960_ca :
- return i960base_h_pc_get (current_cpu);
-#endif
- default :
- abort ();
- }
-}
-
-/* Set a value for h-pc. */
-
-void
-a_i960_h_pc_set (SIM_CPU *current_cpu, USI newval)
-{
- switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
- {
-#ifdef HAVE_CPU_I960BASE
- case bfd_mach_i960_ka_sa :
- i960base_h_pc_set (current_cpu, newval);
- break;
-#endif
-#ifdef HAVE_CPU_I960BASE
- case bfd_mach_i960_ca :
- i960base_h_pc_set (current_cpu, newval);
- break;
-#endif
- default :
- abort ();
- }
-}
-
-/* Get the value of h-gr. */
-
-SI
-a_i960_h_gr_get (SIM_CPU *current_cpu, UINT regno)
-{
- switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
- {
-#ifdef HAVE_CPU_I960BASE
- case bfd_mach_i960_ka_sa :
- return i960base_h_gr_get (current_cpu, regno);
-#endif
-#ifdef HAVE_CPU_I960BASE
- case bfd_mach_i960_ca :
- return i960base_h_gr_get (current_cpu, regno);
-#endif
- default :
- abort ();
- }
-}
-
-/* Set a value for h-gr. */
-
-void
-a_i960_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
-{
- switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
- {
-#ifdef HAVE_CPU_I960BASE
- case bfd_mach_i960_ka_sa :
- i960base_h_gr_set (current_cpu, regno, newval);
- break;
-#endif
-#ifdef HAVE_CPU_I960BASE
- case bfd_mach_i960_ca :
- i960base_h_gr_set (current_cpu, regno, newval);
- break;
-#endif
- default :
- abort ();
- }
-}
-
-/* Get the value of h-cc. */
-
-SI
-a_i960_h_cc_get (SIM_CPU *current_cpu)
-{
- switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
- {
-#ifdef HAVE_CPU_I960BASE
- case bfd_mach_i960_ka_sa :
- return i960base_h_cc_get (current_cpu);
-#endif
-#ifdef HAVE_CPU_I960BASE
- case bfd_mach_i960_ca :
- return i960base_h_cc_get (current_cpu);
-#endif
- default :
- abort ();
- }
-}
-
-/* Set a value for h-cc. */
-
-void
-a_i960_h_cc_set (SIM_CPU *current_cpu, SI newval)
-{
- switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
- {
-#ifdef HAVE_CPU_I960BASE
- case bfd_mach_i960_ka_sa :
- i960base_h_cc_set (current_cpu, newval);
- break;
-#endif
-#ifdef HAVE_CPU_I960BASE
- case bfd_mach_i960_ca :
- i960base_h_cc_set (current_cpu, newval);
- break;
-#endif
- default :
- abort ();
- }
-}
-
diff --git a/sim/i960/arch.h b/sim/i960/arch.h
index 26dcfd6..fdfbf35 100644
--- a/sim/i960/arch.h
+++ b/sim/i960/arch.h
@@ -27,14 +27,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#define TARGET_BIG_ENDIAN 1
-/* Cover fns for register access. */
-USI a_i960_h_pc_get (SIM_CPU *);
-void a_i960_h_pc_set (SIM_CPU *, USI);
-SI a_i960_h_gr_get (SIM_CPU *, UINT);
-void a_i960_h_gr_set (SIM_CPU *, UINT, SI);
-SI a_i960_h_cc_get (SIM_CPU *);
-void a_i960_h_cc_set (SIM_CPU *, SI);
-
/* Enum declaration for model types. */
typedef enum model_type {
MODEL_I960KA, MODEL_I960CA, MODEL_MAX
diff --git a/sim/i960/cpu.c b/sim/i960/cpu.c
index aec6a06..c41b643 100644
--- a/sim/i960/cpu.c
+++ b/sim/i960/cpu.c
@@ -26,6 +26,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#define WANT_CPU_I960BASE
#include "sim-main.h"
+#include "cgen-ops.h"
/* Get the value of h-pc. */
diff --git a/sim/i960/cpu.h b/sim/i960/cpu.h
index 42532b0..9887906 100644
--- a/sim/i960/cpu.h
+++ b/sim/i960/cpu.h
@@ -154,6 +154,34 @@ union sem_fields {
SI * i_dst;
unsigned char out_dst;
} fmt_not3;
+ struct { /* e.g. shlo $src1, $src2, $dst */
+ SI * i_src1;
+ SI * i_src2;
+ SI * i_dst;
+ unsigned char in_src1;
+ unsigned char in_src2;
+ unsigned char out_dst;
+ } fmt_shlo;
+ struct { /* e.g. shlo $lit1, $src2, $dst */
+ UINT f_src1;
+ SI * i_src2;
+ SI * i_dst;
+ unsigned char in_src2;
+ unsigned char out_dst;
+ } fmt_shlo1;
+ struct { /* e.g. shlo $src1, $lit2, $dst */
+ UINT f_src2;
+ SI * i_src1;
+ SI * i_dst;
+ unsigned char in_src1;
+ unsigned char out_dst;
+ } fmt_shlo2;
+ struct { /* e.g. shlo $lit1, $lit2, $dst */
+ UINT f_src1;
+ UINT f_src2;
+ SI * i_dst;
+ unsigned char out_dst;
+ } fmt_shlo3;
struct { /* e.g. emul $src1, $src2, $dst */
UINT f_srcdst;
SI * i_src1;
@@ -162,7 +190,7 @@ union sem_fields {
unsigned char in_src1;
unsigned char in_src2;
unsigned char out_dst;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+ unsigned char out_h_gr_add__VM_index_of_dst_1;
} fmt_emul;
struct { /* e.g. emul $lit1, $src2, $dst */
UINT f_srcdst;
@@ -171,7 +199,7 @@ union sem_fields {
SI * i_dst;
unsigned char in_src2;
unsigned char out_dst;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+ unsigned char out_h_gr_add__VM_index_of_dst_1;
} fmt_emul1;
struct { /* e.g. emul $src1, $lit2, $dst */
UINT f_srcdst;
@@ -180,7 +208,7 @@ union sem_fields {
SI * i_dst;
unsigned char in_src1;
unsigned char out_dst;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+ unsigned char out_h_gr_add__VM_index_of_dst_1;
} fmt_emul2;
struct { /* e.g. emul $lit1, $lit2, $dst */
UINT f_srcdst;
@@ -188,67 +216,67 @@ union sem_fields {
UINT f_src2;
SI * i_dst;
unsigned char out_dst;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+ unsigned char out_h_gr_add__VM_index_of_dst_1;
} fmt_emul3;
struct { /* e.g. movl $src1, $dst */
UINT f_src1;
UINT f_srcdst;
SI * i_src1;
SI * i_dst;
- unsigned char in_h_gr_add__VM_index_of_src1_const__WI_1;
+ unsigned char in_h_gr_add__VM_index_of_src1_1;
unsigned char in_src1;
unsigned char out_dst;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+ unsigned char out_h_gr_add__VM_index_of_dst_1;
} fmt_movl;
struct { /* e.g. movl $lit1, $dst */
UINT f_srcdst;
UINT f_src1;
SI * i_dst;
unsigned char out_dst;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+ unsigned char out_h_gr_add__VM_index_of_dst_1;
} fmt_movl1;
struct { /* e.g. movt $src1, $dst */
UINT f_src1;
UINT f_srcdst;
SI * i_src1;
SI * i_dst;
- unsigned char in_h_gr_add__VM_index_of_src1_const__WI_1;
- unsigned char in_h_gr_add__VM_index_of_src1_const__WI_2;
+ unsigned char in_h_gr_add__VM_index_of_src1_1;
+ unsigned char in_h_gr_add__VM_index_of_src1_2;
unsigned char in_src1;
unsigned char out_dst;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
+ unsigned char out_h_gr_add__VM_index_of_dst_1;
+ unsigned char out_h_gr_add__VM_index_of_dst_2;
} fmt_movt;
struct { /* e.g. movt $lit1, $dst */
UINT f_srcdst;
UINT f_src1;
SI * i_dst;
unsigned char out_dst;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
+ unsigned char out_h_gr_add__VM_index_of_dst_1;
+ unsigned char out_h_gr_add__VM_index_of_dst_2;
} fmt_movt1;
struct { /* e.g. movq $src1, $dst */
UINT f_src1;
UINT f_srcdst;
SI * i_src1;
SI * i_dst;
- unsigned char in_h_gr_add__VM_index_of_src1_const__WI_1;
- unsigned char in_h_gr_add__VM_index_of_src1_const__WI_2;
- unsigned char in_h_gr_add__VM_index_of_src1_const__WI_3;
+ unsigned char in_h_gr_add__VM_index_of_src1_1;
+ unsigned char in_h_gr_add__VM_index_of_src1_2;
+ unsigned char in_h_gr_add__VM_index_of_src1_3;
unsigned char in_src1;
unsigned char out_dst;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_3;
+ unsigned char out_h_gr_add__VM_index_of_dst_1;
+ unsigned char out_h_gr_add__VM_index_of_dst_2;
+ unsigned char out_h_gr_add__VM_index_of_dst_3;
} fmt_movq;
struct { /* e.g. movq $lit1, $dst */
UINT f_srcdst;
UINT f_src1;
SI * i_dst;
unsigned char out_dst;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_3;
+ unsigned char out_h_gr_add__VM_index_of_dst_1;
+ unsigned char out_h_gr_add__VM_index_of_dst_2;
+ unsigned char out_h_gr_add__VM_index_of_dst_3;
} fmt_movq1;
struct { /* e.g. modpc $src1, $src2, $dst */
SI * i_src2;
@@ -603,7 +631,7 @@ union sem_fields {
UINT f_offset;
SI * i_dst;
unsigned char out_dst;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+ unsigned char out_h_gr_add__VM_index_of_dst_1;
} fmt_ldl_offset;
struct { /* e.g. ldl $offset($abase), $dst */
UINT f_srcdst;
@@ -612,7 +640,7 @@ union sem_fields {
SI * i_dst;
unsigned char in_abase;
unsigned char out_dst;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+ unsigned char out_h_gr_add__VM_index_of_dst_1;
} fmt_ldl_indirect_offset;
struct { /* e.g. ldl ($abase), $dst */
UINT f_srcdst;
@@ -620,7 +648,7 @@ union sem_fields {
SI * i_dst;
unsigned char in_abase;
unsigned char out_dst;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+ unsigned char out_h_gr_add__VM_index_of_dst_1;
} fmt_ldl_indirect;
struct { /* e.g. ldl ($abase)[$index*S$scale], $dst */
UINT f_srcdst;
@@ -631,14 +659,14 @@ union sem_fields {
unsigned char in_abase;
unsigned char in_index;
unsigned char out_dst;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+ unsigned char out_h_gr_add__VM_index_of_dst_1;
} fmt_ldl_indirect_index;
struct { /* e.g. ldl $optdisp, $dst */
UINT f_srcdst;
UINT f_optdisp;
SI * i_dst;
unsigned char out_dst;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+ unsigned char out_h_gr_add__VM_index_of_dst_1;
} fmt_ldl_disp;
struct { /* e.g. ldl $optdisp($abase), $dst */
UINT f_srcdst;
@@ -647,7 +675,7 @@ union sem_fields {
SI * i_dst;
unsigned char in_abase;
unsigned char out_dst;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+ unsigned char out_h_gr_add__VM_index_of_dst_1;
} fmt_ldl_indirect_disp;
struct { /* e.g. ldl $optdisp[$index*S$scale], $dst */
UINT f_srcdst;
@@ -657,7 +685,7 @@ union sem_fields {
SI * i_dst;
unsigned char in_index;
unsigned char out_dst;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+ unsigned char out_h_gr_add__VM_index_of_dst_1;
} fmt_ldl_index_disp;
struct { /* e.g. ldl $optdisp($abase)[$index*S$scale], $dst */
UINT f_srcdst;
@@ -669,15 +697,15 @@ union sem_fields {
unsigned char in_abase;
unsigned char in_index;
unsigned char out_dst;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
+ unsigned char out_h_gr_add__VM_index_of_dst_1;
} fmt_ldl_indirect_index_disp;
struct { /* e.g. ldt $offset, $dst */
UINT f_srcdst;
UINT f_offset;
SI * i_dst;
unsigned char out_dst;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
+ unsigned char out_h_gr_add__VM_index_of_dst_1;
+ unsigned char out_h_gr_add__VM_index_of_dst_2;
} fmt_ldt_offset;
struct { /* e.g. ldt $offset($abase), $dst */
UINT f_srcdst;
@@ -686,8 +714,8 @@ union sem_fields {
SI * i_dst;
unsigned char in_abase;
unsigned char out_dst;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
+ unsigned char out_h_gr_add__VM_index_of_dst_1;
+ unsigned char out_h_gr_add__VM_index_of_dst_2;
} fmt_ldt_indirect_offset;
struct { /* e.g. ldt ($abase), $dst */
UINT f_srcdst;
@@ -695,8 +723,8 @@ union sem_fields {
SI * i_dst;
unsigned char in_abase;
unsigned char out_dst;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
+ unsigned char out_h_gr_add__VM_index_of_dst_1;
+ unsigned char out_h_gr_add__VM_index_of_dst_2;
} fmt_ldt_indirect;
struct { /* e.g. ldt ($abase)[$index*S$scale], $dst */
UINT f_srcdst;
@@ -707,16 +735,16 @@ union sem_fields {
unsigned char in_abase;
unsigned char in_index;
unsigned char out_dst;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
+ unsigned char out_h_gr_add__VM_index_of_dst_1;
+ unsigned char out_h_gr_add__VM_index_of_dst_2;
} fmt_ldt_indirect_index;
struct { /* e.g. ldt $optdisp, $dst */
UINT f_srcdst;
UINT f_optdisp;
SI * i_dst;
unsigned char out_dst;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
+ unsigned char out_h_gr_add__VM_index_of_dst_1;
+ unsigned char out_h_gr_add__VM_index_of_dst_2;
} fmt_ldt_disp;
struct { /* e.g. ldt $optdisp($abase), $dst */
UINT f_srcdst;
@@ -725,8 +753,8 @@ union sem_fields {
SI * i_dst;
unsigned char in_abase;
unsigned char out_dst;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
+ unsigned char out_h_gr_add__VM_index_of_dst_1;
+ unsigned char out_h_gr_add__VM_index_of_dst_2;
} fmt_ldt_indirect_disp;
struct { /* e.g. ldt $optdisp[$index*S$scale], $dst */
UINT f_srcdst;
@@ -736,8 +764,8 @@ union sem_fields {
SI * i_dst;
unsigned char in_index;
unsigned char out_dst;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
+ unsigned char out_h_gr_add__VM_index_of_dst_1;
+ unsigned char out_h_gr_add__VM_index_of_dst_2;
} fmt_ldt_index_disp;
struct { /* e.g. ldt $optdisp($abase)[$index*S$scale], $dst */
UINT f_srcdst;
@@ -749,17 +777,17 @@ union sem_fields {
unsigned char in_abase;
unsigned char in_index;
unsigned char out_dst;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
+ unsigned char out_h_gr_add__VM_index_of_dst_1;
+ unsigned char out_h_gr_add__VM_index_of_dst_2;
} fmt_ldt_indirect_index_disp;
struct { /* e.g. ldq $offset, $dst */
UINT f_srcdst;
UINT f_offset;
SI * i_dst;
unsigned char out_dst;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_3;
+ unsigned char out_h_gr_add__VM_index_of_dst_1;
+ unsigned char out_h_gr_add__VM_index_of_dst_2;
+ unsigned char out_h_gr_add__VM_index_of_dst_3;
} fmt_ldq_offset;
struct { /* e.g. ldq $offset($abase), $dst */
UINT f_srcdst;
@@ -768,9 +796,9 @@ union sem_fields {
SI * i_dst;
unsigned char in_abase;
unsigned char out_dst;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_3;
+ unsigned char out_h_gr_add__VM_index_of_dst_1;
+ unsigned char out_h_gr_add__VM_index_of_dst_2;
+ unsigned char out_h_gr_add__VM_index_of_dst_3;
} fmt_ldq_indirect_offset;
struct { /* e.g. ldq ($abase), $dst */
UINT f_srcdst;
@@ -778,9 +806,9 @@ union sem_fields {
SI * i_dst;
unsigned char in_abase;
unsigned char out_dst;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_3;
+ unsigned char out_h_gr_add__VM_index_of_dst_1;
+ unsigned char out_h_gr_add__VM_index_of_dst_2;
+ unsigned char out_h_gr_add__VM_index_of_dst_3;
} fmt_ldq_indirect;
struct { /* e.g. ldq ($abase)[$index*S$scale], $dst */
UINT f_srcdst;
@@ -791,18 +819,18 @@ union sem_fields {
unsigned char in_abase;
unsigned char in_index;
unsigned char out_dst;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_3;
+ unsigned char out_h_gr_add__VM_index_of_dst_1;
+ unsigned char out_h_gr_add__VM_index_of_dst_2;
+ unsigned char out_h_gr_add__VM_index_of_dst_3;
} fmt_ldq_indirect_index;
struct { /* e.g. ldq $optdisp, $dst */
UINT f_srcdst;
UINT f_optdisp;
SI * i_dst;
unsigned char out_dst;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_3;
+ unsigned char out_h_gr_add__VM_index_of_dst_1;
+ unsigned char out_h_gr_add__VM_index_of_dst_2;
+ unsigned char out_h_gr_add__VM_index_of_dst_3;
} fmt_ldq_disp;
struct { /* e.g. ldq $optdisp($abase), $dst */
UINT f_srcdst;
@@ -811,9 +839,9 @@ union sem_fields {
SI * i_dst;
unsigned char in_abase;
unsigned char out_dst;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_3;
+ unsigned char out_h_gr_add__VM_index_of_dst_1;
+ unsigned char out_h_gr_add__VM_index_of_dst_2;
+ unsigned char out_h_gr_add__VM_index_of_dst_3;
} fmt_ldq_indirect_disp;
struct { /* e.g. ldq $optdisp[$index*S$scale], $dst */
UINT f_srcdst;
@@ -823,9 +851,9 @@ union sem_fields {
SI * i_dst;
unsigned char in_index;
unsigned char out_dst;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_3;
+ unsigned char out_h_gr_add__VM_index_of_dst_1;
+ unsigned char out_h_gr_add__VM_index_of_dst_2;
+ unsigned char out_h_gr_add__VM_index_of_dst_3;
} fmt_ldq_index_disp;
struct { /* e.g. ldq $optdisp($abase)[$index*S$scale], $dst */
UINT f_srcdst;
@@ -837,9 +865,9 @@ union sem_fields {
unsigned char in_abase;
unsigned char in_index;
unsigned char out_dst;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
- unsigned char out_h_gr_add__VM_index_of_dst_const__WI_3;
+ unsigned char out_h_gr_add__VM_index_of_dst_1;
+ unsigned char out_h_gr_add__VM_index_of_dst_2;
+ unsigned char out_h_gr_add__VM_index_of_dst_3;
} fmt_ldq_indirect_index_disp;
struct { /* e.g. st $st_src, $offset */
UINT f_offset;
@@ -1016,7 +1044,7 @@ union sem_fields {
UINT f_srcdst;
UINT f_offset;
SI * i_st_src;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
+ unsigned char in_h_gr_add__VM_index_of_st_src_1;
unsigned char in_st_src;
} fmt_stl_offset;
struct { /* e.g. stl $st_src, $offset($abase) */
@@ -1025,7 +1053,7 @@ union sem_fields {
SI * i_abase;
SI * i_st_src;
unsigned char in_abase;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
+ unsigned char in_h_gr_add__VM_index_of_st_src_1;
unsigned char in_st_src;
} fmt_stl_indirect_offset;
struct { /* e.g. stl $st_src, ($abase) */
@@ -1033,7 +1061,7 @@ union sem_fields {
SI * i_abase;
SI * i_st_src;
unsigned char in_abase;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
+ unsigned char in_h_gr_add__VM_index_of_st_src_1;
unsigned char in_st_src;
} fmt_stl_indirect;
struct { /* e.g. stl $st_src, ($abase)[$index*S$scale] */
@@ -1043,7 +1071,7 @@ union sem_fields {
SI * i_index;
SI * i_st_src;
unsigned char in_abase;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
+ unsigned char in_h_gr_add__VM_index_of_st_src_1;
unsigned char in_index;
unsigned char in_st_src;
} fmt_stl_indirect_index;
@@ -1051,7 +1079,7 @@ union sem_fields {
UINT f_srcdst;
UINT f_optdisp;
SI * i_st_src;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
+ unsigned char in_h_gr_add__VM_index_of_st_src_1;
unsigned char in_st_src;
} fmt_stl_disp;
struct { /* e.g. stl $st_src, $optdisp($abase) */
@@ -1060,7 +1088,7 @@ union sem_fields {
SI * i_abase;
SI * i_st_src;
unsigned char in_abase;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
+ unsigned char in_h_gr_add__VM_index_of_st_src_1;
unsigned char in_st_src;
} fmt_stl_indirect_disp;
struct { /* e.g. stl $st_src, $optdisp[$index*S$scale */
@@ -1069,7 +1097,7 @@ union sem_fields {
UINT f_scale;
SI * i_index;
SI * i_st_src;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
+ unsigned char in_h_gr_add__VM_index_of_st_src_1;
unsigned char in_index;
unsigned char in_st_src;
} fmt_stl_index_disp;
@@ -1081,7 +1109,7 @@ union sem_fields {
SI * i_index;
SI * i_st_src;
unsigned char in_abase;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
+ unsigned char in_h_gr_add__VM_index_of_st_src_1;
unsigned char in_index;
unsigned char in_st_src;
} fmt_stl_indirect_index_disp;
@@ -1089,8 +1117,8 @@ union sem_fields {
UINT f_srcdst;
UINT f_offset;
SI * i_st_src;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
+ unsigned char in_h_gr_add__VM_index_of_st_src_1;
+ unsigned char in_h_gr_add__VM_index_of_st_src_2;
unsigned char in_st_src;
} fmt_stt_offset;
struct { /* e.g. stt $st_src, $offset($abase) */
@@ -1099,8 +1127,8 @@ union sem_fields {
SI * i_abase;
SI * i_st_src;
unsigned char in_abase;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
+ unsigned char in_h_gr_add__VM_index_of_st_src_1;
+ unsigned char in_h_gr_add__VM_index_of_st_src_2;
unsigned char in_st_src;
} fmt_stt_indirect_offset;
struct { /* e.g. stt $st_src, ($abase) */
@@ -1108,8 +1136,8 @@ union sem_fields {
SI * i_abase;
SI * i_st_src;
unsigned char in_abase;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
+ unsigned char in_h_gr_add__VM_index_of_st_src_1;
+ unsigned char in_h_gr_add__VM_index_of_st_src_2;
unsigned char in_st_src;
} fmt_stt_indirect;
struct { /* e.g. stt $st_src, ($abase)[$index*S$scale] */
@@ -1119,8 +1147,8 @@ union sem_fields {
SI * i_index;
SI * i_st_src;
unsigned char in_abase;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
+ unsigned char in_h_gr_add__VM_index_of_st_src_1;
+ unsigned char in_h_gr_add__VM_index_of_st_src_2;
unsigned char in_index;
unsigned char in_st_src;
} fmt_stt_indirect_index;
@@ -1128,8 +1156,8 @@ union sem_fields {
UINT f_srcdst;
UINT f_optdisp;
SI * i_st_src;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
+ unsigned char in_h_gr_add__VM_index_of_st_src_1;
+ unsigned char in_h_gr_add__VM_index_of_st_src_2;
unsigned char in_st_src;
} fmt_stt_disp;
struct { /* e.g. stt $st_src, $optdisp($abase) */
@@ -1138,8 +1166,8 @@ union sem_fields {
SI * i_abase;
SI * i_st_src;
unsigned char in_abase;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
+ unsigned char in_h_gr_add__VM_index_of_st_src_1;
+ unsigned char in_h_gr_add__VM_index_of_st_src_2;
unsigned char in_st_src;
} fmt_stt_indirect_disp;
struct { /* e.g. stt $st_src, $optdisp[$index*S$scale */
@@ -1148,8 +1176,8 @@ union sem_fields {
UINT f_scale;
SI * i_index;
SI * i_st_src;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
+ unsigned char in_h_gr_add__VM_index_of_st_src_1;
+ unsigned char in_h_gr_add__VM_index_of_st_src_2;
unsigned char in_index;
unsigned char in_st_src;
} fmt_stt_index_disp;
@@ -1161,8 +1189,8 @@ union sem_fields {
SI * i_index;
SI * i_st_src;
unsigned char in_abase;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
+ unsigned char in_h_gr_add__VM_index_of_st_src_1;
+ unsigned char in_h_gr_add__VM_index_of_st_src_2;
unsigned char in_index;
unsigned char in_st_src;
} fmt_stt_indirect_index_disp;
@@ -1170,9 +1198,9 @@ union sem_fields {
UINT f_srcdst;
UINT f_offset;
SI * i_st_src;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_3;
+ unsigned char in_h_gr_add__VM_index_of_st_src_1;
+ unsigned char in_h_gr_add__VM_index_of_st_src_2;
+ unsigned char in_h_gr_add__VM_index_of_st_src_3;
unsigned char in_st_src;
} fmt_stq_offset;
struct { /* e.g. stq $st_src, $offset($abase) */
@@ -1181,9 +1209,9 @@ union sem_fields {
SI * i_abase;
SI * i_st_src;
unsigned char in_abase;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_3;
+ unsigned char in_h_gr_add__VM_index_of_st_src_1;
+ unsigned char in_h_gr_add__VM_index_of_st_src_2;
+ unsigned char in_h_gr_add__VM_index_of_st_src_3;
unsigned char in_st_src;
} fmt_stq_indirect_offset;
struct { /* e.g. stq $st_src, ($abase) */
@@ -1191,9 +1219,9 @@ union sem_fields {
SI * i_abase;
SI * i_st_src;
unsigned char in_abase;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_3;
+ unsigned char in_h_gr_add__VM_index_of_st_src_1;
+ unsigned char in_h_gr_add__VM_index_of_st_src_2;
+ unsigned char in_h_gr_add__VM_index_of_st_src_3;
unsigned char in_st_src;
} fmt_stq_indirect;
struct { /* e.g. stq $st_src, ($abase)[$index*S$scale] */
@@ -1203,9 +1231,9 @@ union sem_fields {
SI * i_index;
SI * i_st_src;
unsigned char in_abase;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_3;
+ unsigned char in_h_gr_add__VM_index_of_st_src_1;
+ unsigned char in_h_gr_add__VM_index_of_st_src_2;
+ unsigned char in_h_gr_add__VM_index_of_st_src_3;
unsigned char in_index;
unsigned char in_st_src;
} fmt_stq_indirect_index;
@@ -1213,9 +1241,9 @@ union sem_fields {
UINT f_srcdst;
UINT f_optdisp;
SI * i_st_src;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_3;
+ unsigned char in_h_gr_add__VM_index_of_st_src_1;
+ unsigned char in_h_gr_add__VM_index_of_st_src_2;
+ unsigned char in_h_gr_add__VM_index_of_st_src_3;
unsigned char in_st_src;
} fmt_stq_disp;
struct { /* e.g. stq $st_src, $optdisp($abase) */
@@ -1224,9 +1252,9 @@ union sem_fields {
SI * i_abase;
SI * i_st_src;
unsigned char in_abase;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_3;
+ unsigned char in_h_gr_add__VM_index_of_st_src_1;
+ unsigned char in_h_gr_add__VM_index_of_st_src_2;
+ unsigned char in_h_gr_add__VM_index_of_st_src_3;
unsigned char in_st_src;
} fmt_stq_indirect_disp;
struct { /* e.g. stq $st_src, $optdisp[$index*S$scale */
@@ -1235,9 +1263,9 @@ union sem_fields {
UINT f_scale;
SI * i_index;
SI * i_st_src;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_3;
+ unsigned char in_h_gr_add__VM_index_of_st_src_1;
+ unsigned char in_h_gr_add__VM_index_of_st_src_2;
+ unsigned char in_h_gr_add__VM_index_of_st_src_3;
unsigned char in_index;
unsigned char in_st_src;
} fmt_stq_index_disp;
@@ -1249,9 +1277,9 @@ union sem_fields {
SI * i_index;
SI * i_st_src;
unsigned char in_abase;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
- unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_3;
+ unsigned char in_h_gr_add__VM_index_of_st_src_1;
+ unsigned char in_h_gr_add__VM_index_of_st_src_2;
+ unsigned char in_h_gr_add__VM_index_of_st_src_3;
unsigned char in_index;
unsigned char in_st_src;
} fmt_stq_indirect_index_disp;
diff --git a/sim/i960/decode.c b/sim/i960/decode.c
index 2bb81ee..a3ac523 100644
--- a/sim/i960/decode.c
+++ b/sim/i960/decode.c
@@ -46,6 +46,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#define FAST(fn)
#endif
+/* The INSN_ prefix is not here and is instead part of the `insn' argument
+ to avoid collisions with header files (e.g. `AND' in ansidecl.h). */
+#define IDX(insn) CONCAT2 (I960BASE_,insn)
+#define TYPE(insn) CONCAT2 (I960_,insn)
+
/* The instruction descriptor array.
This is computed at runtime. Space for it is not malloc'd to save a
teensy bit of cpu in the decoder. Moving it to malloc space is trivial
@@ -53,11 +58,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
addition of instructions nor an SMP machine with different cpus). */
static IDESC i960base_insn_data[I960BASE_INSN_MAX];
-/* The INSN_ prefix is not here and is instead part of the `insn' argument
- to avoid collisions with header files (e.g. `AND' in ansidecl.h). */
-#define IDX(insn) CONCAT2 (I960BASE_,insn)
-#define TYPE(insn) CONCAT2 (I960_,insn)
-
/* Commas between elements are contained in the macros.
Some of these are conditionally compiled out. */
@@ -129,10 +129,18 @@ static const struct insn_sem i960base_insn_sem[] =
{ TYPE (INSN_NOR1), IDX (INSN_NOR1), FULL (nor1) FAST (nor1) },
{ TYPE (INSN_NOR2), IDX (INSN_NOR2), FULL (nor2) FAST (nor2) },
{ TYPE (INSN_NOR3), IDX (INSN_NOR3), FULL (nor3) FAST (nor3) },
+ { TYPE (INSN_XNOR), IDX (INSN_XNOR), FULL (xnor) FAST (xnor) },
+ { TYPE (INSN_XNOR1), IDX (INSN_XNOR1), FULL (xnor1) FAST (xnor1) },
+ { TYPE (INSN_XNOR2), IDX (INSN_XNOR2), FULL (xnor2) FAST (xnor2) },
+ { TYPE (INSN_XNOR3), IDX (INSN_XNOR3), FULL (xnor3) FAST (xnor3) },
{ TYPE (INSN_NOT), IDX (INSN_NOT), FULL (not) FAST (not) },
{ TYPE (INSN_NOT1), IDX (INSN_NOT1), FULL (not1) FAST (not1) },
{ TYPE (INSN_NOT2), IDX (INSN_NOT2), FULL (not2) FAST (not2) },
{ TYPE (INSN_NOT3), IDX (INSN_NOT3), FULL (not3) FAST (not3) },
+ { TYPE (INSN_ORNOT), IDX (INSN_ORNOT), FULL (ornot) FAST (ornot) },
+ { TYPE (INSN_ORNOT1), IDX (INSN_ORNOT1), FULL (ornot1) FAST (ornot1) },
+ { TYPE (INSN_ORNOT2), IDX (INSN_ORNOT2), FULL (ornot2) FAST (ornot2) },
+ { TYPE (INSN_ORNOT3), IDX (INSN_ORNOT3), FULL (ornot3) FAST (ornot3) },
{ TYPE (INSN_CLRBIT), IDX (INSN_CLRBIT), FULL (clrbit) FAST (clrbit) },
{ TYPE (INSN_CLRBIT1), IDX (INSN_CLRBIT1), FULL (clrbit1) FAST (clrbit1) },
{ TYPE (INSN_CLRBIT2), IDX (INSN_CLRBIT2), FULL (clrbit2) FAST (clrbit2) },
@@ -359,6 +367,9 @@ static const struct insn_sem i960base_insn_sem_invalid =
VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), FULL (x_invalid) FAST (x_invalid)
};
+#undef FMT
+#undef FULL
+#undef FAST
#undef IDX
#undef TYPE
@@ -420,80 +431,6 @@ i960base_init_idesc_table (SIM_CPU *cpu)
CPU_IDESC (cpu) = table;
}
-/* Enum declaration for all instruction semantic formats. */
-typedef enum sfmt {
- FMT_EMPTY, FMT_MULO, FMT_MULO1, FMT_MULO2
- , FMT_MULO3, FMT_NOTBIT, FMT_NOTBIT1, FMT_NOTBIT2
- , FMT_NOTBIT3, FMT_NOT, FMT_NOT1, FMT_NOT2
- , FMT_NOT3, FMT_EMUL, FMT_EMUL1, FMT_EMUL2
- , FMT_EMUL3, FMT_MOVL, FMT_MOVL1, FMT_MOVT
- , FMT_MOVT1, FMT_MOVQ, FMT_MOVQ1, FMT_MODPC
- , FMT_LDA_OFFSET, FMT_LDA_INDIRECT_OFFSET, FMT_LDA_INDIRECT, FMT_LDA_INDIRECT_INDEX
- , FMT_LDA_DISP, FMT_LDA_INDIRECT_DISP, FMT_LDA_INDEX_DISP, FMT_LDA_INDIRECT_INDEX_DISP
- , FMT_LD_OFFSET, FMT_LD_INDIRECT_OFFSET, FMT_LD_INDIRECT, FMT_LD_INDIRECT_INDEX
- , FMT_LD_DISP, FMT_LD_INDIRECT_DISP, FMT_LD_INDEX_DISP, FMT_LD_INDIRECT_INDEX_DISP
- , FMT_LDOB_OFFSET, FMT_LDOB_INDIRECT_OFFSET, FMT_LDOB_INDIRECT, FMT_LDOB_INDIRECT_INDEX
- , FMT_LDOB_DISP, FMT_LDOB_INDIRECT_DISP, FMT_LDOB_INDEX_DISP, FMT_LDOB_INDIRECT_INDEX_DISP
- , FMT_LDOS_OFFSET, FMT_LDOS_INDIRECT_OFFSET, FMT_LDOS_INDIRECT, FMT_LDOS_INDIRECT_INDEX
- , FMT_LDOS_DISP, FMT_LDOS_INDIRECT_DISP, FMT_LDOS_INDEX_DISP, FMT_LDOS_INDIRECT_INDEX_DISP
- , FMT_LDIB_OFFSET, FMT_LDIB_INDIRECT_OFFSET, FMT_LDIB_INDIRECT, FMT_LDIB_INDIRECT_INDEX
- , FMT_LDIB_DISP, FMT_LDIB_INDIRECT_DISP, FMT_LDIB_INDEX_DISP, FMT_LDIB_INDIRECT_INDEX_DISP
- , FMT_LDIS_OFFSET, FMT_LDIS_INDIRECT_OFFSET, FMT_LDIS_INDIRECT, FMT_LDIS_INDIRECT_INDEX
- , FMT_LDIS_DISP, FMT_LDIS_INDIRECT_DISP, FMT_LDIS_INDEX_DISP, FMT_LDIS_INDIRECT_INDEX_DISP
- , FMT_LDL_OFFSET, FMT_LDL_INDIRECT_OFFSET, FMT_LDL_INDIRECT, FMT_LDL_INDIRECT_INDEX
- , FMT_LDL_DISP, FMT_LDL_INDIRECT_DISP, FMT_LDL_INDEX_DISP, FMT_LDL_INDIRECT_INDEX_DISP
- , FMT_LDT_OFFSET, FMT_LDT_INDIRECT_OFFSET, FMT_LDT_INDIRECT, FMT_LDT_INDIRECT_INDEX
- , FMT_LDT_DISP, FMT_LDT_INDIRECT_DISP, FMT_LDT_INDEX_DISP, FMT_LDT_INDIRECT_INDEX_DISP
- , FMT_LDQ_OFFSET, FMT_LDQ_INDIRECT_OFFSET, FMT_LDQ_INDIRECT, FMT_LDQ_INDIRECT_INDEX
- , FMT_LDQ_DISP, FMT_LDQ_INDIRECT_DISP, FMT_LDQ_INDEX_DISP, FMT_LDQ_INDIRECT_INDEX_DISP
- , FMT_ST_OFFSET, FMT_ST_INDIRECT_OFFSET, FMT_ST_INDIRECT, FMT_ST_INDIRECT_INDEX
- , FMT_ST_DISP, FMT_ST_INDIRECT_DISP, FMT_ST_INDEX_DISP, FMT_ST_INDIRECT_INDEX_DISP
- , FMT_STOB_OFFSET, FMT_STOB_INDIRECT_OFFSET, FMT_STOB_INDIRECT, FMT_STOB_INDIRECT_INDEX
- , FMT_STOB_DISP, FMT_STOB_INDIRECT_DISP, FMT_STOB_INDEX_DISP, FMT_STOB_INDIRECT_INDEX_DISP
- , FMT_STOS_OFFSET, FMT_STOS_INDIRECT_OFFSET, FMT_STOS_INDIRECT, FMT_STOS_INDIRECT_INDEX
- , FMT_STOS_DISP, FMT_STOS_INDIRECT_DISP, FMT_STOS_INDEX_DISP, FMT_STOS_INDIRECT_INDEX_DISP
- , FMT_STL_OFFSET, FMT_STL_INDIRECT_OFFSET, FMT_STL_INDIRECT, FMT_STL_INDIRECT_INDEX
- , FMT_STL_DISP, FMT_STL_INDIRECT_DISP, FMT_STL_INDEX_DISP, FMT_STL_INDIRECT_INDEX_DISP
- , FMT_STT_OFFSET, FMT_STT_INDIRECT_OFFSET, FMT_STT_INDIRECT, FMT_STT_INDIRECT_INDEX
- , FMT_STT_DISP, FMT_STT_INDIRECT_DISP, FMT_STT_INDEX_DISP, FMT_STT_INDIRECT_INDEX_DISP
- , FMT_STQ_OFFSET, FMT_STQ_INDIRECT_OFFSET, FMT_STQ_INDIRECT, FMT_STQ_INDIRECT_INDEX
- , FMT_STQ_DISP, FMT_STQ_INDIRECT_DISP, FMT_STQ_INDEX_DISP, FMT_STQ_INDIRECT_INDEX_DISP
- , FMT_CMPOBE_REG, FMT_CMPOBE_LIT, FMT_CMPOBL_REG, FMT_CMPOBL_LIT
- , FMT_BBC_REG, FMT_BBC_LIT, FMT_CMPI, FMT_CMPI1
- , FMT_CMPI2, FMT_CMPI3, FMT_CMPO, FMT_CMPO1
- , FMT_CMPO2, FMT_CMPO3, FMT_TESTNO_REG, FMT_BNO
- , FMT_B, FMT_BX_INDIRECT_OFFSET, FMT_BX_INDIRECT, FMT_BX_INDIRECT_INDEX
- , FMT_BX_DISP, FMT_BX_INDIRECT_DISP, FMT_CALLX_DISP, FMT_CALLX_INDIRECT
- , FMT_CALLX_INDIRECT_OFFSET, FMT_RET, FMT_CALLS, FMT_FMARK
- , FMT_FLUSHREG
-} SFMT;
-
-/* The decoder uses this to record insns and direct extraction handling. */
-
-typedef struct {
- const IDESC *idesc;
-#ifdef __GNUC__
- void *sfmt;
-#else
- enum sfmt sfmt;
-#endif
-} DECODE_DESC;
-
-/* Macro to go from decode phase to extraction phase. */
-
-#ifdef __GNUC__
-#define GOTO_EXTRACT(id) goto *(id)->sfmt
-#else
-#define GOTO_EXTRACT(id) goto extract
-#endif
-
-/* The decoder needs a slightly different computed goto switch control. */
-#ifdef __GNUC__
-#define DECODE_SWITCH(N, X) goto *labels_##N[X];
-#else
-#define DECODE_SWITCH(N, X) switch (X)
-#endif
-
/* Given an instruction, return a pointer to its IDESC entry. */
const IDESC *
@@ -501,1409 +438,981 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
CGEN_INSN_INT base_insn,
ARGBUF *abuf)
{
- /* Result of decoder, used by extractor. */
- const DECODE_DESC *idecode;
-
- /* First decode the instruction. */
+ /* Result of decoder. */
+ I960BASE_INSN_TYPE itype;
{
-#define I(insn) & i960base_insn_data[CONCAT2 (I960BASE_,insn)]
-#ifdef __GNUC__
-#define E(fmt) && case_ex_##fmt
-#else
-#define E(fmt) fmt
-#endif
- CGEN_INSN_INT insn = base_insn;
- static const DECODE_DESC idecode_invalid = { I (INSN_X_INVALID), E (FMT_EMPTY) };
-
- {
-#ifdef __GNUC__
- static const void *labels_0[256] = {
- && default_0, && default_0, && default_0, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- && case_0_48, && case_0_49, && case_0_50, && case_0_51,
- && case_0_52, && case_0_53, && case_0_54, && case_0_55,
- && default_0, && case_0_57, && case_0_58, && case_0_59,
- && case_0_60, && case_0_61, && case_0_62, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- && case_0_88, && case_0_89, && case_0_90, && default_0,
- && case_0_92, && case_0_93, && case_0_94, && case_0_95,
- && default_0, && default_0, && default_0, && default_0,
- && default_0, && default_0, && case_0_102, && case_0_103,
- && default_0, && default_0, && default_0, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- && case_0_112, && default_0, && default_0, && default_0,
- && case_0_116, && default_0, && default_0, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- && case_0_128, && default_0, && case_0_130, && default_0,
- && case_0_132, && default_0, && case_0_134, && default_0,
- && case_0_136, && default_0, && case_0_138, && default_0,
- && case_0_140, && default_0, && default_0, && default_0,
- && case_0_144, && default_0, && case_0_146, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- && case_0_152, && default_0, && case_0_154, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- && case_0_160, && default_0, && case_0_162, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- && case_0_176, && default_0, && case_0_178, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- && case_0_192, && default_0, && default_0, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- && case_0_200, && default_0, && default_0, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- && default_0, && default_0, && default_0, && default_0,
- };
-#endif
- static const DECODE_DESC insns[256] = {
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_B), E (FMT_B) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_RET), E (FMT_RET) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_BNO), E (FMT_BNO) }, { I (INSN_BG), E (FMT_BNO) },
- { I (INSN_BE), E (FMT_BNO) }, { I (INSN_BGE), E (FMT_BNO) },
- { I (INSN_BL), E (FMT_BNO) }, { I (INSN_BNE), E (FMT_BNO) },
- { I (INSN_BLE), E (FMT_BNO) }, { I (INSN_BO), E (FMT_BNO) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_TESTNO_REG), E (FMT_TESTNO_REG) }, { I (INSN_TESTG_REG), E (FMT_TESTNO_REG) },
- { I (INSN_TESTE_REG), E (FMT_TESTNO_REG) }, { I (INSN_TESTGE_REG), E (FMT_TESTNO_REG) },
- { I (INSN_TESTL_REG), E (FMT_TESTNO_REG) }, { I (INSN_TESTNE_REG), E (FMT_TESTNO_REG) },
- { I (INSN_TESTLE_REG), E (FMT_TESTNO_REG) }, { I (INSN_TESTO_REG), E (FMT_TESTNO_REG) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { 0 }, { 0 },
- { 0 }, { 0 },
- { 0 }, { 0 },
- { 0 }, { 0 },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { 0 },
- { 0 }, { 0 },
- { 0 }, { 0 },
- { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { 0 }, { 0 },
- { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { 0 }, { 0 },
- { 0 }, { 0 },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_MODAC), E (FMT_MODPC) }, { I (INSN_MODPC), E (FMT_MODPC) },
- { 0 }, { 0 },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val;
- val = (((insn >> 24) & (255 << 0)));
- DECODE_SWITCH (0, val)
+ CGEN_INSN_INT insn = base_insn;
+
+ {
+ unsigned int val = (((insn >> 24) & (255 << 0)));
+ switch (val)
+ {
+ case 8 : itype = I960BASE_INSN_B; goto extract_fmt_b;
+ case 10 : itype = I960BASE_INSN_RET; goto extract_fmt_ret;
+ case 16 : itype = I960BASE_INSN_BNO; goto extract_fmt_bno;
+ case 17 : itype = I960BASE_INSN_BG; goto extract_fmt_bno;
+ case 18 : itype = I960BASE_INSN_BE; goto extract_fmt_bno;
+ case 19 : itype = I960BASE_INSN_BGE; goto extract_fmt_bno;
+ case 20 : itype = I960BASE_INSN_BL; goto extract_fmt_bno;
+ case 21 : itype = I960BASE_INSN_BNE; goto extract_fmt_bno;
+ case 22 : itype = I960BASE_INSN_BLE; goto extract_fmt_bno;
+ case 23 : itype = I960BASE_INSN_BO; goto extract_fmt_bno;
+ case 32 : itype = I960BASE_INSN_TESTNO_REG; goto extract_fmt_testno_reg;
+ case 33 : itype = I960BASE_INSN_TESTG_REG; goto extract_fmt_testno_reg;
+ case 34 : itype = I960BASE_INSN_TESTE_REG; goto extract_fmt_testno_reg;
+ case 35 : itype = I960BASE_INSN_TESTGE_REG; goto extract_fmt_testno_reg;
+ case 36 : itype = I960BASE_INSN_TESTL_REG; goto extract_fmt_testno_reg;
+ case 37 : itype = I960BASE_INSN_TESTNE_REG; goto extract_fmt_testno_reg;
+ case 38 : itype = I960BASE_INSN_TESTLE_REG; goto extract_fmt_testno_reg;
+ case 39 : itype = I960BASE_INSN_TESTO_REG; goto extract_fmt_testno_reg;
+ case 48 :
{
- CASE (0, 48) :
+ unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
+ switch (val)
{
- static const DECODE_DESC insns[8] = {
- { I (INSN_BBC_REG), E (FMT_BBC_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_BBC_LIT), E (FMT_BBC_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 0 : itype = I960BASE_INSN_BBC_REG; goto extract_fmt_bbc_reg;
+ case 4 : itype = I960BASE_INSN_BBC_LIT; goto extract_fmt_bbc_lit;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- CASE (0, 49) :
+ }
+ case 49 :
+ {
+ unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
+ switch (val)
{
- static const DECODE_DESC insns[8] = {
- { I (INSN_CMPOBG_REG), E (FMT_CMPOBL_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_CMPOBG_LIT), E (FMT_CMPOBL_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 0 : itype = I960BASE_INSN_CMPOBG_REG; goto extract_fmt_cmpobl_reg;
+ case 4 : itype = I960BASE_INSN_CMPOBG_LIT; goto extract_fmt_cmpobl_lit;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- CASE (0, 50) :
+ }
+ case 50 :
+ {
+ unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
+ switch (val)
{
- static const DECODE_DESC insns[8] = {
- { I (INSN_CMPOBE_REG), E (FMT_CMPOBE_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_CMPOBE_LIT), E (FMT_CMPOBE_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 0 : itype = I960BASE_INSN_CMPOBE_REG; goto extract_fmt_cmpobe_reg;
+ case 4 : itype = I960BASE_INSN_CMPOBE_LIT; goto extract_fmt_cmpobe_lit;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- CASE (0, 51) :
+ }
+ case 51 :
+ {
+ unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
+ switch (val)
{
- static const DECODE_DESC insns[8] = {
- { I (INSN_CMPOBGE_REG), E (FMT_CMPOBL_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_CMPOBGE_LIT), E (FMT_CMPOBL_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 0 : itype = I960BASE_INSN_CMPOBGE_REG; goto extract_fmt_cmpobl_reg;
+ case 4 : itype = I960BASE_INSN_CMPOBGE_LIT; goto extract_fmt_cmpobl_lit;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- CASE (0, 52) :
+ }
+ case 52 :
+ {
+ unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
+ switch (val)
{
- static const DECODE_DESC insns[8] = {
- { I (INSN_CMPOBL_REG), E (FMT_CMPOBL_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_CMPOBL_LIT), E (FMT_CMPOBL_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 0 : itype = I960BASE_INSN_CMPOBL_REG; goto extract_fmt_cmpobl_reg;
+ case 4 : itype = I960BASE_INSN_CMPOBL_LIT; goto extract_fmt_cmpobl_lit;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- CASE (0, 53) :
+ }
+ case 53 :
+ {
+ unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
+ switch (val)
{
- static const DECODE_DESC insns[8] = {
- { I (INSN_CMPOBNE_REG), E (FMT_CMPOBE_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_CMPOBNE_LIT), E (FMT_CMPOBE_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 0 : itype = I960BASE_INSN_CMPOBNE_REG; goto extract_fmt_cmpobe_reg;
+ case 4 : itype = I960BASE_INSN_CMPOBNE_LIT; goto extract_fmt_cmpobe_lit;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- CASE (0, 54) :
+ }
+ case 54 :
+ {
+ unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
+ switch (val)
{
- static const DECODE_DESC insns[8] = {
- { I (INSN_CMPOBLE_REG), E (FMT_CMPOBL_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_CMPOBLE_LIT), E (FMT_CMPOBL_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 0 : itype = I960BASE_INSN_CMPOBLE_REG; goto extract_fmt_cmpobl_reg;
+ case 4 : itype = I960BASE_INSN_CMPOBLE_LIT; goto extract_fmt_cmpobl_lit;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- CASE (0, 55) :
+ }
+ case 55 :
+ {
+ unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
+ switch (val)
{
- static const DECODE_DESC insns[8] = {
- { I (INSN_BBS_REG), E (FMT_BBC_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_BBS_LIT), E (FMT_BBC_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 0 : itype = I960BASE_INSN_BBS_REG; goto extract_fmt_bbc_reg;
+ case 4 : itype = I960BASE_INSN_BBS_LIT; goto extract_fmt_bbc_lit;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- CASE (0, 57) :
+ }
+ case 57 :
+ {
+ unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
+ switch (val)
{
- static const DECODE_DESC insns[8] = {
- { I (INSN_CMPIBG_REG), E (FMT_CMPOBE_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_CMPIBG_LIT), E (FMT_CMPOBE_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 0 : itype = I960BASE_INSN_CMPIBG_REG; goto extract_fmt_cmpobe_reg;
+ case 4 : itype = I960BASE_INSN_CMPIBG_LIT; goto extract_fmt_cmpobe_lit;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- CASE (0, 58) :
+ }
+ case 58 :
+ {
+ unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
+ switch (val)
{
- static const DECODE_DESC insns[8] = {
- { I (INSN_CMPIBE_REG), E (FMT_CMPOBE_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_CMPIBE_LIT), E (FMT_CMPOBE_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 0 : itype = I960BASE_INSN_CMPIBE_REG; goto extract_fmt_cmpobe_reg;
+ case 4 : itype = I960BASE_INSN_CMPIBE_LIT; goto extract_fmt_cmpobe_lit;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- CASE (0, 59) :
+ }
+ case 59 :
+ {
+ unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
+ switch (val)
{
- static const DECODE_DESC insns[8] = {
- { I (INSN_CMPIBGE_REG), E (FMT_CMPOBE_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_CMPIBGE_LIT), E (FMT_CMPOBE_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 0 : itype = I960BASE_INSN_CMPIBGE_REG; goto extract_fmt_cmpobe_reg;
+ case 4 : itype = I960BASE_INSN_CMPIBGE_LIT; goto extract_fmt_cmpobe_lit;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- CASE (0, 60) :
+ }
+ case 60 :
+ {
+ unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
+ switch (val)
{
- static const DECODE_DESC insns[8] = {
- { I (INSN_CMPIBL_REG), E (FMT_CMPOBE_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_CMPIBL_LIT), E (FMT_CMPOBE_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 0 : itype = I960BASE_INSN_CMPIBL_REG; goto extract_fmt_cmpobe_reg;
+ case 4 : itype = I960BASE_INSN_CMPIBL_LIT; goto extract_fmt_cmpobe_lit;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- CASE (0, 61) :
+ }
+ case 61 :
+ {
+ unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
+ switch (val)
{
- static const DECODE_DESC insns[8] = {
- { I (INSN_CMPIBNE_REG), E (FMT_CMPOBE_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_CMPIBNE_LIT), E (FMT_CMPOBE_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 0 : itype = I960BASE_INSN_CMPIBNE_REG; goto extract_fmt_cmpobe_reg;
+ case 4 : itype = I960BASE_INSN_CMPIBNE_LIT; goto extract_fmt_cmpobe_lit;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- CASE (0, 62) :
+ }
+ case 62 :
+ {
+ unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
+ switch (val)
{
- static const DECODE_DESC insns[8] = {
- { I (INSN_CMPIBLE_REG), E (FMT_CMPOBE_REG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_CMPIBLE_LIT), E (FMT_CMPOBE_LIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 11) & (1 << 2)) | ((insn >> 0) & (3 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 0 : itype = I960BASE_INSN_CMPIBLE_REG; goto extract_fmt_cmpobe_reg;
+ case 4 : itype = I960BASE_INSN_CMPIBLE_LIT; goto extract_fmt_cmpobe_lit;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- CASE (0, 88) :
+ }
+ case 88 :
+ {
+ unsigned int val = (((insn >> 10) & (15 << 0)));
+ switch (val)
{
-#ifdef __GNUC__
- static const void *labels_0_88[16] = {
- && case_0_88_0, && case_0_88_1, && case_0_88_2, && case_0_88_3,
- && case_0_88_4, && case_0_88_5, && case_0_88_6, && case_0_88_7,
- && default_0_88, && default_0_88, && default_0_88, && default_0_88,
- && default_0_88, && default_0_88, && default_0_88, && default_0_88,
- };
-#endif
- static const DECODE_DESC insns[16] = {
- { 0 }, { 0 },
- { 0 }, { 0 },
- { 0 }, { 0 },
- { 0 }, { 0 },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val;
- val = (((insn >> 10) & (15 << 0)));
- DECODE_SWITCH (0_88, val)
+ case 0 :
+ {
+ unsigned int val = (((insn >> 6) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : itype = I960BASE_INSN_NOTBIT; goto extract_fmt_notbit;
+ case 2 : itype = I960BASE_INSN_AND; goto extract_fmt_mulo;
+ case 4 : itype = I960BASE_INSN_ANDNOT; goto extract_fmt_mulo;
+ case 6 : itype = I960BASE_INSN_SETBIT; goto extract_fmt_notbit;
+ case 8 : itype = I960BASE_INSN_NOTAND; goto extract_fmt_mulo;
+ case 12 : itype = I960BASE_INSN_XOR; goto extract_fmt_mulo;
+ case 14 : itype = I960BASE_INSN_OR; goto extract_fmt_mulo;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
+ }
+ }
+ case 1 :
+ {
+ unsigned int val = (((insn >> 6) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : itype = I960BASE_INSN_NOR; goto extract_fmt_mulo;
+ case 2 : itype = I960BASE_INSN_XNOR; goto extract_fmt_mulo;
+ case 4 : itype = I960BASE_INSN_NOT; goto extract_fmt_not;
+ case 6 : itype = I960BASE_INSN_ORNOT; goto extract_fmt_mulo;
+ case 8 : itype = I960BASE_INSN_CLRBIT; goto extract_fmt_notbit;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
+ }
+ }
+ case 2 :
+ {
+ unsigned int val = (((insn >> 6) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : itype = I960BASE_INSN_NOTBIT1; goto extract_fmt_notbit1;
+ case 2 : itype = I960BASE_INSN_AND1; goto extract_fmt_mulo1;
+ case 4 : itype = I960BASE_INSN_ANDNOT1; goto extract_fmt_mulo1;
+ case 6 : itype = I960BASE_INSN_SETBIT1; goto extract_fmt_notbit1;
+ case 8 : itype = I960BASE_INSN_NOTAND1; goto extract_fmt_mulo1;
+ case 12 : itype = I960BASE_INSN_XOR1; goto extract_fmt_mulo1;
+ case 14 : itype = I960BASE_INSN_OR1; goto extract_fmt_mulo1;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
+ }
+ }
+ case 3 :
+ {
+ unsigned int val = (((insn >> 6) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : itype = I960BASE_INSN_NOR1; goto extract_fmt_mulo1;
+ case 2 : itype = I960BASE_INSN_XNOR1; goto extract_fmt_mulo1;
+ case 4 : itype = I960BASE_INSN_NOT1; goto extract_fmt_not1;
+ case 6 : itype = I960BASE_INSN_ORNOT1; goto extract_fmt_mulo1;
+ case 8 : itype = I960BASE_INSN_CLRBIT1; goto extract_fmt_notbit1;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
+ }
+ }
+ case 4 :
+ {
+ unsigned int val = (((insn >> 6) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : itype = I960BASE_INSN_NOTBIT2; goto extract_fmt_notbit2;
+ case 2 : itype = I960BASE_INSN_AND2; goto extract_fmt_mulo2;
+ case 4 : itype = I960BASE_INSN_ANDNOT2; goto extract_fmt_mulo2;
+ case 6 : itype = I960BASE_INSN_SETBIT2; goto extract_fmt_notbit2;
+ case 8 : itype = I960BASE_INSN_NOTAND2; goto extract_fmt_mulo2;
+ case 12 : itype = I960BASE_INSN_XOR2; goto extract_fmt_mulo2;
+ case 14 : itype = I960BASE_INSN_OR2; goto extract_fmt_mulo2;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
+ }
+ }
+ case 5 :
+ {
+ unsigned int val = (((insn >> 6) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : itype = I960BASE_INSN_NOR2; goto extract_fmt_mulo2;
+ case 2 : itype = I960BASE_INSN_XNOR2; goto extract_fmt_mulo2;
+ case 4 : itype = I960BASE_INSN_NOT2; goto extract_fmt_not2;
+ case 6 : itype = I960BASE_INSN_ORNOT2; goto extract_fmt_mulo2;
+ case 8 : itype = I960BASE_INSN_CLRBIT2; goto extract_fmt_notbit2;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
+ }
+ }
+ case 6 :
+ {
+ unsigned int val = (((insn >> 6) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : itype = I960BASE_INSN_NOTBIT3; goto extract_fmt_notbit3;
+ case 2 : itype = I960BASE_INSN_AND3; goto extract_fmt_mulo3;
+ case 4 : itype = I960BASE_INSN_ANDNOT3; goto extract_fmt_mulo3;
+ case 6 : itype = I960BASE_INSN_SETBIT3; goto extract_fmt_notbit3;
+ case 8 : itype = I960BASE_INSN_NOTAND3; goto extract_fmt_mulo3;
+ case 12 : itype = I960BASE_INSN_XOR3; goto extract_fmt_mulo3;
+ case 14 : itype = I960BASE_INSN_OR3; goto extract_fmt_mulo3;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
+ }
+ }
+ case 7 :
+ {
+ unsigned int val = (((insn >> 6) & (15 << 0)));
+ switch (val)
{
- CASE (0_88, 0) :
- {
- static const DECODE_DESC insns[16] = {
- { I (INSN_NOTBIT), E (FMT_NOTBIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_AND), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_ANDNOT), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_SETBIT), E (FMT_NOTBIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_NOTAND), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_XOR), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_OR), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 6) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
- }
- CASE (0_88, 1) :
- {
- static const DECODE_DESC insns[16] = {
- { I (INSN_NOR), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_NOT), E (FMT_NOT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_CLRBIT), E (FMT_NOTBIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 6) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
- }
- CASE (0_88, 2) :
- {
- static const DECODE_DESC insns[16] = {
- { I (INSN_NOTBIT1), E (FMT_NOTBIT1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_AND1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_ANDNOT1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_SETBIT1), E (FMT_NOTBIT1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_NOTAND1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_XOR1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_OR1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 6) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
- }
- CASE (0_88, 3) :
- {
- static const DECODE_DESC insns[16] = {
- { I (INSN_NOR1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_NOT1), E (FMT_NOT1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_CLRBIT1), E (FMT_NOTBIT1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 6) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
- }
- CASE (0_88, 4) :
- {
- static const DECODE_DESC insns[16] = {
- { I (INSN_NOTBIT2), E (FMT_NOTBIT2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_AND2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_ANDNOT2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_SETBIT2), E (FMT_NOTBIT2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_NOTAND2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_XOR2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_OR2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 6) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
- }
- CASE (0_88, 5) :
- {
- static const DECODE_DESC insns[16] = {
- { I (INSN_NOR2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_NOT2), E (FMT_NOT2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_CLRBIT2), E (FMT_NOTBIT2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 6) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
- }
- CASE (0_88, 6) :
- {
- static const DECODE_DESC insns[16] = {
- { I (INSN_NOTBIT3), E (FMT_NOTBIT3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_AND3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_ANDNOT3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_SETBIT3), E (FMT_NOTBIT3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_NOTAND3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_XOR3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_OR3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 6) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
- }
- CASE (0_88, 7) :
- {
- static const DECODE_DESC insns[16] = {
- { I (INSN_NOR3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_NOT3), E (FMT_NOT3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_CLRBIT3), E (FMT_NOTBIT3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 6) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
- }
- DEFAULT (0_88) :
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 0 : itype = I960BASE_INSN_NOR3; goto extract_fmt_mulo3;
+ case 2 : itype = I960BASE_INSN_XNOR3; goto extract_fmt_mulo3;
+ case 4 : itype = I960BASE_INSN_NOT3; goto extract_fmt_not3;
+ case 6 : itype = I960BASE_INSN_ORNOT3; goto extract_fmt_mulo3;
+ case 8 : itype = I960BASE_INSN_CLRBIT3; goto extract_fmt_notbit3;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- ENDSWITCH (0_88)
+ }
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- CASE (0, 89) :
+ }
+ case 89 :
+ {
+ unsigned int val = (((insn >> 10) & (15 << 0)));
+ switch (val)
{
-#ifdef __GNUC__
- static const void *labels_0_89[16] = {
- && case_0_89_0, && case_0_89_1, && case_0_89_2, && case_0_89_3,
- && case_0_89_4, && case_0_89_5, && case_0_89_6, && case_0_89_7,
- && default_0_89, && default_0_89, && default_0_89, && default_0_89,
- && default_0_89, && default_0_89, && default_0_89, && default_0_89,
- };
-#endif
- static const DECODE_DESC insns[16] = {
- { 0 }, { 0 },
- { 0 }, { 0 },
- { 0 }, { 0 },
- { 0 }, { 0 },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val;
- val = (((insn >> 10) & (15 << 0)));
- DECODE_SWITCH (0_89, val)
+ case 0 :
+ {
+ unsigned int val = (((insn >> 6) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : itype = I960BASE_INSN_ADDO; goto extract_fmt_mulo;
+ case 4 : itype = I960BASE_INSN_SUBO; goto extract_fmt_mulo;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
+ }
+ }
+ case 1 :
+ {
+ unsigned int val = (((insn >> 6) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : itype = I960BASE_INSN_SHRO; goto extract_fmt_shlo;
+ case 6 : itype = I960BASE_INSN_SHRI; goto extract_fmt_shlo;
+ case 8 : itype = I960BASE_INSN_SHLO; goto extract_fmt_shlo;
+ case 12 : itype = I960BASE_INSN_SHLI; goto extract_fmt_shlo;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
+ }
+ }
+ case 2 :
+ {
+ unsigned int val = (((insn >> 6) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : itype = I960BASE_INSN_ADDO1; goto extract_fmt_mulo1;
+ case 4 : itype = I960BASE_INSN_SUBO1; goto extract_fmt_mulo1;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
+ }
+ }
+ case 3 :
+ {
+ unsigned int val = (((insn >> 6) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : itype = I960BASE_INSN_SHRO1; goto extract_fmt_shlo1;
+ case 6 : itype = I960BASE_INSN_SHRI1; goto extract_fmt_shlo1;
+ case 8 : itype = I960BASE_INSN_SHLO1; goto extract_fmt_shlo1;
+ case 12 : itype = I960BASE_INSN_SHLI1; goto extract_fmt_shlo1;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
+ }
+ }
+ case 4 :
+ {
+ unsigned int val = (((insn >> 6) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : itype = I960BASE_INSN_ADDO2; goto extract_fmt_mulo2;
+ case 4 : itype = I960BASE_INSN_SUBO2; goto extract_fmt_mulo2;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
+ }
+ }
+ case 5 :
+ {
+ unsigned int val = (((insn >> 6) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : itype = I960BASE_INSN_SHRO2; goto extract_fmt_shlo2;
+ case 6 : itype = I960BASE_INSN_SHRI2; goto extract_fmt_shlo2;
+ case 8 : itype = I960BASE_INSN_SHLO2; goto extract_fmt_shlo2;
+ case 12 : itype = I960BASE_INSN_SHLI2; goto extract_fmt_shlo2;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
+ }
+ }
+ case 6 :
+ {
+ unsigned int val = (((insn >> 6) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : itype = I960BASE_INSN_ADDO3; goto extract_fmt_mulo3;
+ case 4 : itype = I960BASE_INSN_SUBO3; goto extract_fmt_mulo3;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
+ }
+ }
+ case 7 :
+ {
+ unsigned int val = (((insn >> 6) & (15 << 0)));
+ switch (val)
{
- CASE (0_89, 0) :
- {
- static const DECODE_DESC insns[16] = {
- { I (INSN_ADDO), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_SUBO), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 6) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
- }
- CASE (0_89, 1) :
- {
- static const DECODE_DESC insns[16] = {
- { I (INSN_SHRO), E (FMT_NOTBIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_SHRI), E (FMT_NOTBIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_SHLO), E (FMT_NOTBIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_SHLI), E (FMT_NOTBIT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 6) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
- }
- CASE (0_89, 2) :
- {
- static const DECODE_DESC insns[16] = {
- { I (INSN_ADDO1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_SUBO1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 6) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
- }
- CASE (0_89, 3) :
- {
- static const DECODE_DESC insns[16] = {
- { I (INSN_SHRO1), E (FMT_NOTBIT1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_SHRI1), E (FMT_NOTBIT1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_SHLO1), E (FMT_NOTBIT1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_SHLI1), E (FMT_NOTBIT1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 6) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
- }
- CASE (0_89, 4) :
- {
- static const DECODE_DESC insns[16] = {
- { I (INSN_ADDO2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_SUBO2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 6) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
- }
- CASE (0_89, 5) :
- {
- static const DECODE_DESC insns[16] = {
- { I (INSN_SHRO2), E (FMT_NOTBIT2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_SHRI2), E (FMT_NOTBIT2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_SHLO2), E (FMT_NOTBIT2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_SHLI2), E (FMT_NOTBIT2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 6) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
- }
- CASE (0_89, 6) :
- {
- static const DECODE_DESC insns[16] = {
- { I (INSN_ADDO3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_SUBO3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 6) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
- }
- CASE (0_89, 7) :
- {
- static const DECODE_DESC insns[16] = {
- { I (INSN_SHRO3), E (FMT_NOTBIT3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_SHRI3), E (FMT_NOTBIT3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_SHLO3), E (FMT_NOTBIT3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_SHLI3), E (FMT_NOTBIT3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 6) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
- }
- DEFAULT (0_89) :
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 0 : itype = I960BASE_INSN_SHRO3; goto extract_fmt_shlo3;
+ case 6 : itype = I960BASE_INSN_SHRI3; goto extract_fmt_shlo3;
+ case 8 : itype = I960BASE_INSN_SHLO3; goto extract_fmt_shlo3;
+ case 12 : itype = I960BASE_INSN_SHLI3; goto extract_fmt_shlo3;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- ENDSWITCH (0_89)
+ }
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- CASE (0, 90) :
+ }
+ case 90 :
+ {
+ unsigned int val = (((insn >> 10) & (15 << 0)));
+ switch (val)
{
-#ifdef __GNUC__
- static const void *labels_0_90[16] = {
- && default_0_90, && default_0_90, && default_0_90, && default_0_90,
- && default_0_90, && default_0_90, && default_0_90, && default_0_90,
- && case_0_90_8, && default_0_90, && case_0_90_10, && default_0_90,
- && case_0_90_12, && default_0_90, && case_0_90_14, && default_0_90,
- };
-#endif
- static const DECODE_DESC insns[16] = {
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val;
- val = (((insn >> 10) & (15 << 0)));
- DECODE_SWITCH (0_90, val)
+ case 8 :
+ {
+ unsigned int val = (((insn >> 6) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : itype = I960BASE_INSN_CMPO; goto extract_fmt_cmpo;
+ case 2 : itype = I960BASE_INSN_CMPI; goto extract_fmt_cmpi;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
+ }
+ }
+ case 10 :
+ {
+ unsigned int val = (((insn >> 6) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : itype = I960BASE_INSN_CMPO1; goto extract_fmt_cmpo1;
+ case 2 : itype = I960BASE_INSN_CMPI1; goto extract_fmt_cmpi1;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
+ }
+ }
+ case 12 :
+ {
+ unsigned int val = (((insn >> 6) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : itype = I960BASE_INSN_CMPO2; goto extract_fmt_cmpo2;
+ case 2 : itype = I960BASE_INSN_CMPI2; goto extract_fmt_cmpi2;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
+ }
+ }
+ case 14 :
+ {
+ unsigned int val = (((insn >> 6) & (15 << 0)));
+ switch (val)
{
- CASE (0_90, 8) :
- {
- static const DECODE_DESC insns[16] = {
- { I (INSN_CMPO), E (FMT_CMPO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_CMPI), E (FMT_CMPI) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 6) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
- }
- CASE (0_90, 10) :
- {
- static const DECODE_DESC insns[16] = {
- { I (INSN_CMPO1), E (FMT_CMPO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_CMPI1), E (FMT_CMPI1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 6) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
- }
- CASE (0_90, 12) :
- {
- static const DECODE_DESC insns[16] = {
- { I (INSN_CMPO2), E (FMT_CMPO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_CMPI2), E (FMT_CMPI2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 6) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
- }
- CASE (0_90, 14) :
- {
- static const DECODE_DESC insns[16] = {
- { I (INSN_CMPO3), E (FMT_CMPO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_CMPI3), E (FMT_CMPI3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 6) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
- }
- DEFAULT (0_90) :
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 0 : itype = I960BASE_INSN_CMPO3; goto extract_fmt_cmpo3;
+ case 2 : itype = I960BASE_INSN_CMPI3; goto extract_fmt_cmpi3;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- ENDSWITCH (0_90)
+ }
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- CASE (0, 92) :
+ }
+ case 92 :
+ {
+ unsigned int val = (((insn >> 10) & (15 << 0)));
+ switch (val)
{
- static const DECODE_DESC insns[16] = {
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_MOV), E (FMT_NOT2) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_MOV1), E (FMT_NOT3) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 10) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 5 : itype = I960BASE_INSN_MOV; goto extract_fmt_not2;
+ case 7 : itype = I960BASE_INSN_MOV1; goto extract_fmt_not3;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- CASE (0, 93) :
+ }
+ case 93 :
+ {
+ unsigned int val = (((insn >> 10) & (15 << 0)));
+ switch (val)
{
- static const DECODE_DESC insns[16] = {
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_MOVL), E (FMT_MOVL) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_MOVL1), E (FMT_MOVL1) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 10) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 5 : itype = I960BASE_INSN_MOVL; goto extract_fmt_movl;
+ case 7 : itype = I960BASE_INSN_MOVL1; goto extract_fmt_movl1;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- CASE (0, 94) :
+ }
+ case 94 :
+ {
+ unsigned int val = (((insn >> 10) & (15 << 0)));
+ switch (val)
{
- static const DECODE_DESC insns[16] = {
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_MOVT), E (FMT_MOVT) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_MOVT1), E (FMT_MOVT1) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 10) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 5 : itype = I960BASE_INSN_MOVT; goto extract_fmt_movt;
+ case 7 : itype = I960BASE_INSN_MOVT1; goto extract_fmt_movt1;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- CASE (0, 95) :
+ }
+ case 95 :
+ {
+ unsigned int val = (((insn >> 10) & (15 << 0)));
+ switch (val)
{
- static const DECODE_DESC insns[16] = {
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_MOVQ), E (FMT_MOVQ) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_MOVQ1), E (FMT_MOVQ1) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 10) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 5 : itype = I960BASE_INSN_MOVQ; goto extract_fmt_movq;
+ case 7 : itype = I960BASE_INSN_MOVQ1; goto extract_fmt_movq1;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- CASE (0, 102) :
+ }
+ case 100 : itype = I960BASE_INSN_MODAC; goto extract_fmt_modpc;
+ case 101 : itype = I960BASE_INSN_MODPC; goto extract_fmt_modpc;
+ case 102 :
+ {
+ unsigned int val = (((insn >> 10) & (15 << 0)));
+ switch (val)
{
-#ifdef __GNUC__
- static const void *labels_0_102[16] = {
- && default_0_102, && default_0_102, && default_0_102, && default_0_102,
- && default_0_102, && default_0_102, && default_0_102, && default_0_102,
- && default_0_102, && default_0_102, && default_0_102, && default_0_102,
- && default_0_102, && default_0_102, && default_0_102, && case_0_102_15,
- };
-#endif
- static const DECODE_DESC insns[16] = {
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_CALLS), E (FMT_CALLS) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { 0 },
- };
- unsigned int val;
- val = (((insn >> 10) & (15 << 0)));
- DECODE_SWITCH (0_102, val)
+ case 12 : itype = I960BASE_INSN_CALLS; goto extract_fmt_calls;
+ case 15 :
+ {
+ unsigned int val = (((insn >> 6) & (15 << 0)));
+ switch (val)
{
- CASE (0_102, 15) :
- {
- static const DECODE_DESC insns[16] = {
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_FMARK), E (FMT_FMARK) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_FLUSHREG), E (FMT_FLUSHREG) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 6) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
- }
- DEFAULT (0_102) :
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 8 : itype = I960BASE_INSN_FMARK; goto extract_fmt_fmark;
+ case 10 : itype = I960BASE_INSN_FLUSHREG; goto extract_fmt_flushreg;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- ENDSWITCH (0_102)
+ }
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- CASE (0, 103) :
+ }
+ case 103 :
+ {
+ unsigned int val = (((insn >> 10) & (15 << 0)));
+ switch (val)
{
- static const DECODE_DESC insns[16] = {
- { I (INSN_EMUL), E (FMT_EMUL) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_EMUL1), E (FMT_EMUL1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_EMUL2), E (FMT_EMUL2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_EMUL3), E (FMT_EMUL3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 10) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 0 : itype = I960BASE_INSN_EMUL; goto extract_fmt_emul;
+ case 2 : itype = I960BASE_INSN_EMUL1; goto extract_fmt_emul1;
+ case 4 : itype = I960BASE_INSN_EMUL2; goto extract_fmt_emul2;
+ case 6 : itype = I960BASE_INSN_EMUL3; goto extract_fmt_emul3;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- CASE (0, 112) :
+ }
+ case 112 :
+ {
+ unsigned int val = (((insn >> 10) & (15 << 0)));
+ switch (val)
{
-#ifdef __GNUC__
- static const void *labels_0_112[16] = {
- && default_0_112, && case_0_112_1, && default_0_112, && case_0_112_3,
- && default_0_112, && case_0_112_5, && default_0_112, && case_0_112_7,
- && default_0_112, && default_0_112, && default_0_112, && default_0_112,
- && default_0_112, && default_0_112, && default_0_112, && default_0_112,
- };
-#endif
- static const DECODE_DESC insns[16] = {
- { I (INSN_MULO), E (FMT_MULO) }, { 0 },
- { I (INSN_MULO1), E (FMT_MULO1) }, { 0 },
- { I (INSN_MULO2), E (FMT_MULO2) }, { 0 },
- { I (INSN_MULO3), E (FMT_MULO3) }, { 0 },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val;
- val = (((insn >> 10) & (15 << 0)));
- DECODE_SWITCH (0_112, val)
+ case 0 : itype = I960BASE_INSN_MULO; goto extract_fmt_mulo;
+ case 1 :
+ {
+ unsigned int val = (((insn >> 6) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : itype = I960BASE_INSN_REMO; goto extract_fmt_mulo;
+ case 6 : itype = I960BASE_INSN_DIVO; goto extract_fmt_mulo;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
+ }
+ }
+ case 2 : itype = I960BASE_INSN_MULO1; goto extract_fmt_mulo1;
+ case 3 :
+ {
+ unsigned int val = (((insn >> 6) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : itype = I960BASE_INSN_REMO1; goto extract_fmt_mulo1;
+ case 6 : itype = I960BASE_INSN_DIVO1; goto extract_fmt_mulo1;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
+ }
+ }
+ case 4 : itype = I960BASE_INSN_MULO2; goto extract_fmt_mulo2;
+ case 5 :
+ {
+ unsigned int val = (((insn >> 6) & (15 << 0)));
+ switch (val)
{
- CASE (0_112, 1) :
- {
- static const DECODE_DESC insns[16] = {
- { I (INSN_REMO), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_DIVO), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 6) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
- }
- CASE (0_112, 3) :
- {
- static const DECODE_DESC insns[16] = {
- { I (INSN_REMO1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_DIVO1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 6) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
- }
- CASE (0_112, 5) :
- {
- static const DECODE_DESC insns[16] = {
- { I (INSN_REMO2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_DIVO2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 6) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
- }
- CASE (0_112, 7) :
- {
- static const DECODE_DESC insns[16] = {
- { I (INSN_REMO3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_DIVO3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 6) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
- }
- DEFAULT (0_112) :
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 0 : itype = I960BASE_INSN_REMO2; goto extract_fmt_mulo2;
+ case 6 : itype = I960BASE_INSN_DIVO2; goto extract_fmt_mulo2;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- ENDSWITCH (0_112)
+ }
+ case 6 : itype = I960BASE_INSN_MULO3; goto extract_fmt_mulo3;
+ case 7 :
+ {
+ unsigned int val = (((insn >> 6) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : itype = I960BASE_INSN_REMO3; goto extract_fmt_mulo3;
+ case 6 : itype = I960BASE_INSN_DIVO3; goto extract_fmt_mulo3;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
+ }
+ }
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- CASE (0, 116) :
+ }
+ case 116 :
+ {
+ unsigned int val = (((insn >> 10) & (15 << 0)));
+ switch (val)
{
-#ifdef __GNUC__
- static const void *labels_0_116[16] = {
- && default_0_116, && case_0_116_1, && default_0_116, && case_0_116_3,
- && default_0_116, && case_0_116_5, && default_0_116, && case_0_116_7,
- && default_0_116, && default_0_116, && default_0_116, && default_0_116,
- && default_0_116, && default_0_116, && default_0_116, && default_0_116,
- };
-#endif
- static const DECODE_DESC insns[16] = {
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { 0 },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { 0 },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { 0 },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { 0 },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val;
- val = (((insn >> 10) & (15 << 0)));
- DECODE_SWITCH (0_116, val)
+ case 1 :
+ {
+ unsigned int val = (((insn >> 6) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : itype = I960BASE_INSN_REMI; goto extract_fmt_mulo;
+ case 6 : itype = I960BASE_INSN_DIVI; goto extract_fmt_mulo;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
+ }
+ }
+ case 3 :
+ {
+ unsigned int val = (((insn >> 6) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : itype = I960BASE_INSN_REMI1; goto extract_fmt_mulo1;
+ case 6 : itype = I960BASE_INSN_DIVI1; goto extract_fmt_mulo1;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
+ }
+ }
+ case 5 :
+ {
+ unsigned int val = (((insn >> 6) & (15 << 0)));
+ switch (val)
{
- CASE (0_116, 1) :
- {
- static const DECODE_DESC insns[16] = {
- { I (INSN_REMI), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_DIVI), E (FMT_MULO) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 6) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
- }
- CASE (0_116, 3) :
- {
- static const DECODE_DESC insns[16] = {
- { I (INSN_REMI1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_DIVI1), E (FMT_MULO1) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 6) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
- }
- CASE (0_116, 5) :
- {
- static const DECODE_DESC insns[16] = {
- { I (INSN_REMI2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_DIVI2), E (FMT_MULO2) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 6) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
- }
- CASE (0_116, 7) :
- {
- static const DECODE_DESC insns[16] = {
- { I (INSN_REMI3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_DIVI3), E (FMT_MULO3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 6) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
- }
- DEFAULT (0_116) :
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 0 : itype = I960BASE_INSN_REMI2; goto extract_fmt_mulo2;
+ case 6 : itype = I960BASE_INSN_DIVI2; goto extract_fmt_mulo2;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- ENDSWITCH (0_116)
+ }
+ case 7 :
+ {
+ unsigned int val = (((insn >> 6) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : itype = I960BASE_INSN_REMI3; goto extract_fmt_mulo3;
+ case 6 : itype = I960BASE_INSN_DIVI3; goto extract_fmt_mulo3;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
+ }
+ }
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- CASE (0, 128) :
+ }
+ case 128 :
+ {
+ unsigned int val = (((insn >> 10) & (15 << 0)));
+ switch (val)
{
- static const DECODE_DESC insns[16] = {
- { I (INSN_LDOB_OFFSET), E (FMT_LDOB_OFFSET) }, { I (INSN_LDOB_OFFSET), E (FMT_LDOB_OFFSET) },
- { I (INSN_LDOB_OFFSET), E (FMT_LDOB_OFFSET) }, { I (INSN_LDOB_OFFSET), E (FMT_LDOB_OFFSET) },
- { I (INSN_LDOB_INDIRECT), E (FMT_LDOB_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LDOB_INDIRECT_INDEX), E (FMT_LDOB_INDIRECT_INDEX) },
- { I (INSN_LDOB_INDIRECT_OFFSET), E (FMT_LDOB_INDIRECT_OFFSET) }, { I (INSN_LDOB_INDIRECT_OFFSET), E (FMT_LDOB_INDIRECT_OFFSET) },
- { I (INSN_LDOB_INDIRECT_OFFSET), E (FMT_LDOB_INDIRECT_OFFSET) }, { I (INSN_LDOB_INDIRECT_OFFSET), E (FMT_LDOB_INDIRECT_OFFSET) },
- { I (INSN_LDOB_DISP), E (FMT_LDOB_DISP) }, { I (INSN_LDOB_INDIRECT_DISP), E (FMT_LDOB_INDIRECT_DISP) },
- { I (INSN_LDOB_INDEX_DISP), E (FMT_LDOB_INDEX_DISP) }, { I (INSN_LDOB_INDIRECT_INDEX_DISP), E (FMT_LDOB_INDIRECT_INDEX_DISP) },
- };
- unsigned int val = (((insn >> 10) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : itype = I960BASE_INSN_LDOB_OFFSET; goto extract_fmt_ldob_offset;
+ case 4 : itype = I960BASE_INSN_LDOB_INDIRECT; goto extract_fmt_ldob_indirect;
+ case 7 : itype = I960BASE_INSN_LDOB_INDIRECT_INDEX; goto extract_fmt_ldob_indirect_index;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : itype = I960BASE_INSN_LDOB_INDIRECT_OFFSET; goto extract_fmt_ldob_indirect_offset;
+ case 12 : itype = I960BASE_INSN_LDOB_DISP; goto extract_fmt_ldob_disp;
+ case 13 : itype = I960BASE_INSN_LDOB_INDIRECT_DISP; goto extract_fmt_ldob_indirect_disp;
+ case 14 : itype = I960BASE_INSN_LDOB_INDEX_DISP; goto extract_fmt_ldob_index_disp;
+ case 15 : itype = I960BASE_INSN_LDOB_INDIRECT_INDEX_DISP; goto extract_fmt_ldob_indirect_index_disp;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- CASE (0, 130) :
+ }
+ case 130 :
+ {
+ unsigned int val = (((insn >> 10) & (15 << 0)));
+ switch (val)
{
- static const DECODE_DESC insns[16] = {
- { I (INSN_STOB_OFFSET), E (FMT_STOB_OFFSET) }, { I (INSN_STOB_OFFSET), E (FMT_STOB_OFFSET) },
- { I (INSN_STOB_OFFSET), E (FMT_STOB_OFFSET) }, { I (INSN_STOB_OFFSET), E (FMT_STOB_OFFSET) },
- { I (INSN_STOB_INDIRECT), E (FMT_STOB_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_STOB_INDIRECT_INDEX), E (FMT_STOB_INDIRECT_INDEX) },
- { I (INSN_STOB_INDIRECT_OFFSET), E (FMT_STOB_INDIRECT_OFFSET) }, { I (INSN_STOB_INDIRECT_OFFSET), E (FMT_STOB_INDIRECT_OFFSET) },
- { I (INSN_STOB_INDIRECT_OFFSET), E (FMT_STOB_INDIRECT_OFFSET) }, { I (INSN_STOB_INDIRECT_OFFSET), E (FMT_STOB_INDIRECT_OFFSET) },
- { I (INSN_STOB_DISP), E (FMT_STOB_DISP) }, { I (INSN_STOB_INDIRECT_DISP), E (FMT_STOB_INDIRECT_DISP) },
- { I (INSN_STOB_INDEX_DISP), E (FMT_STOB_INDEX_DISP) }, { I (INSN_STOB_INDIRECT_INDEX_DISP), E (FMT_STOB_INDIRECT_INDEX_DISP) },
- };
- unsigned int val = (((insn >> 10) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : itype = I960BASE_INSN_STOB_OFFSET; goto extract_fmt_stob_offset;
+ case 4 : itype = I960BASE_INSN_STOB_INDIRECT; goto extract_fmt_stob_indirect;
+ case 7 : itype = I960BASE_INSN_STOB_INDIRECT_INDEX; goto extract_fmt_stob_indirect_index;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : itype = I960BASE_INSN_STOB_INDIRECT_OFFSET; goto extract_fmt_stob_indirect_offset;
+ case 12 : itype = I960BASE_INSN_STOB_DISP; goto extract_fmt_stob_disp;
+ case 13 : itype = I960BASE_INSN_STOB_INDIRECT_DISP; goto extract_fmt_stob_indirect_disp;
+ case 14 : itype = I960BASE_INSN_STOB_INDEX_DISP; goto extract_fmt_stob_index_disp;
+ case 15 : itype = I960BASE_INSN_STOB_INDIRECT_INDEX_DISP; goto extract_fmt_stob_indirect_index_disp;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- CASE (0, 132) :
+ }
+ case 132 :
+ {
+ unsigned int val = (((insn >> 10) & (15 << 0)));
+ switch (val)
{
- static const DECODE_DESC insns[16] = {
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_BX_INDIRECT), E (FMT_BX_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_BX_INDIRECT_INDEX), E (FMT_BX_INDIRECT_INDEX) },
- { I (INSN_BX_INDIRECT_OFFSET), E (FMT_BX_INDIRECT_OFFSET) }, { I (INSN_BX_INDIRECT_OFFSET), E (FMT_BX_INDIRECT_OFFSET) },
- { I (INSN_BX_INDIRECT_OFFSET), E (FMT_BX_INDIRECT_OFFSET) }, { I (INSN_BX_INDIRECT_OFFSET), E (FMT_BX_INDIRECT_OFFSET) },
- { I (INSN_BX_DISP), E (FMT_BX_DISP) }, { I (INSN_BX_INDIRECT_DISP), E (FMT_BX_INDIRECT_DISP) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 10) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 4 : itype = I960BASE_INSN_BX_INDIRECT; goto extract_fmt_bx_indirect;
+ case 7 : itype = I960BASE_INSN_BX_INDIRECT_INDEX; goto extract_fmt_bx_indirect_index;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : itype = I960BASE_INSN_BX_INDIRECT_OFFSET; goto extract_fmt_bx_indirect_offset;
+ case 12 : itype = I960BASE_INSN_BX_DISP; goto extract_fmt_bx_disp;
+ case 13 : itype = I960BASE_INSN_BX_INDIRECT_DISP; goto extract_fmt_bx_indirect_disp;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- CASE (0, 134) :
+ }
+ case 134 :
+ {
+ unsigned int val = (((insn >> 10) & (15 << 0)));
+ switch (val)
{
- static const DECODE_DESC insns[16] = {
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_CALLX_INDIRECT), E (FMT_CALLX_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_CALLX_INDIRECT_OFFSET), E (FMT_CALLX_INDIRECT_OFFSET) }, { I (INSN_CALLX_INDIRECT_OFFSET), E (FMT_CALLX_INDIRECT_OFFSET) },
- { I (INSN_CALLX_INDIRECT_OFFSET), E (FMT_CALLX_INDIRECT_OFFSET) }, { I (INSN_CALLX_INDIRECT_OFFSET), E (FMT_CALLX_INDIRECT_OFFSET) },
- { I (INSN_CALLX_DISP), E (FMT_CALLX_DISP) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- };
- unsigned int val = (((insn >> 10) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 4 : itype = I960BASE_INSN_CALLX_INDIRECT; goto extract_fmt_callx_indirect;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : itype = I960BASE_INSN_CALLX_INDIRECT_OFFSET; goto extract_fmt_callx_indirect_offset;
+ case 12 : itype = I960BASE_INSN_CALLX_DISP; goto extract_fmt_callx_disp;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- CASE (0, 136) :
+ }
+ case 136 :
+ {
+ unsigned int val = (((insn >> 10) & (15 << 0)));
+ switch (val)
{
- static const DECODE_DESC insns[16] = {
- { I (INSN_LDOS_OFFSET), E (FMT_LDOS_OFFSET) }, { I (INSN_LDOS_OFFSET), E (FMT_LDOS_OFFSET) },
- { I (INSN_LDOS_OFFSET), E (FMT_LDOS_OFFSET) }, { I (INSN_LDOS_OFFSET), E (FMT_LDOS_OFFSET) },
- { I (INSN_LDOS_INDIRECT), E (FMT_LDOS_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LDOS_INDIRECT_INDEX), E (FMT_LDOS_INDIRECT_INDEX) },
- { I (INSN_LDOS_INDIRECT_OFFSET), E (FMT_LDOS_INDIRECT_OFFSET) }, { I (INSN_LDOS_INDIRECT_OFFSET), E (FMT_LDOS_INDIRECT_OFFSET) },
- { I (INSN_LDOS_INDIRECT_OFFSET), E (FMT_LDOS_INDIRECT_OFFSET) }, { I (INSN_LDOS_INDIRECT_OFFSET), E (FMT_LDOS_INDIRECT_OFFSET) },
- { I (INSN_LDOS_DISP), E (FMT_LDOS_DISP) }, { I (INSN_LDOS_INDIRECT_DISP), E (FMT_LDOS_INDIRECT_DISP) },
- { I (INSN_LDOS_INDEX_DISP), E (FMT_LDOS_INDEX_DISP) }, { I (INSN_LDOS_INDIRECT_INDEX_DISP), E (FMT_LDOS_INDIRECT_INDEX_DISP) },
- };
- unsigned int val = (((insn >> 10) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : itype = I960BASE_INSN_LDOS_OFFSET; goto extract_fmt_ldos_offset;
+ case 4 : itype = I960BASE_INSN_LDOS_INDIRECT; goto extract_fmt_ldos_indirect;
+ case 7 : itype = I960BASE_INSN_LDOS_INDIRECT_INDEX; goto extract_fmt_ldos_indirect_index;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : itype = I960BASE_INSN_LDOS_INDIRECT_OFFSET; goto extract_fmt_ldos_indirect_offset;
+ case 12 : itype = I960BASE_INSN_LDOS_DISP; goto extract_fmt_ldos_disp;
+ case 13 : itype = I960BASE_INSN_LDOS_INDIRECT_DISP; goto extract_fmt_ldos_indirect_disp;
+ case 14 : itype = I960BASE_INSN_LDOS_INDEX_DISP; goto extract_fmt_ldos_index_disp;
+ case 15 : itype = I960BASE_INSN_LDOS_INDIRECT_INDEX_DISP; goto extract_fmt_ldos_indirect_index_disp;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- CASE (0, 138) :
+ }
+ case 138 :
+ {
+ unsigned int val = (((insn >> 10) & (15 << 0)));
+ switch (val)
{
- static const DECODE_DESC insns[16] = {
- { I (INSN_STOS_OFFSET), E (FMT_STOS_OFFSET) }, { I (INSN_STOS_OFFSET), E (FMT_STOS_OFFSET) },
- { I (INSN_STOS_OFFSET), E (FMT_STOS_OFFSET) }, { I (INSN_STOS_OFFSET), E (FMT_STOS_OFFSET) },
- { I (INSN_STOS_INDIRECT), E (FMT_STOS_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_STOS_INDIRECT_INDEX), E (FMT_STOS_INDIRECT_INDEX) },
- { I (INSN_STOS_INDIRECT_OFFSET), E (FMT_STOS_INDIRECT_OFFSET) }, { I (INSN_STOS_INDIRECT_OFFSET), E (FMT_STOS_INDIRECT_OFFSET) },
- { I (INSN_STOS_INDIRECT_OFFSET), E (FMT_STOS_INDIRECT_OFFSET) }, { I (INSN_STOS_INDIRECT_OFFSET), E (FMT_STOS_INDIRECT_OFFSET) },
- { I (INSN_STOS_DISP), E (FMT_STOS_DISP) }, { I (INSN_STOS_INDIRECT_DISP), E (FMT_STOS_INDIRECT_DISP) },
- { I (INSN_STOS_INDEX_DISP), E (FMT_STOS_INDEX_DISP) }, { I (INSN_STOS_INDIRECT_INDEX_DISP), E (FMT_STOS_INDIRECT_INDEX_DISP) },
- };
- unsigned int val = (((insn >> 10) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : itype = I960BASE_INSN_STOS_OFFSET; goto extract_fmt_stos_offset;
+ case 4 : itype = I960BASE_INSN_STOS_INDIRECT; goto extract_fmt_stos_indirect;
+ case 7 : itype = I960BASE_INSN_STOS_INDIRECT_INDEX; goto extract_fmt_stos_indirect_index;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : itype = I960BASE_INSN_STOS_INDIRECT_OFFSET; goto extract_fmt_stos_indirect_offset;
+ case 12 : itype = I960BASE_INSN_STOS_DISP; goto extract_fmt_stos_disp;
+ case 13 : itype = I960BASE_INSN_STOS_INDIRECT_DISP; goto extract_fmt_stos_indirect_disp;
+ case 14 : itype = I960BASE_INSN_STOS_INDEX_DISP; goto extract_fmt_stos_index_disp;
+ case 15 : itype = I960BASE_INSN_STOS_INDIRECT_INDEX_DISP; goto extract_fmt_stos_indirect_index_disp;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- CASE (0, 140) :
+ }
+ case 140 :
+ {
+ unsigned int val = (((insn >> 10) & (15 << 0)));
+ switch (val)
{
- static const DECODE_DESC insns[16] = {
- { I (INSN_LDA_OFFSET), E (FMT_LDA_OFFSET) }, { I (INSN_LDA_OFFSET), E (FMT_LDA_OFFSET) },
- { I (INSN_LDA_OFFSET), E (FMT_LDA_OFFSET) }, { I (INSN_LDA_OFFSET), E (FMT_LDA_OFFSET) },
- { I (INSN_LDA_INDIRECT), E (FMT_LDA_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LDA_INDIRECT_INDEX), E (FMT_LDA_INDIRECT_INDEX) },
- { I (INSN_LDA_INDIRECT_OFFSET), E (FMT_LDA_INDIRECT_OFFSET) }, { I (INSN_LDA_INDIRECT_OFFSET), E (FMT_LDA_INDIRECT_OFFSET) },
- { I (INSN_LDA_INDIRECT_OFFSET), E (FMT_LDA_INDIRECT_OFFSET) }, { I (INSN_LDA_INDIRECT_OFFSET), E (FMT_LDA_INDIRECT_OFFSET) },
- { I (INSN_LDA_DISP), E (FMT_LDA_DISP) }, { I (INSN_LDA_INDIRECT_DISP), E (FMT_LDA_INDIRECT_DISP) },
- { I (INSN_LDA_INDEX_DISP), E (FMT_LDA_INDEX_DISP) }, { I (INSN_LDA_INDIRECT_INDEX_DISP), E (FMT_LDA_INDIRECT_INDEX_DISP) },
- };
- unsigned int val = (((insn >> 10) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : itype = I960BASE_INSN_LDA_OFFSET; goto extract_fmt_lda_offset;
+ case 4 : itype = I960BASE_INSN_LDA_INDIRECT; goto extract_fmt_lda_indirect;
+ case 7 : itype = I960BASE_INSN_LDA_INDIRECT_INDEX; goto extract_fmt_lda_indirect_index;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : itype = I960BASE_INSN_LDA_INDIRECT_OFFSET; goto extract_fmt_lda_indirect_offset;
+ case 12 : itype = I960BASE_INSN_LDA_DISP; goto extract_fmt_lda_disp;
+ case 13 : itype = I960BASE_INSN_LDA_INDIRECT_DISP; goto extract_fmt_lda_indirect_disp;
+ case 14 : itype = I960BASE_INSN_LDA_INDEX_DISP; goto extract_fmt_lda_index_disp;
+ case 15 : itype = I960BASE_INSN_LDA_INDIRECT_INDEX_DISP; goto extract_fmt_lda_indirect_index_disp;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- CASE (0, 144) :
+ }
+ case 144 :
+ {
+ unsigned int val = (((insn >> 10) & (15 << 0)));
+ switch (val)
{
- static const DECODE_DESC insns[16] = {
- { I (INSN_LD_OFFSET), E (FMT_LD_OFFSET) }, { I (INSN_LD_OFFSET), E (FMT_LD_OFFSET) },
- { I (INSN_LD_OFFSET), E (FMT_LD_OFFSET) }, { I (INSN_LD_OFFSET), E (FMT_LD_OFFSET) },
- { I (INSN_LD_INDIRECT), E (FMT_LD_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LD_INDIRECT_INDEX), E (FMT_LD_INDIRECT_INDEX) },
- { I (INSN_LD_INDIRECT_OFFSET), E (FMT_LD_INDIRECT_OFFSET) }, { I (INSN_LD_INDIRECT_OFFSET), E (FMT_LD_INDIRECT_OFFSET) },
- { I (INSN_LD_INDIRECT_OFFSET), E (FMT_LD_INDIRECT_OFFSET) }, { I (INSN_LD_INDIRECT_OFFSET), E (FMT_LD_INDIRECT_OFFSET) },
- { I (INSN_LD_DISP), E (FMT_LD_DISP) }, { I (INSN_LD_INDIRECT_DISP), E (FMT_LD_INDIRECT_DISP) },
- { I (INSN_LD_INDEX_DISP), E (FMT_LD_INDEX_DISP) }, { I (INSN_LD_INDIRECT_INDEX_DISP), E (FMT_LD_INDIRECT_INDEX_DISP) },
- };
- unsigned int val = (((insn >> 10) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : itype = I960BASE_INSN_LD_OFFSET; goto extract_fmt_ld_offset;
+ case 4 : itype = I960BASE_INSN_LD_INDIRECT; goto extract_fmt_ld_indirect;
+ case 7 : itype = I960BASE_INSN_LD_INDIRECT_INDEX; goto extract_fmt_ld_indirect_index;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : itype = I960BASE_INSN_LD_INDIRECT_OFFSET; goto extract_fmt_ld_indirect_offset;
+ case 12 : itype = I960BASE_INSN_LD_DISP; goto extract_fmt_ld_disp;
+ case 13 : itype = I960BASE_INSN_LD_INDIRECT_DISP; goto extract_fmt_ld_indirect_disp;
+ case 14 : itype = I960BASE_INSN_LD_INDEX_DISP; goto extract_fmt_ld_index_disp;
+ case 15 : itype = I960BASE_INSN_LD_INDIRECT_INDEX_DISP; goto extract_fmt_ld_indirect_index_disp;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- CASE (0, 146) :
+ }
+ case 146 :
+ {
+ unsigned int val = (((insn >> 10) & (15 << 0)));
+ switch (val)
{
- static const DECODE_DESC insns[16] = {
- { I (INSN_ST_OFFSET), E (FMT_ST_OFFSET) }, { I (INSN_ST_OFFSET), E (FMT_ST_OFFSET) },
- { I (INSN_ST_OFFSET), E (FMT_ST_OFFSET) }, { I (INSN_ST_OFFSET), E (FMT_ST_OFFSET) },
- { I (INSN_ST_INDIRECT), E (FMT_ST_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_ST_INDIRECT_INDEX), E (FMT_ST_INDIRECT_INDEX) },
- { I (INSN_ST_INDIRECT_OFFSET), E (FMT_ST_INDIRECT_OFFSET) }, { I (INSN_ST_INDIRECT_OFFSET), E (FMT_ST_INDIRECT_OFFSET) },
- { I (INSN_ST_INDIRECT_OFFSET), E (FMT_ST_INDIRECT_OFFSET) }, { I (INSN_ST_INDIRECT_OFFSET), E (FMT_ST_INDIRECT_OFFSET) },
- { I (INSN_ST_DISP), E (FMT_ST_DISP) }, { I (INSN_ST_INDIRECT_DISP), E (FMT_ST_INDIRECT_DISP) },
- { I (INSN_ST_INDEX_DISP), E (FMT_ST_INDEX_DISP) }, { I (INSN_ST_INDIRECT_INDEX_DISP), E (FMT_ST_INDIRECT_INDEX_DISP) },
- };
- unsigned int val = (((insn >> 10) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : itype = I960BASE_INSN_ST_OFFSET; goto extract_fmt_st_offset;
+ case 4 : itype = I960BASE_INSN_ST_INDIRECT; goto extract_fmt_st_indirect;
+ case 7 : itype = I960BASE_INSN_ST_INDIRECT_INDEX; goto extract_fmt_st_indirect_index;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : itype = I960BASE_INSN_ST_INDIRECT_OFFSET; goto extract_fmt_st_indirect_offset;
+ case 12 : itype = I960BASE_INSN_ST_DISP; goto extract_fmt_st_disp;
+ case 13 : itype = I960BASE_INSN_ST_INDIRECT_DISP; goto extract_fmt_st_indirect_disp;
+ case 14 : itype = I960BASE_INSN_ST_INDEX_DISP; goto extract_fmt_st_index_disp;
+ case 15 : itype = I960BASE_INSN_ST_INDIRECT_INDEX_DISP; goto extract_fmt_st_indirect_index_disp;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- CASE (0, 152) :
+ }
+ case 152 :
+ {
+ unsigned int val = (((insn >> 10) & (15 << 0)));
+ switch (val)
{
- static const DECODE_DESC insns[16] = {
- { I (INSN_LDL_OFFSET), E (FMT_LDL_OFFSET) }, { I (INSN_LDL_OFFSET), E (FMT_LDL_OFFSET) },
- { I (INSN_LDL_OFFSET), E (FMT_LDL_OFFSET) }, { I (INSN_LDL_OFFSET), E (FMT_LDL_OFFSET) },
- { I (INSN_LDL_INDIRECT), E (FMT_LDL_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LDL_INDIRECT_INDEX), E (FMT_LDL_INDIRECT_INDEX) },
- { I (INSN_LDL_INDIRECT_OFFSET), E (FMT_LDL_INDIRECT_OFFSET) }, { I (INSN_LDL_INDIRECT_OFFSET), E (FMT_LDL_INDIRECT_OFFSET) },
- { I (INSN_LDL_INDIRECT_OFFSET), E (FMT_LDL_INDIRECT_OFFSET) }, { I (INSN_LDL_INDIRECT_OFFSET), E (FMT_LDL_INDIRECT_OFFSET) },
- { I (INSN_LDL_DISP), E (FMT_LDL_DISP) }, { I (INSN_LDL_INDIRECT_DISP), E (FMT_LDL_INDIRECT_DISP) },
- { I (INSN_LDL_INDEX_DISP), E (FMT_LDL_INDEX_DISP) }, { I (INSN_LDL_INDIRECT_INDEX_DISP), E (FMT_LDL_INDIRECT_INDEX_DISP) },
- };
- unsigned int val = (((insn >> 10) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : itype = I960BASE_INSN_LDL_OFFSET; goto extract_fmt_ldl_offset;
+ case 4 : itype = I960BASE_INSN_LDL_INDIRECT; goto extract_fmt_ldl_indirect;
+ case 7 : itype = I960BASE_INSN_LDL_INDIRECT_INDEX; goto extract_fmt_ldl_indirect_index;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : itype = I960BASE_INSN_LDL_INDIRECT_OFFSET; goto extract_fmt_ldl_indirect_offset;
+ case 12 : itype = I960BASE_INSN_LDL_DISP; goto extract_fmt_ldl_disp;
+ case 13 : itype = I960BASE_INSN_LDL_INDIRECT_DISP; goto extract_fmt_ldl_indirect_disp;
+ case 14 : itype = I960BASE_INSN_LDL_INDEX_DISP; goto extract_fmt_ldl_index_disp;
+ case 15 : itype = I960BASE_INSN_LDL_INDIRECT_INDEX_DISP; goto extract_fmt_ldl_indirect_index_disp;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- CASE (0, 154) :
+ }
+ case 154 :
+ {
+ unsigned int val = (((insn >> 10) & (15 << 0)));
+ switch (val)
{
- static const DECODE_DESC insns[16] = {
- { I (INSN_STL_OFFSET), E (FMT_STL_OFFSET) }, { I (INSN_STL_OFFSET), E (FMT_STL_OFFSET) },
- { I (INSN_STL_OFFSET), E (FMT_STL_OFFSET) }, { I (INSN_STL_OFFSET), E (FMT_STL_OFFSET) },
- { I (INSN_STL_INDIRECT), E (FMT_STL_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_STL_INDIRECT_INDEX), E (FMT_STL_INDIRECT_INDEX) },
- { I (INSN_STL_INDIRECT_OFFSET), E (FMT_STL_INDIRECT_OFFSET) }, { I (INSN_STL_INDIRECT_OFFSET), E (FMT_STL_INDIRECT_OFFSET) },
- { I (INSN_STL_INDIRECT_OFFSET), E (FMT_STL_INDIRECT_OFFSET) }, { I (INSN_STL_INDIRECT_OFFSET), E (FMT_STL_INDIRECT_OFFSET) },
- { I (INSN_STL_DISP), E (FMT_STL_DISP) }, { I (INSN_STL_INDIRECT_DISP), E (FMT_STL_INDIRECT_DISP) },
- { I (INSN_STL_INDEX_DISP), E (FMT_STL_INDEX_DISP) }, { I (INSN_STL_INDIRECT_INDEX_DISP), E (FMT_STL_INDIRECT_INDEX_DISP) },
- };
- unsigned int val = (((insn >> 10) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : itype = I960BASE_INSN_STL_OFFSET; goto extract_fmt_stl_offset;
+ case 4 : itype = I960BASE_INSN_STL_INDIRECT; goto extract_fmt_stl_indirect;
+ case 7 : itype = I960BASE_INSN_STL_INDIRECT_INDEX; goto extract_fmt_stl_indirect_index;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : itype = I960BASE_INSN_STL_INDIRECT_OFFSET; goto extract_fmt_stl_indirect_offset;
+ case 12 : itype = I960BASE_INSN_STL_DISP; goto extract_fmt_stl_disp;
+ case 13 : itype = I960BASE_INSN_STL_INDIRECT_DISP; goto extract_fmt_stl_indirect_disp;
+ case 14 : itype = I960BASE_INSN_STL_INDEX_DISP; goto extract_fmt_stl_index_disp;
+ case 15 : itype = I960BASE_INSN_STL_INDIRECT_INDEX_DISP; goto extract_fmt_stl_indirect_index_disp;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- CASE (0, 160) :
+ }
+ case 160 :
+ {
+ unsigned int val = (((insn >> 10) & (15 << 0)));
+ switch (val)
{
- static const DECODE_DESC insns[16] = {
- { I (INSN_LDT_OFFSET), E (FMT_LDT_OFFSET) }, { I (INSN_LDT_OFFSET), E (FMT_LDT_OFFSET) },
- { I (INSN_LDT_OFFSET), E (FMT_LDT_OFFSET) }, { I (INSN_LDT_OFFSET), E (FMT_LDT_OFFSET) },
- { I (INSN_LDT_INDIRECT), E (FMT_LDT_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LDT_INDIRECT_INDEX), E (FMT_LDT_INDIRECT_INDEX) },
- { I (INSN_LDT_INDIRECT_OFFSET), E (FMT_LDT_INDIRECT_OFFSET) }, { I (INSN_LDT_INDIRECT_OFFSET), E (FMT_LDT_INDIRECT_OFFSET) },
- { I (INSN_LDT_INDIRECT_OFFSET), E (FMT_LDT_INDIRECT_OFFSET) }, { I (INSN_LDT_INDIRECT_OFFSET), E (FMT_LDT_INDIRECT_OFFSET) },
- { I (INSN_LDT_DISP), E (FMT_LDT_DISP) }, { I (INSN_LDT_INDIRECT_DISP), E (FMT_LDT_INDIRECT_DISP) },
- { I (INSN_LDT_INDEX_DISP), E (FMT_LDT_INDEX_DISP) }, { I (INSN_LDT_INDIRECT_INDEX_DISP), E (FMT_LDT_INDIRECT_INDEX_DISP) },
- };
- unsigned int val = (((insn >> 10) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : itype = I960BASE_INSN_LDT_OFFSET; goto extract_fmt_ldt_offset;
+ case 4 : itype = I960BASE_INSN_LDT_INDIRECT; goto extract_fmt_ldt_indirect;
+ case 7 : itype = I960BASE_INSN_LDT_INDIRECT_INDEX; goto extract_fmt_ldt_indirect_index;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : itype = I960BASE_INSN_LDT_INDIRECT_OFFSET; goto extract_fmt_ldt_indirect_offset;
+ case 12 : itype = I960BASE_INSN_LDT_DISP; goto extract_fmt_ldt_disp;
+ case 13 : itype = I960BASE_INSN_LDT_INDIRECT_DISP; goto extract_fmt_ldt_indirect_disp;
+ case 14 : itype = I960BASE_INSN_LDT_INDEX_DISP; goto extract_fmt_ldt_index_disp;
+ case 15 : itype = I960BASE_INSN_LDT_INDIRECT_INDEX_DISP; goto extract_fmt_ldt_indirect_index_disp;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- CASE (0, 162) :
+ }
+ case 162 :
+ {
+ unsigned int val = (((insn >> 10) & (15 << 0)));
+ switch (val)
{
- static const DECODE_DESC insns[16] = {
- { I (INSN_STT_OFFSET), E (FMT_STT_OFFSET) }, { I (INSN_STT_OFFSET), E (FMT_STT_OFFSET) },
- { I (INSN_STT_OFFSET), E (FMT_STT_OFFSET) }, { I (INSN_STT_OFFSET), E (FMT_STT_OFFSET) },
- { I (INSN_STT_INDIRECT), E (FMT_STT_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_STT_INDIRECT_INDEX), E (FMT_STT_INDIRECT_INDEX) },
- { I (INSN_STT_INDIRECT_OFFSET), E (FMT_STT_INDIRECT_OFFSET) }, { I (INSN_STT_INDIRECT_OFFSET), E (FMT_STT_INDIRECT_OFFSET) },
- { I (INSN_STT_INDIRECT_OFFSET), E (FMT_STT_INDIRECT_OFFSET) }, { I (INSN_STT_INDIRECT_OFFSET), E (FMT_STT_INDIRECT_OFFSET) },
- { I (INSN_STT_DISP), E (FMT_STT_DISP) }, { I (INSN_STT_INDIRECT_DISP), E (FMT_STT_INDIRECT_DISP) },
- { I (INSN_STT_INDEX_DISP), E (FMT_STT_INDEX_DISP) }, { I (INSN_STT_INDIRECT_INDEX_DISP), E (FMT_STT_INDIRECT_INDEX_DISP) },
- };
- unsigned int val = (((insn >> 10) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : itype = I960BASE_INSN_STT_OFFSET; goto extract_fmt_stt_offset;
+ case 4 : itype = I960BASE_INSN_STT_INDIRECT; goto extract_fmt_stt_indirect;
+ case 7 : itype = I960BASE_INSN_STT_INDIRECT_INDEX; goto extract_fmt_stt_indirect_index;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : itype = I960BASE_INSN_STT_INDIRECT_OFFSET; goto extract_fmt_stt_indirect_offset;
+ case 12 : itype = I960BASE_INSN_STT_DISP; goto extract_fmt_stt_disp;
+ case 13 : itype = I960BASE_INSN_STT_INDIRECT_DISP; goto extract_fmt_stt_indirect_disp;
+ case 14 : itype = I960BASE_INSN_STT_INDEX_DISP; goto extract_fmt_stt_index_disp;
+ case 15 : itype = I960BASE_INSN_STT_INDIRECT_INDEX_DISP; goto extract_fmt_stt_indirect_index_disp;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- CASE (0, 176) :
+ }
+ case 176 :
+ {
+ unsigned int val = (((insn >> 10) & (15 << 0)));
+ switch (val)
{
- static const DECODE_DESC insns[16] = {
- { I (INSN_LDQ_OFFSET), E (FMT_LDQ_OFFSET) }, { I (INSN_LDQ_OFFSET), E (FMT_LDQ_OFFSET) },
- { I (INSN_LDQ_OFFSET), E (FMT_LDQ_OFFSET) }, { I (INSN_LDQ_OFFSET), E (FMT_LDQ_OFFSET) },
- { I (INSN_LDQ_INDIRECT), E (FMT_LDQ_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LDQ_INDIRECT_INDEX), E (FMT_LDQ_INDIRECT_INDEX) },
- { I (INSN_LDQ_INDIRECT_OFFSET), E (FMT_LDQ_INDIRECT_OFFSET) }, { I (INSN_LDQ_INDIRECT_OFFSET), E (FMT_LDQ_INDIRECT_OFFSET) },
- { I (INSN_LDQ_INDIRECT_OFFSET), E (FMT_LDQ_INDIRECT_OFFSET) }, { I (INSN_LDQ_INDIRECT_OFFSET), E (FMT_LDQ_INDIRECT_OFFSET) },
- { I (INSN_LDQ_DISP), E (FMT_LDQ_DISP) }, { I (INSN_LDQ_INDIRECT_DISP), E (FMT_LDQ_INDIRECT_DISP) },
- { I (INSN_LDQ_INDEX_DISP), E (FMT_LDQ_INDEX_DISP) }, { I (INSN_LDQ_INDIRECT_INDEX_DISP), E (FMT_LDQ_INDIRECT_INDEX_DISP) },
- };
- unsigned int val = (((insn >> 10) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : itype = I960BASE_INSN_LDQ_OFFSET; goto extract_fmt_ldq_offset;
+ case 4 : itype = I960BASE_INSN_LDQ_INDIRECT; goto extract_fmt_ldq_indirect;
+ case 7 : itype = I960BASE_INSN_LDQ_INDIRECT_INDEX; goto extract_fmt_ldq_indirect_index;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : itype = I960BASE_INSN_LDQ_INDIRECT_OFFSET; goto extract_fmt_ldq_indirect_offset;
+ case 12 : itype = I960BASE_INSN_LDQ_DISP; goto extract_fmt_ldq_disp;
+ case 13 : itype = I960BASE_INSN_LDQ_INDIRECT_DISP; goto extract_fmt_ldq_indirect_disp;
+ case 14 : itype = I960BASE_INSN_LDQ_INDEX_DISP; goto extract_fmt_ldq_index_disp;
+ case 15 : itype = I960BASE_INSN_LDQ_INDIRECT_INDEX_DISP; goto extract_fmt_ldq_indirect_index_disp;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- CASE (0, 178) :
+ }
+ case 178 :
+ {
+ unsigned int val = (((insn >> 10) & (15 << 0)));
+ switch (val)
{
- static const DECODE_DESC insns[16] = {
- { I (INSN_STQ_OFFSET), E (FMT_STQ_OFFSET) }, { I (INSN_STQ_OFFSET), E (FMT_STQ_OFFSET) },
- { I (INSN_STQ_OFFSET), E (FMT_STQ_OFFSET) }, { I (INSN_STQ_OFFSET), E (FMT_STQ_OFFSET) },
- { I (INSN_STQ_INDIRECT), E (FMT_STQ_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_STQ_INDIRECT_INDEX), E (FMT_STQ_INDIRECT_INDEX) },
- { I (INSN_STQ_INDIRECT_OFFSET), E (FMT_STQ_INDIRECT_OFFSET) }, { I (INSN_STQ_INDIRECT_OFFSET), E (FMT_STQ_INDIRECT_OFFSET) },
- { I (INSN_STQ_INDIRECT_OFFSET), E (FMT_STQ_INDIRECT_OFFSET) }, { I (INSN_STQ_INDIRECT_OFFSET), E (FMT_STQ_INDIRECT_OFFSET) },
- { I (INSN_STQ_DISP), E (FMT_STQ_DISP) }, { I (INSN_STQ_INDIRECT_DISP), E (FMT_STQ_INDIRECT_DISP) },
- { I (INSN_STQ_INDEX_DISP), E (FMT_STQ_INDEX_DISP) }, { I (INSN_STQ_INDIRECT_INDEX_DISP), E (FMT_STQ_INDIRECT_INDEX_DISP) },
- };
- unsigned int val = (((insn >> 10) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : itype = I960BASE_INSN_STQ_OFFSET; goto extract_fmt_stq_offset;
+ case 4 : itype = I960BASE_INSN_STQ_INDIRECT; goto extract_fmt_stq_indirect;
+ case 7 : itype = I960BASE_INSN_STQ_INDIRECT_INDEX; goto extract_fmt_stq_indirect_index;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : itype = I960BASE_INSN_STQ_INDIRECT_OFFSET; goto extract_fmt_stq_indirect_offset;
+ case 12 : itype = I960BASE_INSN_STQ_DISP; goto extract_fmt_stq_disp;
+ case 13 : itype = I960BASE_INSN_STQ_INDIRECT_DISP; goto extract_fmt_stq_indirect_disp;
+ case 14 : itype = I960BASE_INSN_STQ_INDEX_DISP; goto extract_fmt_stq_index_disp;
+ case 15 : itype = I960BASE_INSN_STQ_INDIRECT_INDEX_DISP; goto extract_fmt_stq_indirect_index_disp;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- CASE (0, 192) :
+ }
+ case 192 :
+ {
+ unsigned int val = (((insn >> 10) & (15 << 0)));
+ switch (val)
{
- static const DECODE_DESC insns[16] = {
- { I (INSN_LDIB_OFFSET), E (FMT_LDIB_OFFSET) }, { I (INSN_LDIB_OFFSET), E (FMT_LDIB_OFFSET) },
- { I (INSN_LDIB_OFFSET), E (FMT_LDIB_OFFSET) }, { I (INSN_LDIB_OFFSET), E (FMT_LDIB_OFFSET) },
- { I (INSN_LDIB_INDIRECT), E (FMT_LDIB_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LDIB_INDIRECT_INDEX), E (FMT_LDIB_INDIRECT_INDEX) },
- { I (INSN_LDIB_INDIRECT_OFFSET), E (FMT_LDIB_INDIRECT_OFFSET) }, { I (INSN_LDIB_INDIRECT_OFFSET), E (FMT_LDIB_INDIRECT_OFFSET) },
- { I (INSN_LDIB_INDIRECT_OFFSET), E (FMT_LDIB_INDIRECT_OFFSET) }, { I (INSN_LDIB_INDIRECT_OFFSET), E (FMT_LDIB_INDIRECT_OFFSET) },
- { I (INSN_LDIB_DISP), E (FMT_LDIB_DISP) }, { I (INSN_LDIB_INDIRECT_DISP), E (FMT_LDIB_INDIRECT_DISP) },
- { I (INSN_LDIB_INDEX_DISP), E (FMT_LDIB_INDEX_DISP) }, { I (INSN_LDIB_INDIRECT_INDEX_DISP), E (FMT_LDIB_INDIRECT_INDEX_DISP) },
- };
- unsigned int val = (((insn >> 10) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : itype = I960BASE_INSN_LDIB_OFFSET; goto extract_fmt_ldib_offset;
+ case 4 : itype = I960BASE_INSN_LDIB_INDIRECT; goto extract_fmt_ldib_indirect;
+ case 7 : itype = I960BASE_INSN_LDIB_INDIRECT_INDEX; goto extract_fmt_ldib_indirect_index;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : itype = I960BASE_INSN_LDIB_INDIRECT_OFFSET; goto extract_fmt_ldib_indirect_offset;
+ case 12 : itype = I960BASE_INSN_LDIB_DISP; goto extract_fmt_ldib_disp;
+ case 13 : itype = I960BASE_INSN_LDIB_INDIRECT_DISP; goto extract_fmt_ldib_indirect_disp;
+ case 14 : itype = I960BASE_INSN_LDIB_INDEX_DISP; goto extract_fmt_ldib_index_disp;
+ case 15 : itype = I960BASE_INSN_LDIB_INDIRECT_INDEX_DISP; goto extract_fmt_ldib_indirect_index_disp;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- CASE (0, 200) :
+ }
+ case 200 :
+ {
+ unsigned int val = (((insn >> 10) & (15 << 0)));
+ switch (val)
{
- static const DECODE_DESC insns[16] = {
- { I (INSN_LDIS_OFFSET), E (FMT_LDIS_OFFSET) }, { I (INSN_LDIS_OFFSET), E (FMT_LDIS_OFFSET) },
- { I (INSN_LDIS_OFFSET), E (FMT_LDIS_OFFSET) }, { I (INSN_LDIS_OFFSET), E (FMT_LDIS_OFFSET) },
- { I (INSN_LDIS_INDIRECT), E (FMT_LDIS_INDIRECT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
- { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LDIS_INDIRECT_INDEX), E (FMT_LDIS_INDIRECT_INDEX) },
- { I (INSN_LDIS_INDIRECT_OFFSET), E (FMT_LDIS_INDIRECT_OFFSET) }, { I (INSN_LDIS_INDIRECT_OFFSET), E (FMT_LDIS_INDIRECT_OFFSET) },
- { I (INSN_LDIS_INDIRECT_OFFSET), E (FMT_LDIS_INDIRECT_OFFSET) }, { I (INSN_LDIS_INDIRECT_OFFSET), E (FMT_LDIS_INDIRECT_OFFSET) },
- { I (INSN_LDIS_DISP), E (FMT_LDIS_DISP) }, { I (INSN_LDIS_INDIRECT_DISP), E (FMT_LDIS_INDIRECT_DISP) },
- { I (INSN_LDIS_INDEX_DISP), E (FMT_LDIS_INDEX_DISP) }, { I (INSN_LDIS_INDIRECT_INDEX_DISP), E (FMT_LDIS_INDIRECT_INDEX_DISP) },
- };
- unsigned int val = (((insn >> 10) & (15 << 0)));
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : itype = I960BASE_INSN_LDIS_OFFSET; goto extract_fmt_ldis_offset;
+ case 4 : itype = I960BASE_INSN_LDIS_INDIRECT; goto extract_fmt_ldis_indirect;
+ case 7 : itype = I960BASE_INSN_LDIS_INDIRECT_INDEX; goto extract_fmt_ldis_indirect_index;
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : itype = I960BASE_INSN_LDIS_INDIRECT_OFFSET; goto extract_fmt_ldis_indirect_offset;
+ case 12 : itype = I960BASE_INSN_LDIS_DISP; goto extract_fmt_ldis_disp;
+ case 13 : itype = I960BASE_INSN_LDIS_INDIRECT_DISP; goto extract_fmt_ldis_indirect_disp;
+ case 14 : itype = I960BASE_INSN_LDIS_INDEX_DISP; goto extract_fmt_ldis_index_disp;
+ case 15 : itype = I960BASE_INSN_LDIS_INDIRECT_INDEX_DISP; goto extract_fmt_ldis_indirect_index_disp;
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
}
- DEFAULT (0) :
- idecode = &insns[val];
- GOTO_EXTRACT (idecode);
}
- ENDSWITCH (0)
+ default : itype = I960BASE_INSN_X_INVALID; goto extract_fmt_empty;
+ }
}
-#undef I
-#undef E
}
/* The instruction has been decoded, now extract the fields. */
- extract:
- {
-#ifndef __GNUC__
- switch (idecode->sfmt)
-#endif
- {
-
- CASE (ex, FMT_EMPTY) :
+ extract_fmt_empty:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_empty.f
EXTRACT_IFMT_EMPTY_VARS /* */
@@ -1914,11 +1423,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_empty", (char *) 0));
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_MULO) :
+ extract_fmt_mulo:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_mulo.f
EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
@@ -1941,11 +1451,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_MULO1) :
+ extract_fmt_mulo1:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_mulo1.f
EXTRACT_IFMT_MULO1_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
@@ -1967,11 +1478,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_MULO2) :
+ extract_fmt_mulo2:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_mulo2.f
EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
@@ -1993,11 +1505,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_MULO3) :
+ extract_fmt_mulo3:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_mulo3.f
EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
@@ -2018,11 +1531,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_NOTBIT) :
+ extract_fmt_notbit:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_notbit.f
EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
@@ -2045,11 +1559,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_NOTBIT1) :
+ extract_fmt_notbit1:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_notbit1.f
EXTRACT_IFMT_MULO1_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
@@ -2071,11 +1586,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_NOTBIT2) :
+ extract_fmt_notbit2:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_notbit2.f
EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
@@ -2097,11 +1613,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_NOTBIT3) :
+ extract_fmt_notbit3:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_notbit3.f
EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
@@ -2122,11 +1639,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_NOT) :
+ extract_fmt_not:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_not.f
EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
@@ -2147,11 +1665,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_NOT1) :
+ extract_fmt_not1:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_not1.f
EXTRACT_IFMT_MULO1_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
@@ -2171,11 +1690,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_NOT2) :
+ extract_fmt_not2:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_not2.f
EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
@@ -2196,11 +1716,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_NOT3) :
+ extract_fmt_not3:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_not3.f
EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
@@ -2220,11 +1741,120 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
+ }
+
+ extract_fmt_shlo:
+ {
+ const IDESC *idesc = &i960base_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_shlo.f
+ EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
+
+ EXTRACT_IFMT_MULO_CODE
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_src1) = & CPU (h_gr)[f_src1];
+ FLD (i_src2) = & CPU (h_gr)[f_src2];
+ FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_shlo", "src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_src1) = f_src1;
+ FLD (in_src2) = f_src2;
+ FLD (out_dst) = f_srcdst;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_fmt_shlo1:
+ {
+ const IDESC *idesc = &i960base_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_shlo1.f
+ EXTRACT_IFMT_MULO1_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
+
+ EXTRACT_IFMT_MULO1_CODE
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_src1) = f_src1;
+ FLD (i_src2) = & CPU (h_gr)[f_src2];
+ FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_shlo1", "f_src1 0x%x", 'x', f_src1, "src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_src2) = f_src2;
+ FLD (out_dst) = f_srcdst;
+ }
+#endif
+#undef FLD
+ return idesc;
}
- CASE (ex, FMT_EMUL) :
+ extract_fmt_shlo2:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_shlo2.f
+ EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
+
+ EXTRACT_IFMT_MULO2_CODE
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_src2) = f_src2;
+ FLD (i_src1) = & CPU (h_gr)[f_src1];
+ FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_shlo2", "f_src2 0x%x", 'x', f_src2, "src1 0x%x", 'x', f_src1, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_src1) = f_src1;
+ FLD (out_dst) = f_srcdst;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_fmt_shlo3:
+ {
+ const IDESC *idesc = &i960base_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.fmt_shlo3.f
+ EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
+
+ EXTRACT_IFMT_MULO3_CODE
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_src1) = f_src1;
+ FLD (f_src2) = f_src2;
+ FLD (i_dst) = & CPU (h_gr)[f_srcdst];
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_shlo3", "f_src1 0x%x", 'x', f_src1, "f_src2 0x%x", 'x', f_src2, "dst 0x%x", 'x', f_srcdst, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (out_dst) = f_srcdst;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_fmt_emul:
+ {
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_emul.f
EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
@@ -2245,15 +1875,16 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
FLD (in_src1) = f_src1;
FLD (in_src2) = f_src2;
FLD (out_dst) = f_srcdst;
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+ FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1));
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_EMUL1) :
+ extract_fmt_emul1:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_emul1.f
EXTRACT_IFMT_MULO1_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
@@ -2273,15 +1904,16 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
{
FLD (in_src2) = f_src2;
FLD (out_dst) = f_srcdst;
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+ FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1));
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_EMUL2) :
+ extract_fmt_emul2:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_emul2.f
EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
@@ -2301,15 +1933,16 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
{
FLD (in_src1) = f_src1;
FLD (out_dst) = f_srcdst;
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+ FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1));
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_EMUL3) :
+ extract_fmt_emul3:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_emul3.f
EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
@@ -2328,15 +1961,16 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
if (PROFILE_MODEL_P (current_cpu))
{
FLD (out_dst) = f_srcdst;
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+ FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1));
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_MOVL) :
+ extract_fmt_movl:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_movl.f
EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
@@ -2354,18 +1988,19 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
/* Record the fields for profiling. */
if (PROFILE_MODEL_P (current_cpu))
{
- FLD (in_h_gr_add__VM_index_of_src1_const__WI_1) = ((FLD (f_src1)) + (1));
+ FLD (in_h_gr_add__VM_index_of_src1_1) = ((FLD (f_src1)) + (1));
FLD (in_src1) = f_src1;
FLD (out_dst) = f_srcdst;
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+ FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1));
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_MOVL1) :
+ extract_fmt_movl1:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_movl1.f
EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
@@ -2383,15 +2018,16 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
if (PROFILE_MODEL_P (current_cpu))
{
FLD (out_dst) = f_srcdst;
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+ FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1));
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_MOVT) :
+ extract_fmt_movt:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_movt.f
EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
@@ -2409,20 +2045,21 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
/* Record the fields for profiling. */
if (PROFILE_MODEL_P (current_cpu))
{
- FLD (in_h_gr_add__VM_index_of_src1_const__WI_1) = ((FLD (f_src1)) + (1));
- FLD (in_h_gr_add__VM_index_of_src1_const__WI_2) = ((FLD (f_src1)) + (2));
+ FLD (in_h_gr_add__VM_index_of_src1_1) = ((FLD (f_src1)) + (1));
+ FLD (in_h_gr_add__VM_index_of_src1_2) = ((FLD (f_src1)) + (2));
FLD (in_src1) = f_src1;
FLD (out_dst) = f_srcdst;
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2));
+ FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1));
+ FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2));
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_MOVT1) :
+ extract_fmt_movt1:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_movt1.f
EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
@@ -2440,16 +2077,17 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
if (PROFILE_MODEL_P (current_cpu))
{
FLD (out_dst) = f_srcdst;
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2));
+ FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1));
+ FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2));
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_MOVQ) :
+ extract_fmt_movq:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_movq.f
EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
@@ -2467,22 +2105,23 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
/* Record the fields for profiling. */
if (PROFILE_MODEL_P (current_cpu))
{
- FLD (in_h_gr_add__VM_index_of_src1_const__WI_1) = ((FLD (f_src1)) + (1));
- FLD (in_h_gr_add__VM_index_of_src1_const__WI_2) = ((FLD (f_src1)) + (2));
- FLD (in_h_gr_add__VM_index_of_src1_const__WI_3) = ((FLD (f_src1)) + (3));
+ FLD (in_h_gr_add__VM_index_of_src1_1) = ((FLD (f_src1)) + (1));
+ FLD (in_h_gr_add__VM_index_of_src1_2) = ((FLD (f_src1)) + (2));
+ FLD (in_h_gr_add__VM_index_of_src1_3) = ((FLD (f_src1)) + (3));
FLD (in_src1) = f_src1;
FLD (out_dst) = f_srcdst;
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2));
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_3) = ((FLD (f_srcdst)) + (3));
+ FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1));
+ FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2));
+ FLD (out_h_gr_add__VM_index_of_dst_3) = ((FLD (f_srcdst)) + (3));
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_MOVQ1) :
+ extract_fmt_movq1:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_movq1.f
EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
@@ -2500,17 +2139,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
if (PROFILE_MODEL_P (current_cpu))
{
FLD (out_dst) = f_srcdst;
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2));
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_3) = ((FLD (f_srcdst)) + (3));
+ FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1));
+ FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2));
+ FLD (out_h_gr_add__VM_index_of_dst_3) = ((FLD (f_srcdst)) + (3));
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_MODPC) :
+ extract_fmt_modpc:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_modpc.f
EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
@@ -2531,11 +2171,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDA_OFFSET) :
+ extract_fmt_lda_offset:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_lda_offset.f
EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
@@ -2555,11 +2196,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDA_INDIRECT_OFFSET) :
+ extract_fmt_lda_indirect_offset:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_lda_indirect_offset.f
EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
@@ -2581,11 +2223,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDA_INDIRECT) :
+ extract_fmt_lda_indirect:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_lda_indirect.f
EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -2606,11 +2249,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDA_INDIRECT_INDEX) :
+ extract_fmt_lda_indirect_index:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_lda_indirect_index.f
EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -2634,11 +2278,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDA_DISP) :
+ extract_fmt_lda_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_lda_disp.f
EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -2658,11 +2303,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDA_INDIRECT_DISP) :
+ extract_fmt_lda_indirect_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_lda_indirect_disp.f
EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -2684,11 +2330,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDA_INDEX_DISP) :
+ extract_fmt_lda_index_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_lda_index_disp.f
EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -2711,11 +2358,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDA_INDIRECT_INDEX_DISP) :
+ extract_fmt_lda_indirect_index_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_lda_indirect_index_disp.f
EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -2740,11 +2388,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LD_OFFSET) :
+ extract_fmt_ld_offset:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ld_offset.f
EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
@@ -2764,11 +2413,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LD_INDIRECT_OFFSET) :
+ extract_fmt_ld_indirect_offset:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ld_indirect_offset.f
EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
@@ -2790,11 +2440,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LD_INDIRECT) :
+ extract_fmt_ld_indirect:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ld_indirect.f
EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -2815,11 +2466,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LD_INDIRECT_INDEX) :
+ extract_fmt_ld_indirect_index:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ld_indirect_index.f
EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -2843,11 +2495,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LD_DISP) :
+ extract_fmt_ld_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ld_disp.f
EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -2867,11 +2520,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LD_INDIRECT_DISP) :
+ extract_fmt_ld_indirect_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ld_indirect_disp.f
EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -2893,11 +2547,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LD_INDEX_DISP) :
+ extract_fmt_ld_index_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ld_index_disp.f
EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -2920,11 +2575,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LD_INDIRECT_INDEX_DISP) :
+ extract_fmt_ld_indirect_index_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ld_indirect_index_disp.f
EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -2949,11 +2605,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDOB_OFFSET) :
+ extract_fmt_ldob_offset:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldob_offset.f
EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
@@ -2973,11 +2630,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDOB_INDIRECT_OFFSET) :
+ extract_fmt_ldob_indirect_offset:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldob_indirect_offset.f
EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
@@ -2999,11 +2657,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDOB_INDIRECT) :
+ extract_fmt_ldob_indirect:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldob_indirect.f
EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -3024,11 +2683,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDOB_INDIRECT_INDEX) :
+ extract_fmt_ldob_indirect_index:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldob_indirect_index.f
EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -3052,11 +2712,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDOB_DISP) :
+ extract_fmt_ldob_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldob_disp.f
EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -3076,11 +2737,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDOB_INDIRECT_DISP) :
+ extract_fmt_ldob_indirect_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldob_indirect_disp.f
EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -3102,11 +2764,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDOB_INDEX_DISP) :
+ extract_fmt_ldob_index_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldob_index_disp.f
EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -3129,11 +2792,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDOB_INDIRECT_INDEX_DISP) :
+ extract_fmt_ldob_indirect_index_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldob_indirect_index_disp.f
EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -3158,11 +2822,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDOS_OFFSET) :
+ extract_fmt_ldos_offset:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldos_offset.f
EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
@@ -3182,11 +2847,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDOS_INDIRECT_OFFSET) :
+ extract_fmt_ldos_indirect_offset:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldos_indirect_offset.f
EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
@@ -3208,11 +2874,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDOS_INDIRECT) :
+ extract_fmt_ldos_indirect:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldos_indirect.f
EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -3233,11 +2900,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDOS_INDIRECT_INDEX) :
+ extract_fmt_ldos_indirect_index:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldos_indirect_index.f
EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -3261,11 +2929,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDOS_DISP) :
+ extract_fmt_ldos_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldos_disp.f
EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -3285,11 +2954,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDOS_INDIRECT_DISP) :
+ extract_fmt_ldos_indirect_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldos_indirect_disp.f
EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -3311,11 +2981,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDOS_INDEX_DISP) :
+ extract_fmt_ldos_index_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldos_index_disp.f
EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -3338,11 +3009,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDOS_INDIRECT_INDEX_DISP) :
+ extract_fmt_ldos_indirect_index_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldos_indirect_index_disp.f
EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -3367,11 +3039,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDIB_OFFSET) :
+ extract_fmt_ldib_offset:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldib_offset.f
EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
@@ -3391,11 +3064,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDIB_INDIRECT_OFFSET) :
+ extract_fmt_ldib_indirect_offset:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldib_indirect_offset.f
EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
@@ -3417,11 +3091,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDIB_INDIRECT) :
+ extract_fmt_ldib_indirect:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldib_indirect.f
EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -3442,11 +3117,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDIB_INDIRECT_INDEX) :
+ extract_fmt_ldib_indirect_index:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldib_indirect_index.f
EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -3470,11 +3146,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDIB_DISP) :
+ extract_fmt_ldib_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldib_disp.f
EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -3494,11 +3171,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDIB_INDIRECT_DISP) :
+ extract_fmt_ldib_indirect_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldib_indirect_disp.f
EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -3520,11 +3198,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDIB_INDEX_DISP) :
+ extract_fmt_ldib_index_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldib_index_disp.f
EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -3547,11 +3226,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDIB_INDIRECT_INDEX_DISP) :
+ extract_fmt_ldib_indirect_index_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldib_indirect_index_disp.f
EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -3576,11 +3256,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDIS_OFFSET) :
+ extract_fmt_ldis_offset:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldis_offset.f
EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
@@ -3600,11 +3281,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDIS_INDIRECT_OFFSET) :
+ extract_fmt_ldis_indirect_offset:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldis_indirect_offset.f
EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
@@ -3626,11 +3308,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDIS_INDIRECT) :
+ extract_fmt_ldis_indirect:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldis_indirect.f
EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -3651,11 +3334,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDIS_INDIRECT_INDEX) :
+ extract_fmt_ldis_indirect_index:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldis_indirect_index.f
EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -3679,11 +3363,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDIS_DISP) :
+ extract_fmt_ldis_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldis_disp.f
EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -3703,11 +3388,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDIS_INDIRECT_DISP) :
+ extract_fmt_ldis_indirect_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldis_indirect_disp.f
EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -3729,11 +3415,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDIS_INDEX_DISP) :
+ extract_fmt_ldis_index_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldis_index_disp.f
EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -3756,11 +3443,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDIS_INDIRECT_INDEX_DISP) :
+ extract_fmt_ldis_indirect_index_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldis_indirect_index_disp.f
EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -3785,11 +3473,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDL_OFFSET) :
+ extract_fmt_ldl_offset:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldl_offset.f
EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
@@ -3807,15 +3496,16 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
if (PROFILE_MODEL_P (current_cpu))
{
FLD (out_dst) = f_srcdst;
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+ FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1));
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDL_INDIRECT_OFFSET) :
+ extract_fmt_ldl_indirect_offset:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldl_indirect_offset.f
EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
@@ -3835,15 +3525,16 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
{
FLD (in_abase) = f_abase;
FLD (out_dst) = f_srcdst;
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+ FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1));
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDL_INDIRECT) :
+ extract_fmt_ldl_indirect:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldl_indirect.f
EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -3862,15 +3553,16 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
{
FLD (in_abase) = f_abase;
FLD (out_dst) = f_srcdst;
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+ FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1));
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDL_INDIRECT_INDEX) :
+ extract_fmt_ldl_indirect_index:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldl_indirect_index.f
EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -3892,15 +3584,16 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
FLD (in_abase) = f_abase;
FLD (in_index) = f_index;
FLD (out_dst) = f_srcdst;
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+ FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1));
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDL_DISP) :
+ extract_fmt_ldl_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldl_disp.f
EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -3918,15 +3611,16 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
if (PROFILE_MODEL_P (current_cpu))
{
FLD (out_dst) = f_srcdst;
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+ FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1));
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDL_INDIRECT_DISP) :
+ extract_fmt_ldl_indirect_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldl_indirect_disp.f
EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -3946,15 +3640,16 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
{
FLD (in_abase) = f_abase;
FLD (out_dst) = f_srcdst;
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+ FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1));
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDL_INDEX_DISP) :
+ extract_fmt_ldl_index_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldl_index_disp.f
EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -3975,15 +3670,16 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
{
FLD (in_index) = f_index;
FLD (out_dst) = f_srcdst;
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+ FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1));
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDL_INDIRECT_INDEX_DISP) :
+ extract_fmt_ldl_indirect_index_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldl_indirect_index_disp.f
EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -4006,15 +3702,16 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
FLD (in_abase) = f_abase;
FLD (in_index) = f_index;
FLD (out_dst) = f_srcdst;
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
+ FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1));
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDT_OFFSET) :
+ extract_fmt_ldt_offset:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldt_offset.f
EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
@@ -4032,16 +3729,17 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
if (PROFILE_MODEL_P (current_cpu))
{
FLD (out_dst) = f_srcdst;
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2));
+ FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1));
+ FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2));
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDT_INDIRECT_OFFSET) :
+ extract_fmt_ldt_indirect_offset:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldt_indirect_offset.f
EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
@@ -4061,16 +3759,17 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
{
FLD (in_abase) = f_abase;
FLD (out_dst) = f_srcdst;
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2));
+ FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1));
+ FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2));
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDT_INDIRECT) :
+ extract_fmt_ldt_indirect:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldt_indirect.f
EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -4089,16 +3788,17 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
{
FLD (in_abase) = f_abase;
FLD (out_dst) = f_srcdst;
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2));
+ FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1));
+ FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2));
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDT_INDIRECT_INDEX) :
+ extract_fmt_ldt_indirect_index:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldt_indirect_index.f
EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -4120,16 +3820,17 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
FLD (in_abase) = f_abase;
FLD (in_index) = f_index;
FLD (out_dst) = f_srcdst;
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2));
+ FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1));
+ FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2));
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDT_DISP) :
+ extract_fmt_ldt_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldt_disp.f
EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -4147,16 +3848,17 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
if (PROFILE_MODEL_P (current_cpu))
{
FLD (out_dst) = f_srcdst;
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2));
+ FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1));
+ FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2));
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDT_INDIRECT_DISP) :
+ extract_fmt_ldt_indirect_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldt_indirect_disp.f
EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -4176,16 +3878,17 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
{
FLD (in_abase) = f_abase;
FLD (out_dst) = f_srcdst;
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2));
+ FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1));
+ FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2));
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDT_INDEX_DISP) :
+ extract_fmt_ldt_index_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldt_index_disp.f
EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -4206,16 +3909,17 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
{
FLD (in_index) = f_index;
FLD (out_dst) = f_srcdst;
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2));
+ FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1));
+ FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2));
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDT_INDIRECT_INDEX_DISP) :
+ extract_fmt_ldt_indirect_index_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldt_indirect_index_disp.f
EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -4238,16 +3942,17 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
FLD (in_abase) = f_abase;
FLD (in_index) = f_index;
FLD (out_dst) = f_srcdst;
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2));
+ FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1));
+ FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2));
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDQ_OFFSET) :
+ extract_fmt_ldq_offset:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldq_offset.f
EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
@@ -4265,17 +3970,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
if (PROFILE_MODEL_P (current_cpu))
{
FLD (out_dst) = f_srcdst;
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2));
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_3) = ((FLD (f_srcdst)) + (3));
+ FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1));
+ FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2));
+ FLD (out_h_gr_add__VM_index_of_dst_3) = ((FLD (f_srcdst)) + (3));
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDQ_INDIRECT_OFFSET) :
+ extract_fmt_ldq_indirect_offset:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldq_indirect_offset.f
EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
@@ -4295,17 +4001,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
{
FLD (in_abase) = f_abase;
FLD (out_dst) = f_srcdst;
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2));
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_3) = ((FLD (f_srcdst)) + (3));
+ FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1));
+ FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2));
+ FLD (out_h_gr_add__VM_index_of_dst_3) = ((FLD (f_srcdst)) + (3));
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDQ_INDIRECT) :
+ extract_fmt_ldq_indirect:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldq_indirect.f
EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -4324,17 +4031,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
{
FLD (in_abase) = f_abase;
FLD (out_dst) = f_srcdst;
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2));
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_3) = ((FLD (f_srcdst)) + (3));
+ FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1));
+ FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2));
+ FLD (out_h_gr_add__VM_index_of_dst_3) = ((FLD (f_srcdst)) + (3));
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDQ_INDIRECT_INDEX) :
+ extract_fmt_ldq_indirect_index:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldq_indirect_index.f
EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -4356,17 +4064,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
FLD (in_abase) = f_abase;
FLD (in_index) = f_index;
FLD (out_dst) = f_srcdst;
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2));
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_3) = ((FLD (f_srcdst)) + (3));
+ FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1));
+ FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2));
+ FLD (out_h_gr_add__VM_index_of_dst_3) = ((FLD (f_srcdst)) + (3));
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDQ_DISP) :
+ extract_fmt_ldq_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldq_disp.f
EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -4384,17 +4093,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
if (PROFILE_MODEL_P (current_cpu))
{
FLD (out_dst) = f_srcdst;
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2));
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_3) = ((FLD (f_srcdst)) + (3));
+ FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1));
+ FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2));
+ FLD (out_h_gr_add__VM_index_of_dst_3) = ((FLD (f_srcdst)) + (3));
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDQ_INDIRECT_DISP) :
+ extract_fmt_ldq_indirect_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldq_indirect_disp.f
EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -4414,17 +4124,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
{
FLD (in_abase) = f_abase;
FLD (out_dst) = f_srcdst;
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2));
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_3) = ((FLD (f_srcdst)) + (3));
+ FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1));
+ FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2));
+ FLD (out_h_gr_add__VM_index_of_dst_3) = ((FLD (f_srcdst)) + (3));
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDQ_INDEX_DISP) :
+ extract_fmt_ldq_index_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldq_index_disp.f
EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -4445,17 +4156,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
{
FLD (in_index) = f_index;
FLD (out_dst) = f_srcdst;
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2));
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_3) = ((FLD (f_srcdst)) + (3));
+ FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1));
+ FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2));
+ FLD (out_h_gr_add__VM_index_of_dst_3) = ((FLD (f_srcdst)) + (3));
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_LDQ_INDIRECT_INDEX_DISP) :
+ extract_fmt_ldq_indirect_index_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_ldq_indirect_index_disp.f
EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -4478,17 +4190,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
FLD (in_abase) = f_abase;
FLD (in_index) = f_index;
FLD (out_dst) = f_srcdst;
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_1) = ((FLD (f_srcdst)) + (1));
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_2) = ((FLD (f_srcdst)) + (2));
- FLD (out_h_gr_add__VM_index_of_dst_const__WI_3) = ((FLD (f_srcdst)) + (3));
+ FLD (out_h_gr_add__VM_index_of_dst_1) = ((FLD (f_srcdst)) + (1));
+ FLD (out_h_gr_add__VM_index_of_dst_2) = ((FLD (f_srcdst)) + (2));
+ FLD (out_h_gr_add__VM_index_of_dst_3) = ((FLD (f_srcdst)) + (3));
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_ST_OFFSET) :
+ extract_fmt_st_offset:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_st_offset.f
EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
@@ -4508,11 +4221,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_ST_INDIRECT_OFFSET) :
+ extract_fmt_st_indirect_offset:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_st_indirect_offset.f
EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
@@ -4534,11 +4248,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_ST_INDIRECT) :
+ extract_fmt_st_indirect:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_st_indirect.f
EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -4559,11 +4274,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_ST_INDIRECT_INDEX) :
+ extract_fmt_st_indirect_index:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_st_indirect_index.f
EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -4587,11 +4303,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_ST_DISP) :
+ extract_fmt_st_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_st_disp.f
EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -4611,11 +4328,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_ST_INDIRECT_DISP) :
+ extract_fmt_st_indirect_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_st_indirect_disp.f
EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -4637,11 +4355,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_ST_INDEX_DISP) :
+ extract_fmt_st_index_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_st_index_disp.f
EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -4664,11 +4383,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_ST_INDIRECT_INDEX_DISP) :
+ extract_fmt_st_indirect_index_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_st_indirect_index_disp.f
EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -4693,11 +4413,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_STOB_OFFSET) :
+ extract_fmt_stob_offset:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_stob_offset.f
EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
@@ -4717,11 +4438,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_STOB_INDIRECT_OFFSET) :
+ extract_fmt_stob_indirect_offset:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_stob_indirect_offset.f
EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
@@ -4743,11 +4465,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_STOB_INDIRECT) :
+ extract_fmt_stob_indirect:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_stob_indirect.f
EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -4768,11 +4491,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_STOB_INDIRECT_INDEX) :
+ extract_fmt_stob_indirect_index:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_stob_indirect_index.f
EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -4796,11 +4520,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_STOB_DISP) :
+ extract_fmt_stob_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_stob_disp.f
EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -4820,11 +4545,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_STOB_INDIRECT_DISP) :
+ extract_fmt_stob_indirect_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_stob_indirect_disp.f
EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -4846,11 +4572,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_STOB_INDEX_DISP) :
+ extract_fmt_stob_index_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_stob_index_disp.f
EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -4873,11 +4600,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_STOB_INDIRECT_INDEX_DISP) :
+ extract_fmt_stob_indirect_index_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_stob_indirect_index_disp.f
EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -4902,11 +4630,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_STOS_OFFSET) :
+ extract_fmt_stos_offset:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_stos_offset.f
EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
@@ -4926,11 +4655,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_STOS_INDIRECT_OFFSET) :
+ extract_fmt_stos_indirect_offset:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_stos_indirect_offset.f
EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
@@ -4952,11 +4682,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_STOS_INDIRECT) :
+ extract_fmt_stos_indirect:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_stos_indirect.f
EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -4977,11 +4708,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_STOS_INDIRECT_INDEX) :
+ extract_fmt_stos_indirect_index:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_stos_indirect_index.f
EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -5005,11 +4737,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_STOS_DISP) :
+ extract_fmt_stos_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_stos_disp.f
EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -5029,11 +4762,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_STOS_INDIRECT_DISP) :
+ extract_fmt_stos_indirect_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_stos_indirect_disp.f
EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -5055,11 +4789,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_STOS_INDEX_DISP) :
+ extract_fmt_stos_index_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_stos_index_disp.f
EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -5082,11 +4817,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_STOS_INDIRECT_INDEX_DISP) :
+ extract_fmt_stos_indirect_index_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_stos_indirect_index_disp.f
EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -5111,11 +4847,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_STL_OFFSET) :
+ extract_fmt_stl_offset:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_stl_offset.f
EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
@@ -5132,16 +4869,17 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
/* Record the fields for profiling. */
if (PROFILE_MODEL_P (current_cpu))
{
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
+ FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1));
FLD (in_st_src) = f_srcdst;
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_STL_INDIRECT_OFFSET) :
+ extract_fmt_stl_indirect_offset:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_stl_indirect_offset.f
EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
@@ -5160,16 +4898,17 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
if (PROFILE_MODEL_P (current_cpu))
{
FLD (in_abase) = f_abase;
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
+ FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1));
FLD (in_st_src) = f_srcdst;
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_STL_INDIRECT) :
+ extract_fmt_stl_indirect:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_stl_indirect.f
EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -5187,16 +4926,17 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
if (PROFILE_MODEL_P (current_cpu))
{
FLD (in_abase) = f_abase;
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
+ FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1));
FLD (in_st_src) = f_srcdst;
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_STL_INDIRECT_INDEX) :
+ extract_fmt_stl_indirect_index:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_stl_indirect_index.f
EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -5216,17 +4956,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
if (PROFILE_MODEL_P (current_cpu))
{
FLD (in_abase) = f_abase;
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
+ FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1));
FLD (in_index) = f_index;
FLD (in_st_src) = f_srcdst;
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_STL_DISP) :
+ extract_fmt_stl_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_stl_disp.f
EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -5243,16 +4984,17 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
/* Record the fields for profiling. */
if (PROFILE_MODEL_P (current_cpu))
{
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
+ FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1));
FLD (in_st_src) = f_srcdst;
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_STL_INDIRECT_DISP) :
+ extract_fmt_stl_indirect_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_stl_indirect_disp.f
EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -5271,16 +5013,17 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
if (PROFILE_MODEL_P (current_cpu))
{
FLD (in_abase) = f_abase;
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
+ FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1));
FLD (in_st_src) = f_srcdst;
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_STL_INDEX_DISP) :
+ extract_fmt_stl_index_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_stl_index_disp.f
EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -5299,17 +5042,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
/* Record the fields for profiling. */
if (PROFILE_MODEL_P (current_cpu))
{
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
+ FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1));
FLD (in_index) = f_index;
FLD (in_st_src) = f_srcdst;
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_STL_INDIRECT_INDEX_DISP) :
+ extract_fmt_stl_indirect_index_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_stl_indirect_index_disp.f
EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -5330,17 +5074,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
if (PROFILE_MODEL_P (current_cpu))
{
FLD (in_abase) = f_abase;
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
+ FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1));
FLD (in_index) = f_index;
FLD (in_st_src) = f_srcdst;
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_STT_OFFSET) :
+ extract_fmt_stt_offset:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_stt_offset.f
EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
@@ -5357,17 +5102,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
/* Record the fields for profiling. */
if (PROFILE_MODEL_P (current_cpu))
{
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2));
+ FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1));
+ FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2));
FLD (in_st_src) = f_srcdst;
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_STT_INDIRECT_OFFSET) :
+ extract_fmt_stt_indirect_offset:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_stt_indirect_offset.f
EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
@@ -5386,17 +5132,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
if (PROFILE_MODEL_P (current_cpu))
{
FLD (in_abase) = f_abase;
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2));
+ FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1));
+ FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2));
FLD (in_st_src) = f_srcdst;
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_STT_INDIRECT) :
+ extract_fmt_stt_indirect:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_stt_indirect.f
EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -5414,17 +5161,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
if (PROFILE_MODEL_P (current_cpu))
{
FLD (in_abase) = f_abase;
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2));
+ FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1));
+ FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2));
FLD (in_st_src) = f_srcdst;
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_STT_INDIRECT_INDEX) :
+ extract_fmt_stt_indirect_index:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_stt_indirect_index.f
EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -5444,18 +5192,19 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
if (PROFILE_MODEL_P (current_cpu))
{
FLD (in_abase) = f_abase;
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2));
+ FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1));
+ FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2));
FLD (in_index) = f_index;
FLD (in_st_src) = f_srcdst;
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_STT_DISP) :
+ extract_fmt_stt_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_stt_disp.f
EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -5472,17 +5221,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
/* Record the fields for profiling. */
if (PROFILE_MODEL_P (current_cpu))
{
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2));
+ FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1));
+ FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2));
FLD (in_st_src) = f_srcdst;
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_STT_INDIRECT_DISP) :
+ extract_fmt_stt_indirect_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_stt_indirect_disp.f
EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -5501,17 +5251,18 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
if (PROFILE_MODEL_P (current_cpu))
{
FLD (in_abase) = f_abase;
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2));
+ FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1));
+ FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2));
FLD (in_st_src) = f_srcdst;
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_STT_INDEX_DISP) :
+ extract_fmt_stt_index_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_stt_index_disp.f
EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -5530,18 +5281,19 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
/* Record the fields for profiling. */
if (PROFILE_MODEL_P (current_cpu))
{
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2));
+ FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1));
+ FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2));
FLD (in_index) = f_index;
FLD (in_st_src) = f_srcdst;
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_STT_INDIRECT_INDEX_DISP) :
+ extract_fmt_stt_indirect_index_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_stt_indirect_index_disp.f
EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -5562,18 +5314,19 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
if (PROFILE_MODEL_P (current_cpu))
{
FLD (in_abase) = f_abase;
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2));
+ FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1));
+ FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2));
FLD (in_index) = f_index;
FLD (in_st_src) = f_srcdst;
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_STQ_OFFSET) :
+ extract_fmt_stq_offset:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_stq_offset.f
EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
@@ -5590,18 +5343,19 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
/* Record the fields for profiling. */
if (PROFILE_MODEL_P (current_cpu))
{
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2));
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_3) = ((FLD (f_srcdst)) + (3));
+ FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1));
+ FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2));
+ FLD (in_h_gr_add__VM_index_of_st_src_3) = ((FLD (f_srcdst)) + (3));
FLD (in_st_src) = f_srcdst;
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_STQ_INDIRECT_OFFSET) :
+ extract_fmt_stq_indirect_offset:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_stq_indirect_offset.f
EXTRACT_IFMT_ST_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
@@ -5620,18 +5374,19 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
if (PROFILE_MODEL_P (current_cpu))
{
FLD (in_abase) = f_abase;
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2));
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_3) = ((FLD (f_srcdst)) + (3));
+ FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1));
+ FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2));
+ FLD (in_h_gr_add__VM_index_of_st_src_3) = ((FLD (f_srcdst)) + (3));
FLD (in_st_src) = f_srcdst;
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_STQ_INDIRECT) :
+ extract_fmt_stq_indirect:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_stq_indirect.f
EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -5649,18 +5404,19 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
if (PROFILE_MODEL_P (current_cpu))
{
FLD (in_abase) = f_abase;
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2));
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_3) = ((FLD (f_srcdst)) + (3));
+ FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1));
+ FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2));
+ FLD (in_h_gr_add__VM_index_of_st_src_3) = ((FLD (f_srcdst)) + (3));
FLD (in_st_src) = f_srcdst;
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_STQ_INDIRECT_INDEX) :
+ extract_fmt_stq_indirect_index:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_stq_indirect_index.f
EXTRACT_IFMT_ST_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -5680,19 +5436,20 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
if (PROFILE_MODEL_P (current_cpu))
{
FLD (in_abase) = f_abase;
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2));
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_3) = ((FLD (f_srcdst)) + (3));
+ FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1));
+ FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2));
+ FLD (in_h_gr_add__VM_index_of_st_src_3) = ((FLD (f_srcdst)) + (3));
FLD (in_index) = f_index;
FLD (in_st_src) = f_srcdst;
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_STQ_DISP) :
+ extract_fmt_stq_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_stq_disp.f
EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -5709,18 +5466,19 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
/* Record the fields for profiling. */
if (PROFILE_MODEL_P (current_cpu))
{
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2));
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_3) = ((FLD (f_srcdst)) + (3));
+ FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1));
+ FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2));
+ FLD (in_h_gr_add__VM_index_of_st_src_3) = ((FLD (f_srcdst)) + (3));
FLD (in_st_src) = f_srcdst;
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_STQ_INDIRECT_DISP) :
+ extract_fmt_stq_indirect_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_stq_indirect_disp.f
EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -5739,18 +5497,19 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
if (PROFILE_MODEL_P (current_cpu))
{
FLD (in_abase) = f_abase;
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2));
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_3) = ((FLD (f_srcdst)) + (3));
+ FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1));
+ FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2));
+ FLD (in_h_gr_add__VM_index_of_st_src_3) = ((FLD (f_srcdst)) + (3));
FLD (in_st_src) = f_srcdst;
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_STQ_INDEX_DISP) :
+ extract_fmt_stq_index_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_stq_index_disp.f
EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -5769,19 +5528,20 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
/* Record the fields for profiling. */
if (PROFILE_MODEL_P (current_cpu))
{
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2));
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_3) = ((FLD (f_srcdst)) + (3));
+ FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1));
+ FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2));
+ FLD (in_h_gr_add__VM_index_of_st_src_3) = ((FLD (f_srcdst)) + (3));
FLD (in_index) = f_index;
FLD (in_st_src) = f_srcdst;
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_STQ_INDIRECT_INDEX_DISP) :
+ extract_fmt_stq_indirect_index_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_stq_indirect_index_disp.f
EXTRACT_IFMT_ST_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -5802,19 +5562,20 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
if (PROFILE_MODEL_P (current_cpu))
{
FLD (in_abase) = f_abase;
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_1) = ((FLD (f_srcdst)) + (1));
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_2) = ((FLD (f_srcdst)) + (2));
- FLD (in_h_gr_add__VM_index_of_st_src_const__WI_3) = ((FLD (f_srcdst)) + (3));
+ FLD (in_h_gr_add__VM_index_of_st_src_1) = ((FLD (f_srcdst)) + (1));
+ FLD (in_h_gr_add__VM_index_of_st_src_2) = ((FLD (f_srcdst)) + (2));
+ FLD (in_h_gr_add__VM_index_of_st_src_3) = ((FLD (f_srcdst)) + (3));
FLD (in_index) = f_index;
FLD (in_st_src) = f_srcdst;
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_CMPOBE_REG) :
+ extract_fmt_cmpobe_reg:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_reg.f
EXTRACT_IFMT_CMPOBE_REG_VARS /* f-opcode f-br-src1 f-br-src2 f-br-m1 f-br-disp f-br-zero */
@@ -5837,11 +5598,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_CMPOBE_LIT) :
+ extract_fmt_cmpobe_lit:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.cti.fields.fmt_cmpobe_lit.f
EXTRACT_IFMT_CMPOBE_LIT_VARS /* f-opcode f-br-src1 f-br-src2 f-br-m1 f-br-disp f-br-zero */
@@ -5863,11 +5625,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_CMPOBL_REG) :
+ extract_fmt_cmpobl_reg:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_reg.f
EXTRACT_IFMT_CMPOBE_REG_VARS /* f-opcode f-br-src1 f-br-src2 f-br-m1 f-br-disp f-br-zero */
@@ -5890,11 +5653,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_CMPOBL_LIT) :
+ extract_fmt_cmpobl_lit:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.cti.fields.fmt_cmpobl_lit.f
EXTRACT_IFMT_CMPOBE_LIT_VARS /* f-opcode f-br-src1 f-br-src2 f-br-m1 f-br-disp f-br-zero */
@@ -5916,11 +5680,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_BBC_REG) :
+ extract_fmt_bbc_reg:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.cti.fields.fmt_bbc_reg.f
EXTRACT_IFMT_CMPOBE_REG_VARS /* f-opcode f-br-src1 f-br-src2 f-br-m1 f-br-disp f-br-zero */
@@ -5943,11 +5708,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_BBC_LIT) :
+ extract_fmt_bbc_lit:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.cti.fields.fmt_bbc_lit.f
EXTRACT_IFMT_CMPOBE_LIT_VARS /* f-opcode f-br-src1 f-br-src2 f-br-m1 f-br-disp f-br-zero */
@@ -5969,11 +5735,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_CMPI) :
+ extract_fmt_cmpi:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_cmpi.f
EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
@@ -5994,11 +5761,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_CMPI1) :
+ extract_fmt_cmpi1:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_cmpi1.f
EXTRACT_IFMT_MULO1_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
@@ -6018,11 +5786,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_CMPI2) :
+ extract_fmt_cmpi2:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_cmpi2.f
EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
@@ -6042,11 +5811,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_CMPI3) :
+ extract_fmt_cmpi3:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_cmpi3.f
EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
@@ -6065,11 +5835,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_CMPO) :
+ extract_fmt_cmpo:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_cmpo.f
EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
@@ -6090,11 +5861,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_CMPO1) :
+ extract_fmt_cmpo1:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_cmpo1.f
EXTRACT_IFMT_MULO1_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
@@ -6114,11 +5886,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_CMPO2) :
+ extract_fmt_cmpo2:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_cmpo2.f
EXTRACT_IFMT_MULO2_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
@@ -6138,11 +5911,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_CMPO3) :
+ extract_fmt_cmpo3:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_cmpo3.f
EXTRACT_IFMT_MULO3_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
@@ -6161,11 +5935,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_TESTNO_REG) :
+ extract_fmt_testno_reg:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_testno_reg.f
EXTRACT_IFMT_CMPOBE_REG_VARS /* f-opcode f-br-src1 f-br-src2 f-br-m1 f-br-disp f-br-zero */
@@ -6184,11 +5959,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_BNO) :
+ extract_fmt_bno:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.cti.fields.fmt_bno.f
EXTRACT_IFMT_BNO_VARS /* f-opcode f-ctrl-disp f-ctrl-zero */
@@ -6207,11 +5983,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_B) :
+ extract_fmt_b:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.cti.fields.fmt_b.f
EXTRACT_IFMT_BNO_VARS /* f-opcode f-ctrl-disp f-ctrl-zero */
@@ -6230,11 +6007,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_BX_INDIRECT_OFFSET) :
+ extract_fmt_bx_indirect_offset:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect_offset.f
EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
@@ -6255,11 +6033,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_BX_INDIRECT) :
+ extract_fmt_bx_indirect:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect.f
EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -6279,11 +6058,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_BX_INDIRECT_INDEX) :
+ extract_fmt_bx_indirect_index:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect_index.f
EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -6306,11 +6086,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_BX_DISP) :
+ extract_fmt_bx_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.cti.fields.fmt_bx_disp.f
EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -6329,11 +6110,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_BX_INDIRECT_DISP) :
+ extract_fmt_bx_indirect_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.cti.fields.fmt_bx_indirect_disp.f
EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -6354,11 +6136,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_CALLX_DISP) :
+ extract_fmt_callx_disp:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.cti.fields.fmt_callx_disp.f
EXTRACT_IFMT_LDA_DISP_VARS /* f-opcode f-optdisp f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -6411,11 +6194,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_CALLX_INDIRECT) :
+ extract_fmt_callx_indirect:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.cti.fields.fmt_callx_indirect.f
EXTRACT_IFMT_LDA_INDIRECT_VARS /* f-opcode f-srcdst f-abase f-modeb f-scale f-zerob f-index */
@@ -6469,11 +6253,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_CALLX_INDIRECT_OFFSET) :
+ extract_fmt_callx_indirect_offset:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.cti.fields.fmt_callx_indirect_offset.f
EXTRACT_IFMT_LDA_OFFSET_VARS /* f-opcode f-srcdst f-abase f-modea f-zeroa f-offset */
@@ -6528,11 +6313,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_RET) :
+ extract_fmt_ret:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.cti.fields.fmt_ret.f
EXTRACT_IFMT_BNO_VARS /* f-opcode f-ctrl-disp f-ctrl-zero */
@@ -6570,11 +6356,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_CALLS) :
+ extract_fmt_calls:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.cti.fields.fmt_calls.f
EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
@@ -6594,11 +6381,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_FMARK) :
+ extract_fmt_fmark:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.cti.fields.fmt_fmark.f
EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
@@ -6616,11 +6404,12 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
}
#endif
#undef FLD
- BREAK (ex);
+ return idesc;
}
- CASE (ex, FMT_FLUSHREG) :
+ extract_fmt_flushreg:
{
+ const IDESC *idesc = &i960base_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
#define FLD(f) abuf->fields.fmt_flushreg.f
EXTRACT_IFMT_MULO_VARS /* f-opcode f-srcdst f-src2 f-m3 f-m2 f-m1 f-opcode2 f-zero f-src1 */
@@ -6631,14 +6420,7 @@ i960base_decode (SIM_CPU *current_cpu, IADDR pc,
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_flushreg", (char *) 0));
#undef FLD
- BREAK (ex);
- }
-
-
- }
- ENDSWITCH (ex)
-
+ return idesc;
}
- return idecode->idesc;
}
diff --git a/sim/i960/decode.h b/sim/i960/decode.h
index 6137217..80fbde6 100644
--- a/sim/i960/decode.h
+++ b/sim/i960/decode.h
@@ -48,8 +48,10 @@ typedef enum i960base_insn_type {
, I960BASE_INSN_NOTAND2, I960BASE_INSN_NOTAND3, I960BASE_INSN_XOR, I960BASE_INSN_XOR1
, I960BASE_INSN_XOR2, I960BASE_INSN_XOR3, I960BASE_INSN_OR, I960BASE_INSN_OR1
, I960BASE_INSN_OR2, I960BASE_INSN_OR3, I960BASE_INSN_NOR, I960BASE_INSN_NOR1
- , I960BASE_INSN_NOR2, I960BASE_INSN_NOR3, I960BASE_INSN_NOT, I960BASE_INSN_NOT1
- , I960BASE_INSN_NOT2, I960BASE_INSN_NOT3, I960BASE_INSN_CLRBIT, I960BASE_INSN_CLRBIT1
+ , I960BASE_INSN_NOR2, I960BASE_INSN_NOR3, I960BASE_INSN_XNOR, I960BASE_INSN_XNOR1
+ , I960BASE_INSN_XNOR2, I960BASE_INSN_XNOR3, I960BASE_INSN_NOT, I960BASE_INSN_NOT1
+ , I960BASE_INSN_NOT2, I960BASE_INSN_NOT3, I960BASE_INSN_ORNOT, I960BASE_INSN_ORNOT1
+ , I960BASE_INSN_ORNOT2, I960BASE_INSN_ORNOT3, I960BASE_INSN_CLRBIT, I960BASE_INSN_CLRBIT1
, I960BASE_INSN_CLRBIT2, I960BASE_INSN_CLRBIT3, I960BASE_INSN_SHLO, I960BASE_INSN_SHLO1
, I960BASE_INSN_SHLO2, I960BASE_INSN_SHLO3, I960BASE_INSN_SHRO, I960BASE_INSN_SHRO1
, I960BASE_INSN_SHRO2, I960BASE_INSN_SHRO3, I960BASE_INSN_SHLI, I960BASE_INSN_SHLI1
@@ -192,10 +194,18 @@ SEM (nor)
SEM (nor1)
SEM (nor2)
SEM (nor3)
+SEM (xnor)
+SEM (xnor1)
+SEM (xnor2)
+SEM (xnor3)
SEM (not)
SEM (not1)
SEM (not2)
SEM (not3)
+SEM (ornot)
+SEM (ornot1)
+SEM (ornot2)
+SEM (ornot3)
SEM (clrbit)
SEM (clrbit1)
SEM (clrbit2)
diff --git a/sim/i960/devices.c b/sim/i960/devices.c
index d34e672..0a47569 100644
--- a/sim/i960/devices.c
+++ b/sim/i960/devices.c
@@ -32,10 +32,8 @@ device i960_devices;
int
device_io_read_buffer (device *me, void *source, int space,
address_word addr, unsigned nr_bytes,
- SIM_CPU *cpu, sim_cia cia)
+ SIM_DESC sd, SIM_CPU *cpu, sim_cia cia)
{
- SIM_DESC sd = CPU_STATE (cpu);
-
if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
return nr_bytes;
@@ -70,10 +68,8 @@ device_io_read_buffer (device *me, void *source, int space,
int
device_io_write_buffer (device *me, const void *source, int space,
address_word addr, unsigned nr_bytes,
- SIM_CPU *cpu, sim_cia cia)
+ SIM_DESC sd, SIM_CPU *cpu, sim_cia cia)
{
- SIM_DESC sd = CPU_STATE (cpu);
-
#if WITH_SCACHE
/* MSPR support is deprecated but is kept in for upward compatibility
with existing overlay support. */
@@ -105,4 +101,7 @@ device_io_write_buffer (device *me, const void *source, int space,
return nr_bytes;
}
-void device_error () {}
+void
+device_error (device *me, char *message, ...)
+{
+}
diff --git a/sim/i960/i960-desc.c b/sim/i960/i960-desc.c
index 6ea8fdc..8c1ca64 100644
--- a/sim/i960/i960-desc.c
+++ b/sim/i960/i960-desc.c
@@ -25,6 +25,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#include "sysdep.h"
#include <ctype.h>
#include <stdio.h>
+#include <stdarg.h>
#include "ansidecl.h"
#include "bfd.h"
#include "symcat.h"
@@ -50,15 +51,22 @@ static const CGEN_ATTR_ENTRY MACH_attr[] =
{ 0, 0 }
};
+static const CGEN_ATTR_ENTRY ISA_attr[] =
+{
+ { "i960", ISA_I960 },
+ { "max", ISA_MAX },
+ { 0, 0 }
+};
+
const CGEN_ATTR_TABLE i960_cgen_ifield_attr_table[] =
{
{ "MACH", & MACH_attr[0] },
{ "VIRTUAL", &bool_attr[0], &bool_attr[0] },
- { "UNSIGNED", &bool_attr[0], &bool_attr[0] },
{ "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
{ "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
{ "RESERVED", &bool_attr[0], &bool_attr[0] },
{ "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
+ { "SIGNED", &bool_attr[0], &bool_attr[0] },
{ 0, 0, 0 }
};
@@ -66,10 +74,7 @@ const CGEN_ATTR_TABLE i960_cgen_hardware_attr_table[] =
{
{ "MACH", & MACH_attr[0] },
{ "VIRTUAL", &bool_attr[0], &bool_attr[0] },
- { "UNSIGNED", &bool_attr[0], &bool_attr[0] },
- { "SIGNED", &bool_attr[0], &bool_attr[0] },
{ "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
- { "FUN-ACCESS", &bool_attr[0], &bool_attr[0] },
{ "PC", &bool_attr[0], &bool_attr[0] },
{ "PROFILE", &bool_attr[0], &bool_attr[0] },
{ 0, 0, 0 }
@@ -79,10 +84,10 @@ const CGEN_ATTR_TABLE i960_cgen_operand_attr_table[] =
{
{ "MACH", & MACH_attr[0] },
{ "VIRTUAL", &bool_attr[0], &bool_attr[0] },
- { "UNSIGNED", &bool_attr[0], &bool_attr[0] },
{ "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
{ "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
{ "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
+ { "SIGNED", &bool_attr[0], &bool_attr[0] },
{ "NEGATIVE", &bool_attr[0], &bool_attr[0] },
{ "RELAX", &bool_attr[0], &bool_attr[0] },
{ "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
@@ -105,7 +110,22 @@ const CGEN_ATTR_TABLE i960_cgen_insn_attr_table[] =
{ 0, 0, 0 }
};
-CGEN_KEYWORD_ENTRY i960_cgen_opval_h_gr_entries[] =
+/* Instruction set variants. */
+
+static const CGEN_ISA i960_cgen_isa_table[] = {
+ { "i960", 32, 32, 32, 64, },
+ { 0 }
+};
+
+/* Machine variants. */
+
+static const CGEN_MACH i960_cgen_mach_table[] = {
+ { "i960:ka_sa", "i960:ka_sa", MACH_I960_KA_SA },
+ { "i960:ca", "i960:ca", MACH_I960_CA },
+ { 0 }
+};
+
+static CGEN_KEYWORD_ENTRY i960_cgen_opval_h_gr_entries[] =
{
{ "fp", 31 },
{ "sp", 1 },
@@ -143,18 +163,18 @@ CGEN_KEYWORD_ENTRY i960_cgen_opval_h_gr_entries[] =
{ "g15", 31 }
};
-CGEN_KEYWORD i960_cgen_opval_h_gr =
+CGEN_KEYWORD i960_cgen_opval_h_gr =
{
& i960_cgen_opval_h_gr_entries[0],
34
};
-CGEN_KEYWORD_ENTRY i960_cgen_opval_h_cc_entries[] =
+static CGEN_KEYWORD_ENTRY i960_cgen_opval_h_cc_entries[] =
{
{ "cc", 0 }
};
-CGEN_KEYWORD i960_cgen_opval_h_cc =
+CGEN_KEYWORD i960_cgen_opval_h_cc =
{
& i960_cgen_opval_h_cc_entries[0],
1
@@ -164,57 +184,55 @@ CGEN_KEYWORD i960_cgen_opval_h_cc =
/* The hardware table. */
-#define A(a) (1 << (CONCAT2 (CGEN_HW_,a) - CGEN_ATTR_BOOL_OFFSET))
-#define HW_ENT(n) i960_cgen_hw_table[n]
+#define A(a) (1 << CONCAT2 (CGEN_HW_,a))
const CGEN_HW_ENTRY i960_cgen_hw_table[] =
{
- { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
- { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
- { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
- { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
- { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
- { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
- { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & i960_cgen_opval_h_gr, { CGEN_HW_NBOOL_ATTRS, 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } },
- { HW_H_CC, & HW_ENT (HW_H_CC + 1), "h-cc", CGEN_ASM_KEYWORD, (PTR) & i960_cgen_opval_h_cc, { CGEN_HW_NBOOL_ATTRS, 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } },
+ { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+ { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+ { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+ { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+ { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+ { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
+ { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & i960_cgen_opval_h_gr, { 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } },
+ { "h-cc", HW_H_CC, CGEN_ASM_KEYWORD, (PTR) & i960_cgen_opval_h_cc, { 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } },
{ 0 }
};
-/* don't undef HW_ENT, used later */
#undef A
/* The instruction field table. */
-#define A(a) (1 << (CONCAT2 (CGEN_IFLD_,a) - CGEN_ATTR_BOOL_OFFSET))
+#define A(a) (1 << CONCAT2 (CGEN_IFLD_,a))
const CGEN_IFLD i960_cgen_ifld_table[] =
{
- { I960_F_NIL, "f-nil", 0, 0, 0, 0, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
- { I960_F_OPCODE, "f-opcode", 0, 32, 0, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } },
- { I960_F_SRCDST, "f-srcdst", 0, 32, 8, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } },
- { I960_F_SRC2, "f-src2", 0, 32, 13, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } },
- { I960_F_M3, "f-m3", 0, 32, 18, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } },
- { I960_F_M2, "f-m2", 0, 32, 19, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } },
- { I960_F_M1, "f-m1", 0, 32, 20, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } },
- { I960_F_OPCODE2, "f-opcode2", 0, 32, 21, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } },
- { I960_F_ZERO, "f-zero", 0, 32, 25, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } },
- { I960_F_SRC1, "f-src1", 0, 32, 27, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } },
- { I960_F_ABASE, "f-abase", 0, 32, 13, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } },
- { I960_F_MODEA, "f-modea", 0, 32, 18, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } },
- { I960_F_ZEROA, "f-zeroa", 0, 32, 19, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } },
- { I960_F_OFFSET, "f-offset", 0, 32, 20, 12, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } },
- { I960_F_MODEB, "f-modeb", 0, 32, 18, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } },
- { I960_F_SCALE, "f-scale", 0, 32, 22, 3, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } },
- { I960_F_ZEROB, "f-zerob", 0, 32, 25, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } },
- { I960_F_INDEX, "f-index", 0, 32, 27, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } },
- { I960_F_OPTDISP, "f-optdisp", 32, 32, 0, 32, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } },
- { I960_F_BR_SRC1, "f-br-src1", 0, 32, 8, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } },
- { I960_F_BR_SRC2, "f-br-src2", 0, 32, 13, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } },
- { I960_F_BR_M1, "f-br-m1", 0, 32, 18, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } },
- { I960_F_BR_DISP, "f-br-disp", 0, 32, 19, 11, { CGEN_IFLD_NBOOL_ATTRS, 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
- { I960_F_BR_ZERO, "f-br-zero", 0, 32, 30, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } },
- { I960_F_CTRL_DISP, "f-ctrl-disp", 0, 32, 8, 22, { CGEN_IFLD_NBOOL_ATTRS, 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
- { I960_F_CTRL_ZERO, "f-ctrl-zero", 0, 32, 30, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } },
+ { I960_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
+ { I960_F_OPCODE, "f-opcode", 0, 32, 0, 8, { 0, { (1<<MACH_BASE) } } },
+ { I960_F_SRCDST, "f-srcdst", 0, 32, 8, 5, { 0, { (1<<MACH_BASE) } } },
+ { I960_F_SRC2, "f-src2", 0, 32, 13, 5, { 0, { (1<<MACH_BASE) } } },
+ { I960_F_M3, "f-m3", 0, 32, 18, 1, { 0, { (1<<MACH_BASE) } } },
+ { I960_F_M2, "f-m2", 0, 32, 19, 1, { 0, { (1<<MACH_BASE) } } },
+ { I960_F_M1, "f-m1", 0, 32, 20, 1, { 0, { (1<<MACH_BASE) } } },
+ { I960_F_OPCODE2, "f-opcode2", 0, 32, 21, 4, { 0, { (1<<MACH_BASE) } } },
+ { I960_F_ZERO, "f-zero", 0, 32, 25, 2, { 0, { (1<<MACH_BASE) } } },
+ { I960_F_SRC1, "f-src1", 0, 32, 27, 5, { 0, { (1<<MACH_BASE) } } },
+ { I960_F_ABASE, "f-abase", 0, 32, 13, 5, { 0, { (1<<MACH_BASE) } } },
+ { I960_F_MODEA, "f-modea", 0, 32, 18, 1, { 0, { (1<<MACH_BASE) } } },
+ { I960_F_ZEROA, "f-zeroa", 0, 32, 19, 1, { 0, { (1<<MACH_BASE) } } },
+ { I960_F_OFFSET, "f-offset", 0, 32, 20, 12, { 0, { (1<<MACH_BASE) } } },
+ { I960_F_MODEB, "f-modeb", 0, 32, 18, 4, { 0, { (1<<MACH_BASE) } } },
+ { I960_F_SCALE, "f-scale", 0, 32, 22, 3, { 0, { (1<<MACH_BASE) } } },
+ { I960_F_ZEROB, "f-zerob", 0, 32, 25, 2, { 0, { (1<<MACH_BASE) } } },
+ { I960_F_INDEX, "f-index", 0, 32, 27, 5, { 0, { (1<<MACH_BASE) } } },
+ { I960_F_OPTDISP, "f-optdisp", 32, 32, 0, 32, { 0, { (1<<MACH_BASE) } } },
+ { I960_F_BR_SRC1, "f-br-src1", 0, 32, 8, 5, { 0, { (1<<MACH_BASE) } } },
+ { I960_F_BR_SRC2, "f-br-src2", 0, 32, 13, 5, { 0, { (1<<MACH_BASE) } } },
+ { I960_F_BR_M1, "f-br-m1", 0, 32, 18, 1, { 0, { (1<<MACH_BASE) } } },
+ { I960_F_BR_DISP, "f-br-disp", 0, 32, 19, 11, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
+ { I960_F_BR_ZERO, "f-br-zero", 0, 32, 30, 2, { 0, { (1<<MACH_BASE) } } },
+ { I960_F_CTRL_DISP, "f-ctrl-disp", 0, 32, 8, 22, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
+ { I960_F_CTRL_ZERO, "f-ctrl-zero", 0, 32, 30, 2, { 0, { (1<<MACH_BASE) } } },
{ 0 }
};
@@ -222,67 +240,68 @@ const CGEN_IFLD i960_cgen_ifld_table[] =
/* The operand table. */
-#define A(a) (1 << (CONCAT2 (CGEN_OPERAND_,a) - CGEN_ATTR_BOOL_OFFSET))
+#define A(a) (1 << CONCAT2 (CGEN_OPERAND_,a))
#define OPERAND(op) CONCAT2 (I960_OPERAND_,op)
-const CGEN_OPERAND i960_cgen_operand_table[MAX_OPERANDS] =
+const CGEN_OPERAND i960_cgen_operand_table[] =
{
/* pc: program counter */
- { "pc", & HW_ENT (HW_H_PC), 0, 0,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
+ { "pc", I960_OPERAND_PC, HW_H_PC, 0, 0,
+ { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* src1: source register 1 */
- { "src1", & HW_ENT (HW_H_GR), 27, 5,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } },
+ { "src1", I960_OPERAND_SRC1, HW_H_GR, 27, 5,
+ { 0, { (1<<MACH_BASE) } } },
/* src2: source register 2 */
- { "src2", & HW_ENT (HW_H_GR), 13, 5,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } },
+ { "src2", I960_OPERAND_SRC2, HW_H_GR, 13, 5,
+ { 0, { (1<<MACH_BASE) } } },
/* dst: source/dest register */
- { "dst", & HW_ENT (HW_H_GR), 8, 5,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } },
+ { "dst", I960_OPERAND_DST, HW_H_GR, 8, 5,
+ { 0, { (1<<MACH_BASE) } } },
/* lit1: literal 1 */
- { "lit1", & HW_ENT (HW_H_UINT), 27, 5,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } },
+ { "lit1", I960_OPERAND_LIT1, HW_H_UINT, 27, 5,
+ { 0, { (1<<MACH_BASE) } } },
/* lit2: literal 2 */
- { "lit2", & HW_ENT (HW_H_UINT), 13, 5,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } },
+ { "lit2", I960_OPERAND_LIT2, HW_H_UINT, 13, 5,
+ { 0, { (1<<MACH_BASE) } } },
/* st_src: store src */
- { "st_src", & HW_ENT (HW_H_GR), 8, 5,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } },
+ { "st_src", I960_OPERAND_ST_SRC, HW_H_GR, 8, 5,
+ { 0, { (1<<MACH_BASE) } } },
/* abase: abase */
- { "abase", & HW_ENT (HW_H_GR), 13, 5,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } },
+ { "abase", I960_OPERAND_ABASE, HW_H_GR, 13, 5,
+ { 0, { (1<<MACH_BASE) } } },
/* offset: offset */
- { "offset", & HW_ENT (HW_H_UINT), 20, 12,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } },
+ { "offset", I960_OPERAND_OFFSET, HW_H_UINT, 20, 12,
+ { 0, { (1<<MACH_BASE) } } },
/* scale: scale */
- { "scale", & HW_ENT (HW_H_UINT), 22, 3,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } },
+ { "scale", I960_OPERAND_SCALE, HW_H_UINT, 22, 3,
+ { 0, { (1<<MACH_BASE) } } },
/* index: index */
- { "index", & HW_ENT (HW_H_GR), 27, 5,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } },
+ { "index", I960_OPERAND_INDEX, HW_H_GR, 27, 5,
+ { 0, { (1<<MACH_BASE) } } },
/* optdisp: optional displacement */
- { "optdisp", & HW_ENT (HW_H_UINT), 0, 32,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } },
+ { "optdisp", I960_OPERAND_OPTDISP, HW_H_UINT, 0, 32,
+ { 0, { (1<<MACH_BASE) } } },
/* br_src1: branch src1 */
- { "br_src1", & HW_ENT (HW_H_GR), 8, 5,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } },
+ { "br_src1", I960_OPERAND_BR_SRC1, HW_H_GR, 8, 5,
+ { 0, { (1<<MACH_BASE) } } },
/* br_src2: branch src2 */
- { "br_src2", & HW_ENT (HW_H_GR), 13, 5,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } },
+ { "br_src2", I960_OPERAND_BR_SRC2, HW_H_GR, 13, 5,
+ { 0, { (1<<MACH_BASE) } } },
/* br_disp: branch displacement */
- { "br_disp", & HW_ENT (HW_H_IADDR), 19, 11,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
+ { "br_disp", I960_OPERAND_BR_DISP, HW_H_IADDR, 19, 11,
+ { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
/* br_lit1: branch literal 1 */
- { "br_lit1", & HW_ENT (HW_H_UINT), 8, 5,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|A(UNSIGNED), { (1<<MACH_BASE) } } },
+ { "br_lit1", I960_OPERAND_BR_LIT1, HW_H_UINT, 8, 5,
+ { 0, { (1<<MACH_BASE) } } },
/* ctrl_disp: ctrl branch disp */
- { "ctrl_disp", & HW_ENT (HW_H_IADDR), 8, 22,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
+ { "ctrl_disp", I960_OPERAND_CTRL_DISP, HW_H_IADDR, 8, 22,
+ { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
+ { 0 }
};
#undef A
-#define A(a) (1 << (CONCAT2 (CGEN_INSN_,a) - CGEN_ATTR_BOOL_OFFSET))
+#define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
/* The instruction table. */
@@ -296,1417 +315,1457 @@ static const CGEN_IBASE i960_cgen_insn_table[MAX_INSNS] =
/* mulo $src1, $src2, $dst */
{
I960_INSN_MULO, "mulo", "mulo", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* mulo $lit1, $src2, $dst */
{
I960_INSN_MULO1, "mulo1", "mulo", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* mulo $src1, $lit2, $dst */
{
I960_INSN_MULO2, "mulo2", "mulo", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* mulo $lit1, $lit2, $dst */
{
I960_INSN_MULO3, "mulo3", "mulo", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* remo $src1, $src2, $dst */
{
I960_INSN_REMO, "remo", "remo", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* remo $lit1, $src2, $dst */
{
I960_INSN_REMO1, "remo1", "remo", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* remo $src1, $lit2, $dst */
{
I960_INSN_REMO2, "remo2", "remo", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* remo $lit1, $lit2, $dst */
{
I960_INSN_REMO3, "remo3", "remo", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* divo $src1, $src2, $dst */
{
I960_INSN_DIVO, "divo", "divo", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* divo $lit1, $src2, $dst */
{
I960_INSN_DIVO1, "divo1", "divo", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* divo $src1, $lit2, $dst */
{
I960_INSN_DIVO2, "divo2", "divo", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* divo $lit1, $lit2, $dst */
{
I960_INSN_DIVO3, "divo3", "divo", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* remi $src1, $src2, $dst */
{
I960_INSN_REMI, "remi", "remi", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* remi $lit1, $src2, $dst */
{
I960_INSN_REMI1, "remi1", "remi", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* remi $src1, $lit2, $dst */
{
I960_INSN_REMI2, "remi2", "remi", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* remi $lit1, $lit2, $dst */
{
I960_INSN_REMI3, "remi3", "remi", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* divi $src1, $src2, $dst */
{
I960_INSN_DIVI, "divi", "divi", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* divi $lit1, $src2, $dst */
{
I960_INSN_DIVI1, "divi1", "divi", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* divi $src1, $lit2, $dst */
{
I960_INSN_DIVI2, "divi2", "divi", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* divi $lit1, $lit2, $dst */
{
I960_INSN_DIVI3, "divi3", "divi", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* addo $src1, $src2, $dst */
{
I960_INSN_ADDO, "addo", "addo", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* addo $lit1, $src2, $dst */
{
I960_INSN_ADDO1, "addo1", "addo", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* addo $src1, $lit2, $dst */
{
I960_INSN_ADDO2, "addo2", "addo", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* addo $lit1, $lit2, $dst */
{
I960_INSN_ADDO3, "addo3", "addo", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* subo $src1, $src2, $dst */
{
I960_INSN_SUBO, "subo", "subo", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* subo $lit1, $src2, $dst */
{
I960_INSN_SUBO1, "subo1", "subo", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* subo $src1, $lit2, $dst */
{
I960_INSN_SUBO2, "subo2", "subo", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* subo $lit1, $lit2, $dst */
{
I960_INSN_SUBO3, "subo3", "subo", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* notbit $src1, $src2, $dst */
{
I960_INSN_NOTBIT, "notbit", "notbit", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* notbit $lit1, $src2, $dst */
{
I960_INSN_NOTBIT1, "notbit1", "notbit", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* notbit $src1, $lit2, $dst */
{
I960_INSN_NOTBIT2, "notbit2", "notbit", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* notbit $lit1, $lit2, $dst */
{
I960_INSN_NOTBIT3, "notbit3", "notbit", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* and $src1, $src2, $dst */
{
I960_INSN_AND, "and", "and", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* and $lit1, $src2, $dst */
{
I960_INSN_AND1, "and1", "and", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* and $src1, $lit2, $dst */
{
I960_INSN_AND2, "and2", "and", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* and $lit1, $lit2, $dst */
{
I960_INSN_AND3, "and3", "and", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* andnot $src1, $src2, $dst */
{
I960_INSN_ANDNOT, "andnot", "andnot", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* andnot $lit1, $src2, $dst */
{
I960_INSN_ANDNOT1, "andnot1", "andnot", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* andnot $src1, $lit2, $dst */
{
I960_INSN_ANDNOT2, "andnot2", "andnot", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* andnot $lit1, $lit2, $dst */
{
I960_INSN_ANDNOT3, "andnot3", "andnot", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* setbit $src1, $src2, $dst */
{
I960_INSN_SETBIT, "setbit", "setbit", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* setbit $lit1, $src2, $dst */
{
I960_INSN_SETBIT1, "setbit1", "setbit", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* setbit $src1, $lit2, $dst */
{
I960_INSN_SETBIT2, "setbit2", "setbit", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* setbit $lit1, $lit2, $dst */
{
I960_INSN_SETBIT3, "setbit3", "setbit", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* notand $src1, $src2, $dst */
{
I960_INSN_NOTAND, "notand", "notand", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* notand $lit1, $src2, $dst */
{
I960_INSN_NOTAND1, "notand1", "notand", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* notand $src1, $lit2, $dst */
{
I960_INSN_NOTAND2, "notand2", "notand", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* notand $lit1, $lit2, $dst */
{
I960_INSN_NOTAND3, "notand3", "notand", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* xor $src1, $src2, $dst */
{
I960_INSN_XOR, "xor", "xor", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* xor $lit1, $src2, $dst */
{
I960_INSN_XOR1, "xor1", "xor", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* xor $src1, $lit2, $dst */
{
I960_INSN_XOR2, "xor2", "xor", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* xor $lit1, $lit2, $dst */
{
I960_INSN_XOR3, "xor3", "xor", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* or $src1, $src2, $dst */
{
I960_INSN_OR, "or", "or", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* or $lit1, $src2, $dst */
{
I960_INSN_OR1, "or1", "or", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* or $src1, $lit2, $dst */
{
I960_INSN_OR2, "or2", "or", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* or $lit1, $lit2, $dst */
{
I960_INSN_OR3, "or3", "or", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* nor $src1, $src2, $dst */
{
I960_INSN_NOR, "nor", "nor", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* nor $lit1, $src2, $dst */
{
I960_INSN_NOR1, "nor1", "nor", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* nor $src1, $lit2, $dst */
{
I960_INSN_NOR2, "nor2", "nor", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* nor $lit1, $lit2, $dst */
{
I960_INSN_NOR3, "nor3", "nor", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* xnor $src1, $src2, $dst */
+ {
+ I960_INSN_XNOR, "xnor", "xnor", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* xnor $lit1, $src2, $dst */
+ {
+ I960_INSN_XNOR1, "xnor1", "xnor", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* xnor $src1, $lit2, $dst */
+ {
+ I960_INSN_XNOR2, "xnor2", "xnor", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* xnor $lit1, $lit2, $dst */
+ {
+ I960_INSN_XNOR3, "xnor3", "xnor", 32,
+ { 0, { (1<<MACH_BASE) } }
},
/* not $src1, $src2, $dst */
{
I960_INSN_NOT, "not", "not", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* not $lit1, $src2, $dst */
{
I960_INSN_NOT1, "not1", "not", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* not $src1, $lit2, $dst */
{
I960_INSN_NOT2, "not2", "not", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* not $lit1, $lit2, $dst */
{
I960_INSN_NOT3, "not3", "not", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* ornot $src1, $src2, $dst */
+ {
+ I960_INSN_ORNOT, "ornot", "ornot", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* ornot $lit1, $src2, $dst */
+ {
+ I960_INSN_ORNOT1, "ornot1", "ornot", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* ornot $src1, $lit2, $dst */
+ {
+ I960_INSN_ORNOT2, "ornot2", "ornot", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* ornot $lit1, $lit2, $dst */
+ {
+ I960_INSN_ORNOT3, "ornot3", "ornot", 32,
+ { 0, { (1<<MACH_BASE) } }
},
/* clrbit $src1, $src2, $dst */
{
I960_INSN_CLRBIT, "clrbit", "clrbit", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* clrbit $lit1, $src2, $dst */
{
I960_INSN_CLRBIT1, "clrbit1", "clrbit", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* clrbit $src1, $lit2, $dst */
{
I960_INSN_CLRBIT2, "clrbit2", "clrbit", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* clrbit $lit1, $lit2, $dst */
{
I960_INSN_CLRBIT3, "clrbit3", "clrbit", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* shlo $src1, $src2, $dst */
{
I960_INSN_SHLO, "shlo", "shlo", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* shlo $lit1, $src2, $dst */
{
I960_INSN_SHLO1, "shlo1", "shlo", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* shlo $src1, $lit2, $dst */
{
I960_INSN_SHLO2, "shlo2", "shlo", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* shlo $lit1, $lit2, $dst */
{
I960_INSN_SHLO3, "shlo3", "shlo", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* shro $src1, $src2, $dst */
{
I960_INSN_SHRO, "shro", "shro", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* shro $lit1, $src2, $dst */
{
I960_INSN_SHRO1, "shro1", "shro", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* shro $src1, $lit2, $dst */
{
I960_INSN_SHRO2, "shro2", "shro", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* shro $lit1, $lit2, $dst */
{
I960_INSN_SHRO3, "shro3", "shro", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* shli $src1, $src2, $dst */
{
I960_INSN_SHLI, "shli", "shli", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* shli $lit1, $src2, $dst */
{
I960_INSN_SHLI1, "shli1", "shli", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* shli $src1, $lit2, $dst */
{
I960_INSN_SHLI2, "shli2", "shli", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* shli $lit1, $lit2, $dst */
{
I960_INSN_SHLI3, "shli3", "shli", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* shri $src1, $src2, $dst */
{
I960_INSN_SHRI, "shri", "shri", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* shri $lit1, $src2, $dst */
{
I960_INSN_SHRI1, "shri1", "shri", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* shri $src1, $lit2, $dst */
{
I960_INSN_SHRI2, "shri2", "shri", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* shri $lit1, $lit2, $dst */
{
I960_INSN_SHRI3, "shri3", "shri", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* emul $src1, $src2, $dst */
{
I960_INSN_EMUL, "emul", "emul", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* emul $lit1, $src2, $dst */
{
I960_INSN_EMUL1, "emul1", "emul", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* emul $src1, $lit2, $dst */
{
I960_INSN_EMUL2, "emul2", "emul", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* emul $lit1, $lit2, $dst */
{
I960_INSN_EMUL3, "emul3", "emul", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* mov $src1, $dst */
{
I960_INSN_MOV, "mov", "mov", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* mov $lit1, $dst */
{
I960_INSN_MOV1, "mov1", "mov", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* movl $src1, $dst */
{
I960_INSN_MOVL, "movl", "movl", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* movl $lit1, $dst */
{
I960_INSN_MOVL1, "movl1", "movl", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* movt $src1, $dst */
{
I960_INSN_MOVT, "movt", "movt", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* movt $lit1, $dst */
{
I960_INSN_MOVT1, "movt1", "movt", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* movq $src1, $dst */
{
I960_INSN_MOVQ, "movq", "movq", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* movq $lit1, $dst */
{
I960_INSN_MOVQ1, "movq1", "movq", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* modpc $src1, $src2, $dst */
{
I960_INSN_MODPC, "modpc", "modpc", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* modac $src1, $src2, $dst */
{
I960_INSN_MODAC, "modac", "modac", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* lda $offset, $dst */
{
I960_INSN_LDA_OFFSET, "lda-offset", "lda", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* lda $offset($abase), $dst */
{
I960_INSN_LDA_INDIRECT_OFFSET, "lda-indirect-offset", "lda", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* lda ($abase), $dst */
{
I960_INSN_LDA_INDIRECT, "lda-indirect", "lda", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* lda ($abase)[$index*S$scale], $dst */
{
I960_INSN_LDA_INDIRECT_INDEX, "lda-indirect-index", "lda", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* lda $optdisp, $dst */
{
I960_INSN_LDA_DISP, "lda-disp", "lda", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* lda $optdisp($abase), $dst */
{
I960_INSN_LDA_INDIRECT_DISP, "lda-indirect-disp", "lda", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* lda $optdisp[$index*S$scale], $dst */
{
I960_INSN_LDA_INDEX_DISP, "lda-index-disp", "lda", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* lda $optdisp($abase)[$index*S$scale], $dst */
{
I960_INSN_LDA_INDIRECT_INDEX_DISP, "lda-indirect-index-disp", "lda", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ld $offset, $dst */
{
I960_INSN_LD_OFFSET, "ld-offset", "ld", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ld $offset($abase), $dst */
{
I960_INSN_LD_INDIRECT_OFFSET, "ld-indirect-offset", "ld", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ld ($abase), $dst */
{
I960_INSN_LD_INDIRECT, "ld-indirect", "ld", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ld ($abase)[$index*S$scale], $dst */
{
I960_INSN_LD_INDIRECT_INDEX, "ld-indirect-index", "ld", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ld $optdisp, $dst */
{
I960_INSN_LD_DISP, "ld-disp", "ld", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ld $optdisp($abase), $dst */
{
I960_INSN_LD_INDIRECT_DISP, "ld-indirect-disp", "ld", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ld $optdisp[$index*S$scale], $dst */
{
I960_INSN_LD_INDEX_DISP, "ld-index-disp", "ld", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ld $optdisp($abase)[$index*S$scale], $dst */
{
I960_INSN_LD_INDIRECT_INDEX_DISP, "ld-indirect-index-disp", "ld", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldob $offset, $dst */
{
I960_INSN_LDOB_OFFSET, "ldob-offset", "ldob", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldob $offset($abase), $dst */
{
I960_INSN_LDOB_INDIRECT_OFFSET, "ldob-indirect-offset", "ldob", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldob ($abase), $dst */
{
I960_INSN_LDOB_INDIRECT, "ldob-indirect", "ldob", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldob ($abase)[$index*S$scale], $dst */
{
I960_INSN_LDOB_INDIRECT_INDEX, "ldob-indirect-index", "ldob", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldob $optdisp, $dst */
{
I960_INSN_LDOB_DISP, "ldob-disp", "ldob", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldob $optdisp($abase), $dst */
{
I960_INSN_LDOB_INDIRECT_DISP, "ldob-indirect-disp", "ldob", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldob $optdisp[$index*S$scale], $dst */
{
I960_INSN_LDOB_INDEX_DISP, "ldob-index-disp", "ldob", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldob $optdisp($abase)[$index*S$scale], $dst */
{
I960_INSN_LDOB_INDIRECT_INDEX_DISP, "ldob-indirect-index-disp", "ldob", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldos $offset, $dst */
{
I960_INSN_LDOS_OFFSET, "ldos-offset", "ldos", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldos $offset($abase), $dst */
{
I960_INSN_LDOS_INDIRECT_OFFSET, "ldos-indirect-offset", "ldos", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldos ($abase), $dst */
{
I960_INSN_LDOS_INDIRECT, "ldos-indirect", "ldos", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldos ($abase)[$index*S$scale], $dst */
{
I960_INSN_LDOS_INDIRECT_INDEX, "ldos-indirect-index", "ldos", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldos $optdisp, $dst */
{
I960_INSN_LDOS_DISP, "ldos-disp", "ldos", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldos $optdisp($abase), $dst */
{
I960_INSN_LDOS_INDIRECT_DISP, "ldos-indirect-disp", "ldos", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldos $optdisp[$index*S$scale], $dst */
{
I960_INSN_LDOS_INDEX_DISP, "ldos-index-disp", "ldos", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldos $optdisp($abase)[$index*S$scale], $dst */
{
I960_INSN_LDOS_INDIRECT_INDEX_DISP, "ldos-indirect-index-disp", "ldos", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldib $offset, $dst */
{
I960_INSN_LDIB_OFFSET, "ldib-offset", "ldib", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldib $offset($abase), $dst */
{
I960_INSN_LDIB_INDIRECT_OFFSET, "ldib-indirect-offset", "ldib", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldib ($abase), $dst */
{
I960_INSN_LDIB_INDIRECT, "ldib-indirect", "ldib", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldib ($abase)[$index*S$scale], $dst */
{
I960_INSN_LDIB_INDIRECT_INDEX, "ldib-indirect-index", "ldib", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldib $optdisp, $dst */
{
I960_INSN_LDIB_DISP, "ldib-disp", "ldib", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldib $optdisp($abase), $dst */
{
I960_INSN_LDIB_INDIRECT_DISP, "ldib-indirect-disp", "ldib", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldib $optdisp[$index*S$scale], $dst */
{
I960_INSN_LDIB_INDEX_DISP, "ldib-index-disp", "ldib", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldib $optdisp($abase)[$index*S$scale], $dst */
{
I960_INSN_LDIB_INDIRECT_INDEX_DISP, "ldib-indirect-index-disp", "ldib", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldis $offset, $dst */
{
I960_INSN_LDIS_OFFSET, "ldis-offset", "ldis", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldis $offset($abase), $dst */
{
I960_INSN_LDIS_INDIRECT_OFFSET, "ldis-indirect-offset", "ldis", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldis ($abase), $dst */
{
I960_INSN_LDIS_INDIRECT, "ldis-indirect", "ldis", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldis ($abase)[$index*S$scale], $dst */
{
I960_INSN_LDIS_INDIRECT_INDEX, "ldis-indirect-index", "ldis", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldis $optdisp, $dst */
{
I960_INSN_LDIS_DISP, "ldis-disp", "ldis", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldis $optdisp($abase), $dst */
{
I960_INSN_LDIS_INDIRECT_DISP, "ldis-indirect-disp", "ldis", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldis $optdisp[$index*S$scale], $dst */
{
I960_INSN_LDIS_INDEX_DISP, "ldis-index-disp", "ldis", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldis $optdisp($abase)[$index*S$scale], $dst */
{
I960_INSN_LDIS_INDIRECT_INDEX_DISP, "ldis-indirect-index-disp", "ldis", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldl $offset, $dst */
{
I960_INSN_LDL_OFFSET, "ldl-offset", "ldl", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldl $offset($abase), $dst */
{
I960_INSN_LDL_INDIRECT_OFFSET, "ldl-indirect-offset", "ldl", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldl ($abase), $dst */
{
I960_INSN_LDL_INDIRECT, "ldl-indirect", "ldl", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldl ($abase)[$index*S$scale], $dst */
{
I960_INSN_LDL_INDIRECT_INDEX, "ldl-indirect-index", "ldl", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldl $optdisp, $dst */
{
I960_INSN_LDL_DISP, "ldl-disp", "ldl", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldl $optdisp($abase), $dst */
{
I960_INSN_LDL_INDIRECT_DISP, "ldl-indirect-disp", "ldl", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldl $optdisp[$index*S$scale], $dst */
{
I960_INSN_LDL_INDEX_DISP, "ldl-index-disp", "ldl", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldl $optdisp($abase)[$index*S$scale], $dst */
{
I960_INSN_LDL_INDIRECT_INDEX_DISP, "ldl-indirect-index-disp", "ldl", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldt $offset, $dst */
{
I960_INSN_LDT_OFFSET, "ldt-offset", "ldt", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldt $offset($abase), $dst */
{
I960_INSN_LDT_INDIRECT_OFFSET, "ldt-indirect-offset", "ldt", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldt ($abase), $dst */
{
I960_INSN_LDT_INDIRECT, "ldt-indirect", "ldt", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldt ($abase)[$index*S$scale], $dst */
{
I960_INSN_LDT_INDIRECT_INDEX, "ldt-indirect-index", "ldt", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldt $optdisp, $dst */
{
I960_INSN_LDT_DISP, "ldt-disp", "ldt", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldt $optdisp($abase), $dst */
{
I960_INSN_LDT_INDIRECT_DISP, "ldt-indirect-disp", "ldt", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldt $optdisp[$index*S$scale], $dst */
{
I960_INSN_LDT_INDEX_DISP, "ldt-index-disp", "ldt", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldt $optdisp($abase)[$index*S$scale], $dst */
{
I960_INSN_LDT_INDIRECT_INDEX_DISP, "ldt-indirect-index-disp", "ldt", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldq $offset, $dst */
{
I960_INSN_LDQ_OFFSET, "ldq-offset", "ldq", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldq $offset($abase), $dst */
{
I960_INSN_LDQ_INDIRECT_OFFSET, "ldq-indirect-offset", "ldq", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldq ($abase), $dst */
{
I960_INSN_LDQ_INDIRECT, "ldq-indirect", "ldq", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldq ($abase)[$index*S$scale], $dst */
{
I960_INSN_LDQ_INDIRECT_INDEX, "ldq-indirect-index", "ldq", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldq $optdisp, $dst */
{
I960_INSN_LDQ_DISP, "ldq-disp", "ldq", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldq $optdisp($abase), $dst */
{
I960_INSN_LDQ_INDIRECT_DISP, "ldq-indirect-disp", "ldq", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldq $optdisp[$index*S$scale], $dst */
{
I960_INSN_LDQ_INDEX_DISP, "ldq-index-disp", "ldq", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* ldq $optdisp($abase)[$index*S$scale], $dst */
{
I960_INSN_LDQ_INDIRECT_INDEX_DISP, "ldq-indirect-index-disp", "ldq", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* st $st_src, $offset */
{
I960_INSN_ST_OFFSET, "st-offset", "st", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* st $st_src, $offset($abase) */
{
I960_INSN_ST_INDIRECT_OFFSET, "st-indirect-offset", "st", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* st $st_src, ($abase) */
{
I960_INSN_ST_INDIRECT, "st-indirect", "st", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* st $st_src, ($abase)[$index*S$scale] */
{
I960_INSN_ST_INDIRECT_INDEX, "st-indirect-index", "st", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* st $st_src, $optdisp */
{
I960_INSN_ST_DISP, "st-disp", "st", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* st $st_src, $optdisp($abase) */
{
I960_INSN_ST_INDIRECT_DISP, "st-indirect-disp", "st", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* st $st_src, $optdisp[$index*S$scale */
{
I960_INSN_ST_INDEX_DISP, "st-index-disp", "st", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* st $st_src, $optdisp($abase)[$index*S$scale] */
{
I960_INSN_ST_INDIRECT_INDEX_DISP, "st-indirect-index-disp", "st", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* stob $st_src, $offset */
{
I960_INSN_STOB_OFFSET, "stob-offset", "stob", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* stob $st_src, $offset($abase) */
{
I960_INSN_STOB_INDIRECT_OFFSET, "stob-indirect-offset", "stob", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* stob $st_src, ($abase) */
{
I960_INSN_STOB_INDIRECT, "stob-indirect", "stob", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* stob $st_src, ($abase)[$index*S$scale] */
{
I960_INSN_STOB_INDIRECT_INDEX, "stob-indirect-index", "stob", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* stob $st_src, $optdisp */
{
I960_INSN_STOB_DISP, "stob-disp", "stob", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* stob $st_src, $optdisp($abase) */
{
I960_INSN_STOB_INDIRECT_DISP, "stob-indirect-disp", "stob", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* stob $st_src, $optdisp[$index*S$scale */
{
I960_INSN_STOB_INDEX_DISP, "stob-index-disp", "stob", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* stob $st_src, $optdisp($abase)[$index*S$scale] */
{
I960_INSN_STOB_INDIRECT_INDEX_DISP, "stob-indirect-index-disp", "stob", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* stos $st_src, $offset */
{
I960_INSN_STOS_OFFSET, "stos-offset", "stos", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* stos $st_src, $offset($abase) */
{
I960_INSN_STOS_INDIRECT_OFFSET, "stos-indirect-offset", "stos", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* stos $st_src, ($abase) */
{
I960_INSN_STOS_INDIRECT, "stos-indirect", "stos", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* stos $st_src, ($abase)[$index*S$scale] */
{
I960_INSN_STOS_INDIRECT_INDEX, "stos-indirect-index", "stos", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* stos $st_src, $optdisp */
{
I960_INSN_STOS_DISP, "stos-disp", "stos", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* stos $st_src, $optdisp($abase) */
{
I960_INSN_STOS_INDIRECT_DISP, "stos-indirect-disp", "stos", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* stos $st_src, $optdisp[$index*S$scale */
{
I960_INSN_STOS_INDEX_DISP, "stos-index-disp", "stos", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* stos $st_src, $optdisp($abase)[$index*S$scale] */
{
I960_INSN_STOS_INDIRECT_INDEX_DISP, "stos-indirect-index-disp", "stos", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* stl $st_src, $offset */
{
I960_INSN_STL_OFFSET, "stl-offset", "stl", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* stl $st_src, $offset($abase) */
{
I960_INSN_STL_INDIRECT_OFFSET, "stl-indirect-offset", "stl", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* stl $st_src, ($abase) */
{
I960_INSN_STL_INDIRECT, "stl-indirect", "stl", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* stl $st_src, ($abase)[$index*S$scale] */
{
I960_INSN_STL_INDIRECT_INDEX, "stl-indirect-index", "stl", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* stl $st_src, $optdisp */
{
I960_INSN_STL_DISP, "stl-disp", "stl", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* stl $st_src, $optdisp($abase) */
{
I960_INSN_STL_INDIRECT_DISP, "stl-indirect-disp", "stl", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* stl $st_src, $optdisp[$index*S$scale */
{
I960_INSN_STL_INDEX_DISP, "stl-index-disp", "stl", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* stl $st_src, $optdisp($abase)[$index*S$scale] */
{
I960_INSN_STL_INDIRECT_INDEX_DISP, "stl-indirect-index-disp", "stl", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* stt $st_src, $offset */
{
I960_INSN_STT_OFFSET, "stt-offset", "stt", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* stt $st_src, $offset($abase) */
{
I960_INSN_STT_INDIRECT_OFFSET, "stt-indirect-offset", "stt", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* stt $st_src, ($abase) */
{
I960_INSN_STT_INDIRECT, "stt-indirect", "stt", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* stt $st_src, ($abase)[$index*S$scale] */
{
I960_INSN_STT_INDIRECT_INDEX, "stt-indirect-index", "stt", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* stt $st_src, $optdisp */
{
I960_INSN_STT_DISP, "stt-disp", "stt", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* stt $st_src, $optdisp($abase) */
{
I960_INSN_STT_INDIRECT_DISP, "stt-indirect-disp", "stt", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* stt $st_src, $optdisp[$index*S$scale */
{
I960_INSN_STT_INDEX_DISP, "stt-index-disp", "stt", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* stt $st_src, $optdisp($abase)[$index*S$scale] */
{
I960_INSN_STT_INDIRECT_INDEX_DISP, "stt-indirect-index-disp", "stt", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* stq $st_src, $offset */
{
I960_INSN_STQ_OFFSET, "stq-offset", "stq", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* stq $st_src, $offset($abase) */
{
I960_INSN_STQ_INDIRECT_OFFSET, "stq-indirect-offset", "stq", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* stq $st_src, ($abase) */
{
I960_INSN_STQ_INDIRECT, "stq-indirect", "stq", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* stq $st_src, ($abase)[$index*S$scale] */
{
I960_INSN_STQ_INDIRECT_INDEX, "stq-indirect-index", "stq", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* stq $st_src, $optdisp */
{
I960_INSN_STQ_DISP, "stq-disp", "stq", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* stq $st_src, $optdisp($abase) */
{
I960_INSN_STQ_INDIRECT_DISP, "stq-indirect-disp", "stq", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* stq $st_src, $optdisp[$index*S$scale */
{
I960_INSN_STQ_INDEX_DISP, "stq-index-disp", "stq", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* stq $st_src, $optdisp($abase)[$index*S$scale] */
{
I960_INSN_STQ_INDIRECT_INDEX_DISP, "stq-indirect-index-disp", "stq", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* cmpobe $br_src1, $br_src2, $br_disp */
{
I960_INSN_CMPOBE_REG, "cmpobe-reg", "cmpobe", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpobe $br_lit1, $br_src2, $br_disp */
{
I960_INSN_CMPOBE_LIT, "cmpobe-lit", "cmpobe", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpobne $br_src1, $br_src2, $br_disp */
{
I960_INSN_CMPOBNE_REG, "cmpobne-reg", "cmpobne", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpobne $br_lit1, $br_src2, $br_disp */
{
I960_INSN_CMPOBNE_LIT, "cmpobne-lit", "cmpobne", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpobl $br_src1, $br_src2, $br_disp */
{
I960_INSN_CMPOBL_REG, "cmpobl-reg", "cmpobl", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpobl $br_lit1, $br_src2, $br_disp */
{
I960_INSN_CMPOBL_LIT, "cmpobl-lit", "cmpobl", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpoble $br_src1, $br_src2, $br_disp */
{
I960_INSN_CMPOBLE_REG, "cmpoble-reg", "cmpoble", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpoble $br_lit1, $br_src2, $br_disp */
{
I960_INSN_CMPOBLE_LIT, "cmpoble-lit", "cmpoble", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpobg $br_src1, $br_src2, $br_disp */
{
I960_INSN_CMPOBG_REG, "cmpobg-reg", "cmpobg", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpobg $br_lit1, $br_src2, $br_disp */
{
I960_INSN_CMPOBG_LIT, "cmpobg-lit", "cmpobg", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpobge $br_src1, $br_src2, $br_disp */
{
I960_INSN_CMPOBGE_REG, "cmpobge-reg", "cmpobge", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpobge $br_lit1, $br_src2, $br_disp */
{
I960_INSN_CMPOBGE_LIT, "cmpobge-lit", "cmpobge", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpibe $br_src1, $br_src2, $br_disp */
{
I960_INSN_CMPIBE_REG, "cmpibe-reg", "cmpibe", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpibe $br_lit1, $br_src2, $br_disp */
{
I960_INSN_CMPIBE_LIT, "cmpibe-lit", "cmpibe", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpibne $br_src1, $br_src2, $br_disp */
{
I960_INSN_CMPIBNE_REG, "cmpibne-reg", "cmpibne", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpibne $br_lit1, $br_src2, $br_disp */
{
I960_INSN_CMPIBNE_LIT, "cmpibne-lit", "cmpibne", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpibl $br_src1, $br_src2, $br_disp */
{
I960_INSN_CMPIBL_REG, "cmpibl-reg", "cmpibl", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpibl $br_lit1, $br_src2, $br_disp */
{
I960_INSN_CMPIBL_LIT, "cmpibl-lit", "cmpibl", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpible $br_src1, $br_src2, $br_disp */
{
I960_INSN_CMPIBLE_REG, "cmpible-reg", "cmpible", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpible $br_lit1, $br_src2, $br_disp */
{
I960_INSN_CMPIBLE_LIT, "cmpible-lit", "cmpible", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpibg $br_src1, $br_src2, $br_disp */
{
I960_INSN_CMPIBG_REG, "cmpibg-reg", "cmpibg", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpibg $br_lit1, $br_src2, $br_disp */
{
I960_INSN_CMPIBG_LIT, "cmpibg-lit", "cmpibg", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpibge $br_src1, $br_src2, $br_disp */
{
I960_INSN_CMPIBGE_REG, "cmpibge-reg", "cmpibge", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpibge $br_lit1, $br_src2, $br_disp */
{
I960_INSN_CMPIBGE_LIT, "cmpibge-lit", "cmpibge", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* bbc $br_src1, $br_src2, $br_disp */
{
I960_INSN_BBC_REG, "bbc-reg", "bbc", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* bbc $br_lit1, $br_src2, $br_disp */
{
I960_INSN_BBC_LIT, "bbc-lit", "bbc", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* bbs $br_src1, $br_src2, $br_disp */
{
I960_INSN_BBS_REG, "bbs-reg", "bbs", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* bbs $br_lit1, $br_src2, $br_disp */
{
I960_INSN_BBS_LIT, "bbs-lit", "bbs", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpi $src1, $src2 */
{
I960_INSN_CMPI, "cmpi", "cmpi", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* cmpi $lit1, $src2 */
{
I960_INSN_CMPI1, "cmpi1", "cmpi", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* cmpi $src1, $lit2 */
{
I960_INSN_CMPI2, "cmpi2", "cmpi", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* cmpi $lit1, $lit2 */
{
I960_INSN_CMPI3, "cmpi3", "cmpi", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* cmpo $src1, $src2 */
{
I960_INSN_CMPO, "cmpo", "cmpo", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* cmpo $lit1, $src2 */
{
I960_INSN_CMPO1, "cmpo1", "cmpo", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* cmpo $src1, $lit2 */
{
I960_INSN_CMPO2, "cmpo2", "cmpo", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* cmpo $lit1, $lit2 */
{
I960_INSN_CMPO3, "cmpo3", "cmpo", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* testno $br_src1 */
{
I960_INSN_TESTNO_REG, "testno-reg", "testno", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* testg $br_src1 */
{
I960_INSN_TESTG_REG, "testg-reg", "testg", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* teste $br_src1 */
{
I960_INSN_TESTE_REG, "teste-reg", "teste", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* testge $br_src1 */
{
I960_INSN_TESTGE_REG, "testge-reg", "testge", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* testl $br_src1 */
{
I960_INSN_TESTL_REG, "testl-reg", "testl", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* testne $br_src1 */
{
I960_INSN_TESTNE_REG, "testne-reg", "testne", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* testle $br_src1 */
{
I960_INSN_TESTLE_REG, "testle-reg", "testle", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* testo $br_src1 */
{
I960_INSN_TESTO_REG, "testo-reg", "testo", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
/* bno $ctrl_disp */
{
I960_INSN_BNO, "bno", "bno", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* bg $ctrl_disp */
{
I960_INSN_BG, "bg", "bg", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* be $ctrl_disp */
{
I960_INSN_BE, "be", "be", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* bge $ctrl_disp */
{
I960_INSN_BGE, "bge", "bge", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* bl $ctrl_disp */
{
I960_INSN_BL, "bl", "bl", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* bne $ctrl_disp */
{
I960_INSN_BNE, "bne", "bne", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* ble $ctrl_disp */
{
I960_INSN_BLE, "ble", "ble", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* bo $ctrl_disp */
{
I960_INSN_BO, "bo", "bo", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* b $ctrl_disp */
{
I960_INSN_B, "b", "b", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* bx $offset($abase) */
{
I960_INSN_BX_INDIRECT_OFFSET, "bx-indirect-offset", "bx", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* bx ($abase) */
{
I960_INSN_BX_INDIRECT, "bx-indirect", "bx", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* bx ($abase)[$index*S$scale] */
{
I960_INSN_BX_INDIRECT_INDEX, "bx-indirect-index", "bx", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* bx $optdisp */
{
I960_INSN_BX_DISP, "bx-disp", "bx", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* bx $optdisp($abase) */
{
I960_INSN_BX_INDIRECT_DISP, "bx-indirect-disp", "bx", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* callx $optdisp */
{
I960_INSN_CALLX_DISP, "callx-disp", "callx", 64,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* callx ($abase) */
{
I960_INSN_CALLX_INDIRECT, "callx-indirect", "callx", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* callx $offset($abase) */
{
I960_INSN_CALLX_INDIRECT_OFFSET, "callx-indirect-offset", "callx", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* ret */
{
I960_INSN_RET, "ret", "ret", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* calls $src1 */
{
I960_INSN_CALLS, "calls", "calls", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* fmark */
{
I960_INSN_FMARK, "fmark", "fmark", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+ { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* flushreg */
{
I960_INSN_FLUSHREG, "flushreg", "flushreg", 32,
- { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
+ { 0, { (1<<MACH_BASE) } }
},
};
@@ -1714,21 +1773,217 @@ static const CGEN_IBASE i960_cgen_insn_table[MAX_INSNS] =
#undef MNEM
#undef OP
+/* Initialize anything needed to be done once, before any cpu_open call. */
+
static void
init_tables ()
{
}
+/* Subroutine of i960_cgen_cpu_open to look up a mach via its bfd name. */
+
+static const CGEN_MACH *
+lookup_mach_via_bfd_name (table, name)
+ const CGEN_MACH *table;
+ const char *name;
+{
+ while (table->name)
+ {
+ if (strcmp (name, table->bfd_name) == 0)
+ return table;
+ ++table;
+ }
+ abort ();
+}
+
+/* Subroutine of i960_cgen_cpu_open to build the hardware table. */
+
+static void
+build_hw_table (cd)
+ CGEN_CPU_TABLE *cd;
+{
+ int i;
+ int machs = cd->machs;
+ const CGEN_HW_ENTRY *init = & i960_cgen_hw_table[0];
+ /* MAX_HW is only an upper bound on the number of selected entries.
+ However each entry is indexed by it's enum so there can be holes in
+ the table. */
+ const CGEN_HW_ENTRY **selected =
+ (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
+
+ cd->hw_table.init_entries = init;
+ cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
+ memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
+ /* ??? For now we just use machs to determine which ones we want. */
+ for (i = 0; init[i].name != NULL; ++i)
+ if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
+ & machs)
+ selected[init[i].type] = &init[i];
+ cd->hw_table.entries = selected;
+ cd->hw_table.num_entries = MAX_HW;
+}
+
+/* Subroutine of i960_cgen_cpu_open to build the hardware table. */
+
+static void
+build_ifield_table (cd)
+ CGEN_CPU_TABLE *cd;
+{
+ cd->ifld_table = & i960_cgen_ifld_table[0];
+}
+
+/* Subroutine of i960_cgen_cpu_open to build the hardware table. */
+
+static void
+build_operand_table (cd)
+ CGEN_CPU_TABLE *cd;
+{
+ int i;
+ int machs = cd->machs;
+ const CGEN_OPERAND *init = & i960_cgen_operand_table[0];
+ /* MAX_OPERANDS is only an upper bound on the number of selected entries.
+ However each entry is indexed by it's enum so there can be holes in
+ the table. */
+ const CGEN_OPERAND **selected =
+ (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
+
+ cd->operand_table.init_entries = init;
+ cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
+ memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
+ /* ??? For now we just use mach to determine which ones we want. */
+ for (i = 0; init[i].name != NULL; ++i)
+ if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
+ & machs)
+ selected[init[i].type] = &init[i];
+ cd->operand_table.entries = selected;
+ cd->operand_table.num_entries = MAX_OPERANDS;
+}
+
+/* Subroutine of i960_cgen_cpu_open to build the hardware table.
+ ??? This could leave out insns not supported by the specified mach/isa,
+ but that would cause errors like "foo only supported by bar" to become
+ "unknown insn", so for now we include all insns and require the app to
+ do the checking later.
+ ??? On the other hand, parsing of such insns may require their hardware or
+ operand elements to be in the table [which they mightn't be]. */
+
+static void
+build_insn_table (cd)
+ CGEN_CPU_TABLE *cd;
+{
+ int i;
+ const CGEN_IBASE *ib = & i960_cgen_insn_table[0];
+ CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
+
+ memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
+ for (i = 0; i < MAX_INSNS; ++i)
+ insns[i].base = &ib[i];
+ cd->insn_table.init_entries = insns;
+ cd->insn_table.entry_size = sizeof (CGEN_IBASE);
+ cd->insn_table.num_init_entries = MAX_INSNS;
+}
+
+/* Subroutine of i960_cgen_cpu_open to rebuild the tables.
+ This is also called by cgen_set_cpu (via an entry in CD). */
+
+static void
+i960_cgen_rebuild_tables (cd)
+ CGEN_CPU_TABLE *cd;
+{
+ int i,n_isas,n_machs;
+ unsigned int isas = cd->isas;
+ unsigned int machs = cd->machs;
+
+ cd->int_insn_p = CGEN_INT_INSN_P;
+
+ /* Data derived from the isa spec. */
+#define UNSET (CGEN_SIZE_UNKNOWN + 1)
+ cd->default_insn_bitsize = UNSET;
+ cd->base_insn_bitsize = UNSET;
+ cd->min_insn_bitsize = 65535; /* some ridiculously big number */
+ cd->max_insn_bitsize = 0;
+ for (i = 0; i < MAX_ISAS; ++i)
+ if (((1 << i) & isas) != 0)
+ {
+ const CGEN_ISA *isa = & i960_cgen_isa_table[i];
+
+ /* Default insn sizes of all selected isas must be equal or we set
+ the result to 0, meaning "unknown". */
+ if (cd->default_insn_bitsize == UNSET)
+ cd->default_insn_bitsize = isa->default_insn_bitsize;
+ else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
+ ; /* this is ok */
+ else
+ cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
+
+ /* Base insn sizes of all selected isas must be equal or we set
+ the result to 0, meaning "unknown". */
+ if (cd->base_insn_bitsize == UNSET)
+ cd->base_insn_bitsize = isa->base_insn_bitsize;
+ else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
+ ; /* this is ok */
+ else
+ cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
+
+ /* Set min,max insn sizes. */
+ if (isa->min_insn_bitsize < cd->min_insn_bitsize)
+ cd->min_insn_bitsize = isa->min_insn_bitsize;
+ if (isa->max_insn_bitsize > cd->max_insn_bitsize)
+ cd->max_insn_bitsize = isa->max_insn_bitsize;
+
+ ++n_isas;
+ }
+
+ /* Data derived from the mach spec. */
+ for (i = 0; i < MAX_MACHS; ++i)
+ if (((1 << i) & machs) != 0)
+ {
+ const CGEN_MACH *mach = & i960_cgen_mach_table[i];
+
+ ++n_machs;
+ }
+
+ /* Determine which hw elements are used by MACH. */
+ build_hw_table (cd);
+
+ /* Build the ifield table. */
+ build_ifield_table (cd);
+
+ /* Determine which operands are used by MACH/ISA. */
+ build_operand_table (cd);
+
+ /* Build the instruction table. */
+ build_insn_table (cd);
+}
+
/* Initialize a cpu table and return a descriptor.
- It's much like opening a file, and must be the first function called. */
+ It's much like opening a file, and must be the first function called.
+ The arguments are a set of (type/value) pairs, terminated with
+ CGEN_CPU_OPEN_END.
+
+ Currently supported values:
+ CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
+ CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
+ CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
+ CGEN_CPU_OPEN_ENDIAN: specify endian choice
+ CGEN_CPU_OPEN_END: terminates arguments
+
+ ??? Simultaneous multiple isas might not make sense, but it's not (yet)
+ precluded.
+
+ ??? We only support ISO C stdargs here, not K&R.
+ Laziness, plus experiment to see if anything requires K&R - eventually
+ K&R will no longer be supported - e.g. GDB is currently trying this. */
CGEN_CPU_DESC
-i960_cgen_cpu_open (mach, endian)
- int mach;
- enum cgen_endian endian;
+i960_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
{
CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
static int init_p;
+ unsigned int isas = 0; /* 0 = "unspecified" */
+ unsigned int machs = 0; /* 0 = "unspecified" */
+ enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
+ va_list ap;
if (! init_p)
{
@@ -1738,7 +1993,55 @@ i960_cgen_cpu_open (mach, endian)
memset (cd, 0, sizeof (*cd));
- cd->mach = mach;
+ va_start (ap, arg_type);
+ while (arg_type != CGEN_CPU_OPEN_END)
+ {
+ switch (arg_type)
+ {
+ case CGEN_CPU_OPEN_ISAS :
+ isas = va_arg (ap, unsigned int);
+ break;
+ case CGEN_CPU_OPEN_MACHS :
+ machs = va_arg (ap, unsigned int);
+ break;
+ case CGEN_CPU_OPEN_BFDMACH :
+ {
+ const char *name = va_arg (ap, const char *);
+ const CGEN_MACH *mach =
+ lookup_mach_via_bfd_name (i960_cgen_mach_table, name);
+
+ machs |= mach->num << 1;
+ break;
+ }
+ case CGEN_CPU_OPEN_ENDIAN :
+ endian = va_arg (ap, enum cgen_endian);
+ break;
+ default :
+ fprintf (stderr, "i960_cgen_cpu_open: unsupported argument `%d'\n",
+ arg_type);
+ abort (); /* ??? return NULL? */
+ }
+ arg_type = va_arg (ap, enum cgen_cpu_open_arg);
+ }
+ va_end (ap);
+
+ /* mach unspecified means "all" */
+ if (machs == 0)
+ machs = (1 << MAX_MACHS) - 1;
+ /* base mach is always selected */
+ machs |= 1;
+ /* isa unspecified means "all" */
+ if (isas == 0)
+ isas = (1 << MAX_ISAS) - 1;
+ if (endian == CGEN_ENDIAN_UNKNOWN)
+ {
+ /* ??? If target has only one, could have a default. */
+ fprintf (stderr, "i960_cgen_cpu_open: no endianness specified\n");
+ abort ();
+ }
+
+ cd->isas = isas;
+ cd->machs = machs;
cd->endian = endian;
/* FIXME: for the sparc case we can determine insn-endianness statically.
The worry here is where both data and insn endian can be independently
@@ -1746,32 +2049,30 @@ i960_cgen_cpu_open (mach, endian)
Actually, will want to allow for more arguments in the future anyway. */
cd->insn_endian = endian;
- cd->int_insn_p = CGEN_INT_INSN_P;
+ /* Table (re)builder. */
+ cd->rebuild_tables = i960_cgen_rebuild_tables;
+ i960_cgen_rebuild_tables (cd);
- cd->max_insn_size = CGEN_MAX_INSN_SIZE;
-
- cd->hw_list = & i960_cgen_hw_table[0];
-
- cd->ifld_table = & i960_cgen_ifld_table[0];
+ return (CGEN_CPU_DESC) cd;
+}
- cd->operand_table = & i960_cgen_operand_table[0];
+/* Cover fn to i960_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
+ MACH_NAME is the bfd name of the mach. */
- {
- int i;
- const CGEN_IBASE *ib = & i960_cgen_insn_table[0];
- CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
- memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
- for (i = 0; i < MAX_INSNS; ++i)
- insns[i].base = &ib[i];
- cd->insn_table.init_entries = insns;
- }
- cd->insn_table.entry_size = sizeof (CGEN_IBASE);
- cd->insn_table.num_init_entries = MAX_INSNS;
-
- return (CGEN_CPU_DESC) cd;
+CGEN_CPU_DESC
+i960_cgen_cpu_open_1 (mach_name, endian)
+ const char *mach_name;
+ enum cgen_endian endian;
+{
+ return i960_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
+ CGEN_CPU_OPEN_ENDIAN, endian,
+ CGEN_CPU_OPEN_END);
}
-/* Close a cpu table. */
+/* Close a cpu table.
+ ??? This can live in a machine independent file, but there's currently
+ no place to put this file (there's no libcgen). libopcodes is the wrong
+ place as some simulator ports use this but they don't use libopcodes. */
void
i960_cgen_cpu_close (cd)
@@ -1779,6 +2080,8 @@ i960_cgen_cpu_close (cd)
{
if (cd->insn_table.init_entries)
free ((CGEN_INSN *) cd->insn_table.init_entries);
+ if (cd->hw_table.entries)
+ free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
free (cd);
}
diff --git a/sim/i960/i960-desc.h b/sim/i960/i960-desc.h
index 7a3310f..75b3d63 100644
--- a/sim/i960/i960-desc.h
+++ b/sim/i960/i960-desc.h
@@ -34,15 +34,10 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#define HAVE_CPU_I960BASE
#define CGEN_INSN_LSB0_P 0
-#define CGEN_WORD_BITSIZE 32
-#define CGEN_DEFAULT_INSN_BITSIZE 32
-#define CGEN_BASE_INSN_BITSIZE 32
-#define CGEN_MIN_INSN_BITSIZE 32
-#define CGEN_MAX_INSN_BITSIZE 64
-#define CGEN_DEFAULT_INSN_SIZE (CGEN_DEFAULT_INSN_BITSIZE / 8)
-#define CGEN_BASE_INSN_SIZE (CGEN_BASE_INSN_BITSIZE / 8)
-#define CGEN_MIN_INSN_SIZE (CGEN_MIN_INSN_BITSIZE / 8)
-#define CGEN_MAX_INSN_SIZE (CGEN_MAX_INSN_BITSIZE / 8)
+
+/* Maximum size of any insn (in bytes). */
+#define CGEN_MAX_INSN_SIZE 8
+
#define CGEN_INT_INSN_P 0
/* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES. */
@@ -193,24 +188,6 @@ typedef enum insn_ctrl_zero {
CTRL_ZERO_0
} INSN_CTRL_ZERO;
-/* Enum declaration for general registers. */
-typedef enum h_gr {
- H_GR_FP = 31, H_GR_SP = 1, H_GR_R0 = 0, H_GR_R1 = 1
- , H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4, H_GR_R5 = 5
- , H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8, H_GR_R9 = 9
- , H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12, H_GR_R13 = 13
- , H_GR_R14 = 14, H_GR_R15 = 15, H_GR_G0 = 16, H_GR_G1 = 17
- , H_GR_G2 = 18, H_GR_G3 = 19, H_GR_G4 = 20, H_GR_G5 = 21
- , H_GR_G6 = 22, H_GR_G7 = 23, H_GR_G8 = 24, H_GR_G9 = 25
- , H_GR_G10 = 26, H_GR_G11 = 27, H_GR_G12 = 28, H_GR_G13 = 29
- , H_GR_G14 = 30, H_GR_G15 = 31
-} H_GR;
-
-/* Enum declaration for condition code. */
-typedef enum h_cc {
- H_CC_CC
-} H_CC;
-
/* Attributes. */
/* Enum declaration for machine type selection. */
@@ -218,7 +195,13 @@ typedef enum mach_attr {
MACH_BASE, MACH_I960_KA_SA, MACH_I960_CA, MACH_MAX
} MACH_ATTR;
+/* Enum declaration for instruction set selection. */
+typedef enum isa_attr {
+ ISA_I960, ISA_MAX
+} ISA_ATTR;
+
/* Number of architecture variants. */
+#define MAX_ISAS 1
#define MAX_MACHS ((int) MACH_MAX)
/* Ifield support. */
@@ -229,13 +212,13 @@ extern const struct cgen_ifld i960_cgen_ifld_table[];
/* Enum declaration for cgen_ifld attrs. */
typedef enum cgen_ifld_attr {
- CGEN_IFLD_MACH, CGEN_IFLD_NBOOLS, CGEN_IFLD_START_BOOL = 31, CGEN_IFLD_VIRTUAL
- , CGEN_IFLD_UNSIGNED, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
- , CGEN_IFLD_SIGN_OPT
+ CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
+ , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
+ , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
} CGEN_IFLD_ATTR;
-/* Number of non-boolean elements in cgen_ifld. */
-#define CGEN_IFLD_NBOOL_ATTRS ((int) CGEN_IFLD_NBOOLS)
+/* Number of non-boolean elements in cgen_ifld_attr. */
+#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
/* Enum declaration for i960 ifield types. */
typedef enum ifield_type {
@@ -254,20 +237,19 @@ typedef enum ifield_type {
/* Enum declaration for cgen_hw attrs. */
typedef enum cgen_hw_attr {
- CGEN_HW_MACH, CGEN_HW_NBOOLS, CGEN_HW_START_BOOL = 31, CGEN_HW_VIRTUAL
- , CGEN_HW_UNSIGNED, CGEN_HW_SIGNED, CGEN_HW_CACHE_ADDR, CGEN_HW_FUN_ACCESS
- , CGEN_HW_PC, CGEN_HW_PROFILE
+ CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
+ , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
} CGEN_HW_ATTR;
-/* Number of non-boolean elements in cgen_hw. */
-#define CGEN_HW_NBOOL_ATTRS ((int) CGEN_HW_NBOOLS)
+/* Number of non-boolean elements in cgen_hw_attr. */
+#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
/* Enum declaration for i960 hardware types. */
-typedef enum hw_type {
- HW_H_PC, HW_H_MEMORY, HW_H_SINT, HW_H_UINT
- , HW_H_ADDR, HW_H_IADDR, HW_H_GR, HW_H_CC
+typedef enum cgen_hw_type {
+ HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
+ , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_CC
, HW_MAX
-} HW_TYPE;
+} CGEN_HW_TYPE;
#define MAX_HW ((int) HW_MAX)
@@ -275,13 +257,13 @@ typedef enum hw_type {
/* Enum declaration for cgen_operand attrs. */
typedef enum cgen_operand_attr {
- CGEN_OPERAND_MACH, CGEN_OPERAND_NBOOLS, CGEN_OPERAND_START_BOOL = 31, CGEN_OPERAND_VIRTUAL
- , CGEN_OPERAND_UNSIGNED, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
- , CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
+ CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
+ , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
+ , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
} CGEN_OPERAND_ATTR;
-/* Number of non-boolean elements in cgen_operand. */
-#define CGEN_OPERAND_NBOOL_ATTRS ((int) CGEN_OPERAND_NBOOLS)
+/* Number of non-boolean elements in cgen_operand_attr. */
+#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
/* Enum declaration for i960 operand types. */
typedef enum cgen_operand_type {
@@ -302,20 +284,21 @@ typedef enum cgen_operand_type {
/* Enum declaration for cgen_insn attrs. */
typedef enum cgen_insn_attr {
- CGEN_INSN_MACH, CGEN_INSN_NBOOLS, CGEN_INSN_START_BOOL = 31, CGEN_INSN_ALIAS
- , CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI, CGEN_INSN_SKIP_CTI
- , CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX, CGEN_INSN_NO_DIS
- , CGEN_INSN_PBB
+ CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
+ , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX
+ , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31
+ , CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
} CGEN_INSN_ATTR;
-/* Number of non-boolean elements in cgen_insn. */
-#define CGEN_INSN_NBOOL_ATTRS ((int) CGEN_INSN_NBOOLS)
+/* Number of non-boolean elements in cgen_insn_attr. */
+#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
/* cgen.h uses things we just defined. */
#include "opcode/cgen.h"
/* Attributes. */
-extern const CGEN_ATTR_TABLE i960_cgen_hw_attr_table[];
+extern const CGEN_ATTR_TABLE i960_cgen_hardware_attr_table[];
+extern const CGEN_ATTR_TABLE i960_cgen_ifield_attr_table[];
extern const CGEN_ATTR_TABLE i960_cgen_operand_attr_table[];
extern const CGEN_ATTR_TABLE i960_cgen_insn_attr_table[];
@@ -324,18 +307,6 @@ extern const CGEN_ATTR_TABLE i960_cgen_insn_attr_table[];
extern CGEN_KEYWORD i960_cgen_opval_h_gr;
extern CGEN_KEYWORD i960_cgen_opval_h_cc;
-#define CGEN_INIT_PARSE(od) \
-{\
-}
-#define CGEN_INIT_INSERT(od) \
-{\
-}
-#define CGEN_INIT_EXTRACT(od) \
-{\
-}
-#define CGEN_INIT_PRINT(od) \
-{\
-}
diff --git a/sim/i960/i960-opc.h b/sim/i960/i960-opc.h
index a454ab3..0b9da78 100644
--- a/sim/i960/i960-opc.h
+++ b/sim/i960/i960-opc.h
@@ -54,8 +54,10 @@ typedef enum cgen_insn_type {
, I960_INSN_NOTAND3, I960_INSN_XOR, I960_INSN_XOR1, I960_INSN_XOR2
, I960_INSN_XOR3, I960_INSN_OR, I960_INSN_OR1, I960_INSN_OR2
, I960_INSN_OR3, I960_INSN_NOR, I960_INSN_NOR1, I960_INSN_NOR2
- , I960_INSN_NOR3, I960_INSN_NOT, I960_INSN_NOT1, I960_INSN_NOT2
- , I960_INSN_NOT3, I960_INSN_CLRBIT, I960_INSN_CLRBIT1, I960_INSN_CLRBIT2
+ , I960_INSN_NOR3, I960_INSN_XNOR, I960_INSN_XNOR1, I960_INSN_XNOR2
+ , I960_INSN_XNOR3, I960_INSN_NOT, I960_INSN_NOT1, I960_INSN_NOT2
+ , I960_INSN_NOT3, I960_INSN_ORNOT, I960_INSN_ORNOT1, I960_INSN_ORNOT2
+ , I960_INSN_ORNOT3, I960_INSN_CLRBIT, I960_INSN_CLRBIT1, I960_INSN_CLRBIT2
, I960_INSN_CLRBIT3, I960_INSN_SHLO, I960_INSN_SHLO1, I960_INSN_SHLO2
, I960_INSN_SHLO3, I960_INSN_SHRO, I960_INSN_SHRO1, I960_INSN_SHRO2
, I960_INSN_SHRO3, I960_INSN_SHLI, I960_INSN_SHLI1, I960_INSN_SHLI2
@@ -151,6 +153,18 @@ struct cgen_fields
long f_ctrl_zero;
};
+#define CGEN_INIT_PARSE(od) \
+{\
+}
+#define CGEN_INIT_INSERT(od) \
+{\
+}
+#define CGEN_INIT_EXTRACT(od) \
+{\
+}
+#define CGEN_INIT_PRINT(od) \
+{\
+}
#endif /* I960_OPC_H */
diff --git a/sim/i960/i960-sim.h b/sim/i960/i960-sim.h
index e4794da..471b03e 100644
--- a/sim/i960/i960-sim.h
+++ b/sim/i960/i960-sim.h
@@ -10,6 +10,11 @@
#define FP0_REGNUM 36 /* First floating point register */
/* Some registers have more than one name */
#define PC_REGNUM IP_REGNUM /* GDB refers to ip as the Program Counter */
+
+SI a_i960_h_gr_get (SIM_CPU *, UINT);
+void a_i960_h_gr_set (SIM_CPU *, UINT, SI);
+IADDR a_i960_h_pc_get (SIM_CPU *);
+void a_i960_h_pc_set (SIM_CPU *, IADDR);
#define GETTWI GETTSI
#define SETTWI SETTSI
diff --git a/sim/i960/i960.c b/sim/i960/i960.c
index 9737c52..78fac37 100644
--- a/sim/i960/i960.c
+++ b/sim/i960/i960.c
@@ -68,6 +68,70 @@ i960base_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf,
return -1; /*FIXME*/
}
+/* Cover fns for mach independent register accesses. */
+
+SI
+a_i960_h_gr_get (SIM_CPU *current_cpu, UINT regno)
+{
+ switch (MACH_NUM (CPU_MACH (current_cpu)))
+ {
+#ifdef HAVE_CPU_I960BASE
+ case MACH_I960_KA_SA :
+ case MACH_I960_CA :
+ return i960base_h_gr_get (current_cpu, regno);
+#endif
+ default :
+ abort ();
+ }
+}
+
+void
+a_i960_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ switch (MACH_NUM (CPU_MACH (current_cpu)))
+ {
+#ifdef HAVE_CPU_I960BASE
+ case MACH_I960_KA_SA :
+ case MACH_I960_CA :
+ i960base_h_gr_set (current_cpu, regno, newval);
+ break;
+#endif
+ default :
+ abort ();
+ }
+}
+
+IADDR
+a_i960_h_pc_get (SIM_CPU *current_cpu)
+{
+ switch (MACH_NUM (CPU_MACH (current_cpu)))
+ {
+#ifdef HAVE_CPU_I960BASE
+ case MACH_I960_KA_SA :
+ case MACH_I960_CA :
+ return i960base_h_pc_get (current_cpu);
+#endif
+ default :
+ abort ();
+ }
+}
+
+void
+a_i960_h_pc_set (SIM_CPU *current_cpu, IADDR newval)
+{
+ switch (MACH_NUM (CPU_MACH (current_cpu)))
+ {
+#ifdef HAVE_CPU_I960BASE
+ case MACH_I960_KA_SA :
+ case MACH_I960_CA :
+ i960base_h_pc_set (current_cpu, newval);
+ break;
+#endif
+ default :
+ abort ();
+ }
+}
+
#if WITH_PROFILE_MODEL_P
/* FIXME: Some of these should be inline or macros. Later. */
diff --git a/sim/i960/model.c b/sim/i960/model.c
index 5069eb4..8881f3e 100644
--- a/sim/i960/model.c
+++ b/sim/i960/model.c
@@ -995,6 +995,70 @@ model_i960KA_nor3 (SIM_CPU *current_cpu, void *sem_arg)
}
static int
+model_i960KA_xnor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_xnor1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_xnor2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_xnor3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
model_i960KA_not (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_not.f
@@ -1059,6 +1123,70 @@ model_i960KA_not3 (SIM_CPU *current_cpu, void *sem_arg)
}
static int
+model_i960KA_ornot (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ornot1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ornot2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_i960KA_ornot3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
model_i960KA_clrbit (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_notbit.f
@@ -1125,7 +1253,7 @@ model_i960KA_clrbit3 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960KA_shlo (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit.f
+#define FLD(f) abuf->fields.fmt_shlo.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -1141,7 +1269,7 @@ model_i960KA_shlo (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960KA_shlo1 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit1.f
+#define FLD(f) abuf->fields.fmt_shlo1.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -1157,7 +1285,7 @@ model_i960KA_shlo1 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960KA_shlo2 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit2.f
+#define FLD(f) abuf->fields.fmt_shlo2.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -1173,7 +1301,7 @@ model_i960KA_shlo2 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960KA_shlo3 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit3.f
+#define FLD(f) abuf->fields.fmt_shlo3.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -1189,7 +1317,7 @@ model_i960KA_shlo3 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960KA_shro (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit.f
+#define FLD(f) abuf->fields.fmt_shlo.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -1205,7 +1333,7 @@ model_i960KA_shro (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960KA_shro1 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit1.f
+#define FLD(f) abuf->fields.fmt_shlo1.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -1221,7 +1349,7 @@ model_i960KA_shro1 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960KA_shro2 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit2.f
+#define FLD(f) abuf->fields.fmt_shlo2.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -1237,7 +1365,7 @@ model_i960KA_shro2 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960KA_shro3 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit3.f
+#define FLD(f) abuf->fields.fmt_shlo3.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -1253,7 +1381,7 @@ model_i960KA_shro3 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960KA_shli (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit.f
+#define FLD(f) abuf->fields.fmt_shlo.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -1269,7 +1397,7 @@ model_i960KA_shli (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960KA_shli1 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit1.f
+#define FLD(f) abuf->fields.fmt_shlo1.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -1285,7 +1413,7 @@ model_i960KA_shli1 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960KA_shli2 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit2.f
+#define FLD(f) abuf->fields.fmt_shlo2.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -1301,7 +1429,7 @@ model_i960KA_shli2 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960KA_shli3 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit3.f
+#define FLD(f) abuf->fields.fmt_shlo3.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -1317,7 +1445,7 @@ model_i960KA_shli3 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960KA_shri (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit.f
+#define FLD(f) abuf->fields.fmt_shlo.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -1333,7 +1461,7 @@ model_i960KA_shri (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960KA_shri1 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit1.f
+#define FLD(f) abuf->fields.fmt_shlo1.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -1349,7 +1477,7 @@ model_i960KA_shri1 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960KA_shri2 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit2.f
+#define FLD(f) abuf->fields.fmt_shlo2.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -1365,7 +1493,7 @@ model_i960KA_shri2 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960KA_shri3 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit3.f
+#define FLD(f) abuf->fields.fmt_shlo3.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -5523,6 +5651,70 @@ model_i960CA_nor3 (SIM_CPU *current_cpu, void *sem_arg)
}
static int
+model_i960CA_xnor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_xnor1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_xnor2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_xnor3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
model_i960CA_not (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_not.f
@@ -5587,6 +5779,70 @@ model_i960CA_not3 (SIM_CPU *current_cpu, void *sem_arg)
}
static int
+model_i960CA_ornot (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ornot1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ornot2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_i960CA_ornot3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
model_i960CA_clrbit (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_notbit.f
@@ -5653,7 +5909,7 @@ model_i960CA_clrbit3 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960CA_shlo (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit.f
+#define FLD(f) abuf->fields.fmt_shlo.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -5669,7 +5925,7 @@ model_i960CA_shlo (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960CA_shlo1 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit1.f
+#define FLD(f) abuf->fields.fmt_shlo1.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -5685,7 +5941,7 @@ model_i960CA_shlo1 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960CA_shlo2 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit2.f
+#define FLD(f) abuf->fields.fmt_shlo2.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -5701,7 +5957,7 @@ model_i960CA_shlo2 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960CA_shlo3 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit3.f
+#define FLD(f) abuf->fields.fmt_shlo3.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -5717,7 +5973,7 @@ model_i960CA_shlo3 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960CA_shro (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit.f
+#define FLD(f) abuf->fields.fmt_shlo.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -5733,7 +5989,7 @@ model_i960CA_shro (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960CA_shro1 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit1.f
+#define FLD(f) abuf->fields.fmt_shlo1.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -5749,7 +6005,7 @@ model_i960CA_shro1 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960CA_shro2 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit2.f
+#define FLD(f) abuf->fields.fmt_shlo2.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -5765,7 +6021,7 @@ model_i960CA_shro2 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960CA_shro3 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit3.f
+#define FLD(f) abuf->fields.fmt_shlo3.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -5781,7 +6037,7 @@ model_i960CA_shro3 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960CA_shli (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit.f
+#define FLD(f) abuf->fields.fmt_shlo.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -5797,7 +6053,7 @@ model_i960CA_shli (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960CA_shli1 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit1.f
+#define FLD(f) abuf->fields.fmt_shlo1.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -5813,7 +6069,7 @@ model_i960CA_shli1 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960CA_shli2 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit2.f
+#define FLD(f) abuf->fields.fmt_shlo2.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -5829,7 +6085,7 @@ model_i960CA_shli2 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960CA_shli3 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit3.f
+#define FLD(f) abuf->fields.fmt_shlo3.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -5845,7 +6101,7 @@ model_i960CA_shli3 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960CA_shri (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit.f
+#define FLD(f) abuf->fields.fmt_shlo.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -5861,7 +6117,7 @@ model_i960CA_shri (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960CA_shri1 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit1.f
+#define FLD(f) abuf->fields.fmt_shlo1.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -5877,7 +6133,7 @@ model_i960CA_shri1 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960CA_shri2 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit2.f
+#define FLD(f) abuf->fields.fmt_shlo2.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -5893,7 +6149,7 @@ model_i960CA_shri2 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960CA_shri3 (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit3.f
+#define FLD(f) abuf->fields.fmt_shlo3.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -9162,10 +9418,18 @@ static const INSN_TIMING i960KA_timing[] = {
{ I960BASE_INSN_NOR1, model_i960KA_nor1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_NOR2, model_i960KA_nor2, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_NOR3, model_i960KA_nor3, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+ { I960BASE_INSN_XNOR, model_i960KA_xnor, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+ { I960BASE_INSN_XNOR1, model_i960KA_xnor1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+ { I960BASE_INSN_XNOR2, model_i960KA_xnor2, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+ { I960BASE_INSN_XNOR3, model_i960KA_xnor3, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_NOT, model_i960KA_not, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_NOT1, model_i960KA_not1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_NOT2, model_i960KA_not2, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_NOT3, model_i960KA_not3, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+ { I960BASE_INSN_ORNOT, model_i960KA_ornot, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+ { I960BASE_INSN_ORNOT1, model_i960KA_ornot1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+ { I960BASE_INSN_ORNOT2, model_i960KA_ornot2, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
+ { I960BASE_INSN_ORNOT3, model_i960KA_ornot3, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_CLRBIT, model_i960KA_clrbit, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_CLRBIT1, model_i960KA_clrbit1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_CLRBIT2, model_i960KA_clrbit2, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
@@ -9456,10 +9720,18 @@ static const INSN_TIMING i960CA_timing[] = {
{ I960BASE_INSN_NOR1, model_i960CA_nor1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_NOR2, model_i960CA_nor2, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_NOR3, model_i960CA_nor3, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+ { I960BASE_INSN_XNOR, model_i960CA_xnor, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+ { I960BASE_INSN_XNOR1, model_i960CA_xnor1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+ { I960BASE_INSN_XNOR2, model_i960CA_xnor2, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+ { I960BASE_INSN_XNOR3, model_i960CA_xnor3, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_NOT, model_i960CA_not, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_NOT1, model_i960CA_not1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_NOT2, model_i960CA_not2, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_NOT3, model_i960CA_not3, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+ { I960BASE_INSN_ORNOT, model_i960CA_ornot, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+ { I960BASE_INSN_ORNOT1, model_i960CA_ornot1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+ { I960BASE_INSN_ORNOT2, model_i960CA_ornot2, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
+ { I960BASE_INSN_ORNOT3, model_i960CA_ornot3, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_CLRBIT, model_i960CA_clrbit, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_CLRBIT1, model_i960CA_clrbit1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_CLRBIT2, model_i960CA_clrbit2, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
@@ -9759,7 +10031,7 @@ i960_ka_sa_init_cpu (SIM_CPU *cpu)
const MACH i960_ka_sa_mach =
{
- "i960:ka_sa", "i960:ka_sa",
+ "i960:ka_sa", "i960:ka_sa", MACH_I960_KA_SA,
32, 32, & i960_ka_sa_models[0], & i960base_imp_properties,
i960_ka_sa_init_cpu,
i960base_prepare_run
@@ -9785,7 +10057,7 @@ i960_ca_init_cpu (SIM_CPU *cpu)
const MACH i960_ca_mach =
{
- "i960:ca", "i960:ca",
+ "i960:ca", "i960:ca", MACH_I960_CA,
32, 32, & i960_ca_models[0], & i960base_imp_properties,
i960_ca_init_cpu,
i960base_prepare_run
diff --git a/sim/i960/sem-switch.c b/sim/i960/sem-switch.c
index 2ab52eb..b45109f 100644
--- a/sim/i960/sem-switch.c
+++ b/sim/i960/sem-switch.c
@@ -98,10 +98,18 @@ with this program; if not, write to the Free Software Foundation, Inc.,
{ I960BASE_INSN_NOR1, && case_sem_INSN_NOR1 },
{ I960BASE_INSN_NOR2, && case_sem_INSN_NOR2 },
{ I960BASE_INSN_NOR3, && case_sem_INSN_NOR3 },
+ { I960BASE_INSN_XNOR, && case_sem_INSN_XNOR },
+ { I960BASE_INSN_XNOR1, && case_sem_INSN_XNOR1 },
+ { I960BASE_INSN_XNOR2, && case_sem_INSN_XNOR2 },
+ { I960BASE_INSN_XNOR3, && case_sem_INSN_XNOR3 },
{ I960BASE_INSN_NOT, && case_sem_INSN_NOT },
{ I960BASE_INSN_NOT1, && case_sem_INSN_NOT1 },
{ I960BASE_INSN_NOT2, && case_sem_INSN_NOT2 },
{ I960BASE_INSN_NOT3, && case_sem_INSN_NOT3 },
+ { I960BASE_INSN_ORNOT, && case_sem_INSN_ORNOT },
+ { I960BASE_INSN_ORNOT1, && case_sem_INSN_ORNOT1 },
+ { I960BASE_INSN_ORNOT2, && case_sem_INSN_ORNOT2 },
+ { I960BASE_INSN_ORNOT3, && case_sem_INSN_ORNOT3 },
{ I960BASE_INSN_CLRBIT, && case_sem_INSN_CLRBIT },
{ I960BASE_INSN_CLRBIT1, && case_sem_INSN_CLRBIT1 },
{ I960BASE_INSN_CLRBIT2, && case_sem_INSN_CLRBIT2 },
@@ -1652,6 +1660,82 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
}
NEXT (vpc);
+ CASE (sem, INSN_XNOR) : /* xnor $src1, $src2, $dst */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = INVSI (XORSI (* FLD (i_src1), * FLD (i_src2)));
+ * FLD (i_dst) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_XNOR1) : /* xnor $lit1, $src2, $dst */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo1.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = INVSI (XORSI (FLD (f_src1), * FLD (i_src2)));
+ * FLD (i_dst) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_XNOR2) : /* xnor $src1, $lit2, $dst */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo2.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = INVSI (XORSI (* FLD (i_src1), FLD (f_src2)));
+ * FLD (i_dst) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_XNOR3) : /* xnor $lit1, $lit2, $dst */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = INVSI (XORSI (FLD (f_src1), FLD (f_src2)));
+ * FLD (i_dst) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
CASE (sem, INSN_NOT) : /* not $src1, $src2, $dst */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
@@ -1728,6 +1812,82 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
}
NEXT (vpc);
+ CASE (sem, INSN_ORNOT) : /* ornot $src1, $src2, $dst */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = ORSI (* FLD (i_src2), INVSI (* FLD (i_src1)));
+ * FLD (i_dst) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ORNOT1) : /* ornot $lit1, $src2, $dst */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo1.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = ORSI (* FLD (i_src2), INVSI (FLD (f_src1)));
+ * FLD (i_dst) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ORNOT2) : /* ornot $src1, $lit2, $dst */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo2.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = ORSI (FLD (f_src2), INVSI (* FLD (i_src1)));
+ * FLD (i_dst) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ORNOT3) : /* ornot $lit1, $lit2, $dst */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_mulo3.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = ORSI (FLD (f_src2), INVSI (FLD (f_src1)));
+ * FLD (i_dst) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
CASE (sem, INSN_CLRBIT) : /* clrbit $src1, $src2, $dst */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
@@ -1808,13 +1968,13 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_notbit.f
+#define FLD(f) abuf->fields.fmt_shlo.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- SI opval = SLLSI (* FLD (i_src2), * FLD (i_src1));
+ SI opval = (GEUSI (* FLD (i_src1), 32)) ? (0) : (SLLSI (* FLD (i_src2), * FLD (i_src1)));
* FLD (i_dst) = opval;
TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
}
@@ -1827,13 +1987,13 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_notbit1.f
+#define FLD(f) abuf->fields.fmt_shlo1.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- SI opval = SLLSI (* FLD (i_src2), FLD (f_src1));
+ SI opval = (GEUSI (FLD (f_src1), 32)) ? (0) : (SLLSI (* FLD (i_src2), FLD (f_src1)));
* FLD (i_dst) = opval;
TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
}
@@ -1846,13 +2006,13 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_notbit2.f
+#define FLD(f) abuf->fields.fmt_shlo2.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- SI opval = SLLSI (FLD (f_src2), * FLD (i_src1));
+ SI opval = (GEUSI (* FLD (i_src1), 32)) ? (0) : (SLLSI (FLD (f_src2), * FLD (i_src1)));
* FLD (i_dst) = opval;
TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
}
@@ -1865,13 +2025,13 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_notbit3.f
+#define FLD(f) abuf->fields.fmt_shlo3.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- SI opval = SLLSI (FLD (f_src2), FLD (f_src1));
+ SI opval = (GEUSI (FLD (f_src1), 32)) ? (0) : (SLLSI (FLD (f_src2), FLD (f_src1)));
* FLD (i_dst) = opval;
TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
}
@@ -1884,13 +2044,13 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_notbit.f
+#define FLD(f) abuf->fields.fmt_shlo.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- SI opval = SRLSI (* FLD (i_src2), * FLD (i_src1));
+ SI opval = (GEUSI (* FLD (i_src1), 32)) ? (0) : (SRLSI (* FLD (i_src2), * FLD (i_src1)));
* FLD (i_dst) = opval;
TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
}
@@ -1903,13 +2063,13 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_notbit1.f
+#define FLD(f) abuf->fields.fmt_shlo1.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- SI opval = SRLSI (* FLD (i_src2), FLD (f_src1));
+ SI opval = (GEUSI (FLD (f_src1), 32)) ? (0) : (SRLSI (* FLD (i_src2), FLD (f_src1)));
* FLD (i_dst) = opval;
TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
}
@@ -1922,13 +2082,13 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_notbit2.f
+#define FLD(f) abuf->fields.fmt_shlo2.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- SI opval = SRLSI (FLD (f_src2), * FLD (i_src1));
+ SI opval = (GEUSI (* FLD (i_src1), 32)) ? (0) : (SRLSI (FLD (f_src2), * FLD (i_src1)));
* FLD (i_dst) = opval;
TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
}
@@ -1941,13 +2101,13 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_notbit3.f
+#define FLD(f) abuf->fields.fmt_shlo3.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- SI opval = SRLSI (FLD (f_src2), FLD (f_src1));
+ SI opval = (GEUSI (FLD (f_src1), 32)) ? (0) : (SRLSI (FLD (f_src2), FLD (f_src1)));
* FLD (i_dst) = opval;
TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
}
@@ -1960,13 +2120,13 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_notbit.f
+#define FLD(f) abuf->fields.fmt_shlo.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- SI opval = SLLSI (* FLD (i_src2), * FLD (i_src1));
+ SI opval = (GEUSI (* FLD (i_src1), 32)) ? (0) : (SLLSI (* FLD (i_src2), * FLD (i_src1)));
* FLD (i_dst) = opval;
TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
}
@@ -1979,13 +2139,13 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_notbit1.f
+#define FLD(f) abuf->fields.fmt_shlo1.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- SI opval = SLLSI (* FLD (i_src2), FLD (f_src1));
+ SI opval = (GEUSI (FLD (f_src1), 32)) ? (0) : (SLLSI (* FLD (i_src2), FLD (f_src1)));
* FLD (i_dst) = opval;
TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
}
@@ -1998,13 +2158,13 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_notbit2.f
+#define FLD(f) abuf->fields.fmt_shlo2.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- SI opval = SLLSI (FLD (f_src2), * FLD (i_src1));
+ SI opval = (GEUSI (* FLD (i_src1), 32)) ? (0) : (SLLSI (FLD (f_src2), * FLD (i_src1)));
* FLD (i_dst) = opval;
TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
}
@@ -2017,13 +2177,13 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_notbit3.f
+#define FLD(f) abuf->fields.fmt_shlo3.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- SI opval = SLLSI (FLD (f_src2), FLD (f_src1));
+ SI opval = (GEUSI (FLD (f_src1), 32)) ? (0) : (SLLSI (FLD (f_src2), FLD (f_src1)));
* FLD (i_dst) = opval;
TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
}
@@ -2036,13 +2196,13 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_notbit.f
+#define FLD(f) abuf->fields.fmt_shlo.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- SI opval = SRASI (* FLD (i_src2), * FLD (i_src1));
+ SI opval = (GEUSI (* FLD (i_src1), 32)) ? (SRASI (* FLD (i_src2), 31)) : (SRASI (* FLD (i_src2), * FLD (i_src1)));
* FLD (i_dst) = opval;
TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
}
@@ -2055,13 +2215,13 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_notbit1.f
+#define FLD(f) abuf->fields.fmt_shlo1.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- SI opval = SRASI (* FLD (i_src2), FLD (f_src1));
+ SI opval = (GEUSI (FLD (f_src1), 32)) ? (SRASI (* FLD (i_src2), 31)) : (SRASI (* FLD (i_src2), FLD (f_src1)));
* FLD (i_dst) = opval;
TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
}
@@ -2074,13 +2234,13 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_notbit2.f
+#define FLD(f) abuf->fields.fmt_shlo2.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- SI opval = SRASI (FLD (f_src2), * FLD (i_src1));
+ SI opval = (GEUSI (* FLD (i_src1), 32)) ? (SRASI (FLD (f_src2), 31)) : (SRASI (FLD (f_src2), * FLD (i_src1)));
* FLD (i_dst) = opval;
TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
}
@@ -2093,13 +2253,13 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_notbit3.f
+#define FLD(f) abuf->fields.fmt_shlo3.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- SI opval = SRASI (FLD (f_src2), FLD (f_src1));
+ SI opval = (GEUSI (FLD (f_src1), 32)) ? (SRASI (FLD (f_src2), 31)) : (SRASI (FLD (f_src2), FLD (f_src1)));
* FLD (i_dst) = opval;
TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
}
@@ -2117,9 +2277,9 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
- SI tmp_dregno;
+{
DI tmp_temp;
+ SI tmp_dregno;
tmp_temp = MULDI (ZEXTSIDI (* FLD (i_src1)), ZEXTSIDI (* FLD (i_src2)));
tmp_dregno = FLD (f_srcdst);
{
@@ -2130,9 +2290,9 @@ do {
{
SI opval = TRUNCDISI (SRLDI (tmp_temp, 32));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -2147,9 +2307,9 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
- SI tmp_dregno;
+{
DI tmp_temp;
+ SI tmp_dregno;
tmp_temp = MULDI (ZEXTSIDI (FLD (f_src1)), ZEXTSIDI (* FLD (i_src2)));
tmp_dregno = FLD (f_srcdst);
{
@@ -2160,9 +2320,9 @@ do {
{
SI opval = TRUNCDISI (SRLDI (tmp_temp, 32));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -2177,9 +2337,9 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
- SI tmp_dregno;
+{
DI tmp_temp;
+ SI tmp_dregno;
tmp_temp = MULDI (ZEXTSIDI (* FLD (i_src1)), ZEXTSIDI (FLD (f_src2)));
tmp_dregno = FLD (f_srcdst);
{
@@ -2190,9 +2350,9 @@ do {
{
SI opval = TRUNCDISI (SRLDI (tmp_temp, 32));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -2207,9 +2367,9 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
- SI tmp_dregno;
+{
DI tmp_temp;
+ SI tmp_dregno;
tmp_temp = MULDI (ZEXTSIDI (FLD (f_src1)), ZEXTSIDI (FLD (f_src2)));
tmp_dregno = FLD (f_srcdst);
{
@@ -2220,9 +2380,9 @@ do {
{
SI opval = TRUNCDISI (SRLDI (tmp_temp, 32));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -2275,9 +2435,9 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
- SI tmp_sregno;
+{
SI tmp_dregno;
+ SI tmp_sregno;
tmp_dregno = FLD (f_srcdst);
tmp_sregno = FLD (f_src1);
{
@@ -2288,9 +2448,9 @@ do {
{
SI opval = CPU (h_gr[((FLD (f_src1)) + (1))]);
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -2305,7 +2465,7 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
+{
SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
{
@@ -2316,9 +2476,9 @@ do {
{
SI opval = 0;
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -2333,9 +2493,9 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
- SI tmp_sregno;
+{
SI tmp_dregno;
+ SI tmp_sregno;
tmp_dregno = FLD (f_srcdst);
tmp_sregno = FLD (f_src1);
{
@@ -2346,14 +2506,14 @@ do {
{
SI opval = CPU (h_gr[((FLD (f_src1)) + (1))]);
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
{
SI opval = CPU (h_gr[((FLD (f_src1)) + (2))]);
CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -2368,7 +2528,7 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
+{
SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
{
@@ -2379,14 +2539,14 @@ do {
{
SI opval = 0;
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
{
SI opval = 0;
CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -2401,9 +2561,9 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
- SI tmp_sregno;
+{
SI tmp_dregno;
+ SI tmp_sregno;
tmp_dregno = FLD (f_srcdst);
tmp_sregno = FLD (f_src1);
{
@@ -2414,19 +2574,19 @@ do {
{
SI opval = CPU (h_gr[((FLD (f_src1)) + (1))]);
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
{
SI opval = CPU (h_gr[((FLD (f_src1)) + (2))]);
CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval);
}
{
SI opval = CPU (h_gr[((FLD (f_src1)) + (3))]);
CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-3", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -2441,7 +2601,7 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
+{
SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
{
@@ -2452,19 +2612,19 @@ do {
{
SI opval = 0;
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
{
SI opval = 0;
CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval);
}
{
SI opval = 0;
CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-3", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -3429,9 +3589,9 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = FLD (f_offset);
{
@@ -3442,9 +3602,9 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -3459,9 +3619,9 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = ADDSI (FLD (f_offset), * FLD (i_abase));
{
@@ -3472,9 +3632,9 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -3489,9 +3649,9 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = * FLD (i_abase);
{
@@ -3502,9 +3662,9 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -3519,9 +3679,9 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))));
{
@@ -3532,9 +3692,9 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -3549,9 +3709,9 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = FLD (f_optdisp);
{
@@ -3562,9 +3722,9 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -3579,9 +3739,9 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = ADDSI (FLD (f_optdisp), * FLD (i_abase));
{
@@ -3592,9 +3752,9 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -3609,9 +3769,9 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))));
{
@@ -3622,9 +3782,9 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -3639,9 +3799,9 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))));
{
@@ -3652,9 +3812,9 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -3669,9 +3829,9 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = FLD (f_offset);
{
@@ -3682,14 +3842,14 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -3704,9 +3864,9 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = ADDSI (FLD (f_offset), * FLD (i_abase));
{
@@ -3717,14 +3877,14 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -3739,9 +3899,9 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = * FLD (i_abase);
{
@@ -3752,14 +3912,14 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -3774,9 +3934,9 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))));
{
@@ -3787,14 +3947,14 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -3809,9 +3969,9 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = FLD (f_optdisp);
{
@@ -3822,14 +3982,14 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -3844,9 +4004,9 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = ADDSI (FLD (f_optdisp), * FLD (i_abase));
{
@@ -3857,14 +4017,14 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -3879,9 +4039,9 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))));
{
@@ -3892,14 +4052,14 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -3914,9 +4074,9 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))));
{
@@ -3927,14 +4087,14 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -3949,9 +4109,9 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = FLD (f_offset);
{
@@ -3962,19 +4122,19 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12));
CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-3", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -3989,9 +4149,9 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = ADDSI (FLD (f_offset), * FLD (i_abase));
{
@@ -4002,19 +4162,19 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12));
CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-3", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -4029,9 +4189,9 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = * FLD (i_abase);
{
@@ -4042,19 +4202,19 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12));
CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-3", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -4069,9 +4229,9 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))));
{
@@ -4082,19 +4242,19 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12));
CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-3", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -4109,9 +4269,9 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = FLD (f_optdisp);
{
@@ -4122,19 +4282,19 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12));
CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-3", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -4149,9 +4309,9 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = ADDSI (FLD (f_optdisp), * FLD (i_abase));
{
@@ -4162,19 +4322,19 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12));
CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-3", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -4189,9 +4349,9 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))));
{
@@ -4202,19 +4362,19 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12));
CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-3", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -4229,9 +4389,9 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))));
{
@@ -4242,19 +4402,19 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12));
CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-3", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -4725,7 +4885,7 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -4738,7 +4898,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (FLD (f_offset), 4), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -4753,7 +4913,7 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -4766,7 +4926,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_offset), * FLD (i_abase)), 4), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -4781,7 +4941,7 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -4794,7 +4954,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_abase), 4), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -4809,7 +4969,7 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -4822,7 +4982,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 4), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -4837,7 +4997,7 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -4850,7 +5010,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), 4), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -4865,7 +5025,7 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -4878,7 +5038,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), * FLD (i_abase)), 4), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -4893,7 +5053,7 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -4906,7 +5066,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 4), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -4921,7 +5081,7 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -4934,7 +5094,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))), 4), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -4949,7 +5109,7 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -4967,7 +5127,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (FLD (f_offset), 8), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -4982,7 +5142,7 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -5000,7 +5160,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_offset), * FLD (i_abase)), 8), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -5015,7 +5175,7 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -5033,7 +5193,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_abase), 8), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -5048,7 +5208,7 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -5066,7 +5226,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 8), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -5081,7 +5241,7 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -5099,7 +5259,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), 8), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -5114,7 +5274,7 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -5132,7 +5292,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), * FLD (i_abase)), 8), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -5147,7 +5307,7 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -5165,7 +5325,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 8), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -5180,7 +5340,7 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -5198,7 +5358,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))), 8), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -5213,7 +5373,7 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -5236,7 +5396,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (FLD (f_offset), 12), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -5251,7 +5411,7 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -5274,7 +5434,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_offset), * FLD (i_abase)), 12), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -5289,7 +5449,7 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -5312,7 +5472,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_abase), 12), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -5327,7 +5487,7 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -5350,7 +5510,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 12), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -5365,7 +5525,7 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -5388,7 +5548,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), 12), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -5403,7 +5563,7 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -5426,7 +5586,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), * FLD (i_abase)), 12), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -5441,7 +5601,7 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -5464,7 +5624,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 12), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -5479,7 +5639,7 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -5502,7 +5662,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))), 12), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
#undef FLD
}
@@ -6220,7 +6380,7 @@ if (NESI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) {
{
SI opval = (LTSI (* FLD (i_src1), * FLD (i_src2))) ? (4) : (EQSI (* FLD (i_src1), * FLD (i_src2))) ? (2) : (1);
CPU (h_cc) = opval;
- TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "cc", 'x', opval);
}
#undef FLD
@@ -6239,7 +6399,7 @@ if (NESI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) {
{
SI opval = (LTSI (FLD (f_src1), * FLD (i_src2))) ? (4) : (EQSI (FLD (f_src1), * FLD (i_src2))) ? (2) : (1);
CPU (h_cc) = opval;
- TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "cc", 'x', opval);
}
#undef FLD
@@ -6258,7 +6418,7 @@ if (NESI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) {
{
SI opval = (LTSI (* FLD (i_src1), FLD (f_src2))) ? (4) : (EQSI (* FLD (i_src1), FLD (f_src2))) ? (2) : (1);
CPU (h_cc) = opval;
- TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "cc", 'x', opval);
}
#undef FLD
@@ -6277,7 +6437,7 @@ if (NESI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) {
{
SI opval = (LTSI (FLD (f_src1), FLD (f_src2))) ? (4) : (EQSI (FLD (f_src1), FLD (f_src2))) ? (2) : (1);
CPU (h_cc) = opval;
- TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "cc", 'x', opval);
}
#undef FLD
@@ -6296,7 +6456,7 @@ if (NESI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) {
{
SI opval = (LTUSI (* FLD (i_src1), * FLD (i_src2))) ? (4) : (EQSI (* FLD (i_src1), * FLD (i_src2))) ? (2) : (1);
CPU (h_cc) = opval;
- TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "cc", 'x', opval);
}
#undef FLD
@@ -6315,7 +6475,7 @@ if (NESI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) {
{
SI opval = (LTUSI (FLD (f_src1), * FLD (i_src2))) ? (4) : (EQSI (FLD (f_src1), * FLD (i_src2))) ? (2) : (1);
CPU (h_cc) = opval;
- TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "cc", 'x', opval);
}
#undef FLD
@@ -6334,7 +6494,7 @@ if (NESI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) {
{
SI opval = (LTUSI (* FLD (i_src1), FLD (f_src2))) ? (4) : (EQSI (* FLD (i_src1), FLD (f_src2))) ? (2) : (1);
CPU (h_cc) = opval;
- TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "cc", 'x', opval);
}
#undef FLD
@@ -6353,7 +6513,7 @@ if (NESI (ANDSI (SLLSI (1, FLD (f_br_src1)), * FLD (i_br_src2)), 0)) {
{
SI opval = (LTUSI (FLD (f_src1), FLD (f_src2))) ? (4) : (EQSI (FLD (f_src1), FLD (f_src2))) ? (2) : (1);
CPU (h_cc) = opval;
- TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "cc", 'x', opval);
}
#undef FLD
@@ -6848,7 +7008,7 @@ if (NESI (ANDSI (CPU (h_cc), 7), 0)) {
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
+{
SI tmp_temp;
tmp_temp = ANDSI (ADDSI (CPU (h_gr[((UINT) 1)]), 63), INVSI (63));
{
@@ -6908,7 +7068,7 @@ CPU (h_gr[((UINT) 15)]) = 0xdeadbeef;
CPU (h_gr[((UINT) 1)]) = opval;
TRACE_RESULT (current_cpu, abuf, "gr-1", 'x', opval);
}
-} while (0);
+}
SEM_BRANCH_FINI (vpc);
#undef FLD
@@ -6925,7 +7085,7 @@ CPU (h_gr[((UINT) 15)]) = 0xdeadbeef;
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
+{
SI tmp_temp;
tmp_temp = ANDSI (ADDSI (CPU (h_gr[((UINT) 1)]), 63), INVSI (63));
{
@@ -6985,7 +7145,7 @@ CPU (h_gr[((UINT) 15)]) = 0xdeadbeef;
CPU (h_gr[((UINT) 1)]) = opval;
TRACE_RESULT (current_cpu, abuf, "gr-1", 'x', opval);
}
-} while (0);
+}
SEM_BRANCH_FINI (vpc);
#undef FLD
@@ -7002,7 +7162,7 @@ CPU (h_gr[((UINT) 15)]) = 0xdeadbeef;
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
+{
SI tmp_temp;
tmp_temp = ANDSI (ADDSI (CPU (h_gr[((UINT) 1)]), 63), INVSI (63));
{
@@ -7062,7 +7222,7 @@ CPU (h_gr[((UINT) 15)]) = 0xdeadbeef;
CPU (h_gr[((UINT) 1)]) = opval;
TRACE_RESULT (current_cpu, abuf, "gr-1", 'x', opval);
}
-} while (0);
+}
SEM_BRANCH_FINI (vpc);
#undef FLD
@@ -7079,7 +7239,7 @@ CPU (h_gr[((UINT) 15)]) = 0xdeadbeef;
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
+{
{
SI opval = CPU (h_gr[((UINT) 0)]);
CPU (h_gr[((UINT) 31)]) = opval;
@@ -7106,7 +7266,7 @@ CPU (h_gr[((UINT) 15)]) = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
-} while (0);
+}
SEM_BRANCH_FINI (vpc);
#undef FLD
diff --git a/sim/i960/sem.c b/sim/i960/sem.c
index e062188..45f4f7f 100644
--- a/sim/i960/sem.c
+++ b/sim/i960/sem.c
@@ -1440,6 +1440,90 @@ SEM_FN_NAME (i960base,nor3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
+/* xnor: xnor $src1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,xnor) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = INVSI (XORSI (* FLD (i_src1), * FLD (i_src2)));
+ * FLD (i_dst) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* xnor1: xnor $lit1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,xnor1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = INVSI (XORSI (FLD (f_src1), * FLD (i_src2)));
+ * FLD (i_dst) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* xnor2: xnor $src1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,xnor2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = INVSI (XORSI (* FLD (i_src1), FLD (f_src2)));
+ * FLD (i_dst) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* xnor3: xnor $lit1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,xnor3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = INVSI (XORSI (FLD (f_src1), FLD (f_src2)));
+ * FLD (i_dst) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
/* not: not $src1, $src2, $dst */
SEM_PC
@@ -1524,6 +1608,90 @@ SEM_FN_NAME (i960base,not3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
+/* ornot: ornot $src1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ornot) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = ORSI (* FLD (i_src2), INVSI (* FLD (i_src1)));
+ * FLD (i_dst) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ornot1: ornot $lit1, $src2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ornot1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo1.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = ORSI (* FLD (i_src2), INVSI (FLD (f_src1)));
+ * FLD (i_dst) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ornot2: ornot $src1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ornot2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo2.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = ORSI (FLD (f_src2), INVSI (* FLD (i_src1)));
+ * FLD (i_dst) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ornot3: ornot $lit1, $lit2, $dst */
+
+SEM_PC
+SEM_FN_NAME (i960base,ornot3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_mulo3.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = ORSI (FLD (f_src2), INVSI (FLD (f_src1)));
+ * FLD (i_dst) = opval;
+ TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
/* clrbit: clrbit $src1, $src2, $dst */
SEM_PC
@@ -1613,14 +1781,14 @@ SEM_FN_NAME (i960base,clrbit3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC
SEM_FN_NAME (i960base,shlo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit.f
+#define FLD(f) abuf->fields.fmt_shlo.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- SI opval = SLLSI (* FLD (i_src2), * FLD (i_src1));
+ SI opval = (GEUSI (* FLD (i_src1), 32)) ? (0) : (SLLSI (* FLD (i_src2), * FLD (i_src1)));
* FLD (i_dst) = opval;
TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
}
@@ -1634,14 +1802,14 @@ SEM_FN_NAME (i960base,shlo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC
SEM_FN_NAME (i960base,shlo1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit1.f
+#define FLD(f) abuf->fields.fmt_shlo1.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- SI opval = SLLSI (* FLD (i_src2), FLD (f_src1));
+ SI opval = (GEUSI (FLD (f_src1), 32)) ? (0) : (SLLSI (* FLD (i_src2), FLD (f_src1)));
* FLD (i_dst) = opval;
TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
}
@@ -1655,14 +1823,14 @@ SEM_FN_NAME (i960base,shlo1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC
SEM_FN_NAME (i960base,shlo2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit2.f
+#define FLD(f) abuf->fields.fmt_shlo2.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- SI opval = SLLSI (FLD (f_src2), * FLD (i_src1));
+ SI opval = (GEUSI (* FLD (i_src1), 32)) ? (0) : (SLLSI (FLD (f_src2), * FLD (i_src1)));
* FLD (i_dst) = opval;
TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
}
@@ -1676,14 +1844,14 @@ SEM_FN_NAME (i960base,shlo2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC
SEM_FN_NAME (i960base,shlo3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit3.f
+#define FLD(f) abuf->fields.fmt_shlo3.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- SI opval = SLLSI (FLD (f_src2), FLD (f_src1));
+ SI opval = (GEUSI (FLD (f_src1), 32)) ? (0) : (SLLSI (FLD (f_src2), FLD (f_src1)));
* FLD (i_dst) = opval;
TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
}
@@ -1697,14 +1865,14 @@ SEM_FN_NAME (i960base,shlo3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC
SEM_FN_NAME (i960base,shro) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit.f
+#define FLD(f) abuf->fields.fmt_shlo.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- SI opval = SRLSI (* FLD (i_src2), * FLD (i_src1));
+ SI opval = (GEUSI (* FLD (i_src1), 32)) ? (0) : (SRLSI (* FLD (i_src2), * FLD (i_src1)));
* FLD (i_dst) = opval;
TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
}
@@ -1718,14 +1886,14 @@ SEM_FN_NAME (i960base,shro) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC
SEM_FN_NAME (i960base,shro1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit1.f
+#define FLD(f) abuf->fields.fmt_shlo1.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- SI opval = SRLSI (* FLD (i_src2), FLD (f_src1));
+ SI opval = (GEUSI (FLD (f_src1), 32)) ? (0) : (SRLSI (* FLD (i_src2), FLD (f_src1)));
* FLD (i_dst) = opval;
TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
}
@@ -1739,14 +1907,14 @@ SEM_FN_NAME (i960base,shro1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC
SEM_FN_NAME (i960base,shro2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit2.f
+#define FLD(f) abuf->fields.fmt_shlo2.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- SI opval = SRLSI (FLD (f_src2), * FLD (i_src1));
+ SI opval = (GEUSI (* FLD (i_src1), 32)) ? (0) : (SRLSI (FLD (f_src2), * FLD (i_src1)));
* FLD (i_dst) = opval;
TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
}
@@ -1760,14 +1928,14 @@ SEM_FN_NAME (i960base,shro2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC
SEM_FN_NAME (i960base,shro3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit3.f
+#define FLD(f) abuf->fields.fmt_shlo3.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- SI opval = SRLSI (FLD (f_src2), FLD (f_src1));
+ SI opval = (GEUSI (FLD (f_src1), 32)) ? (0) : (SRLSI (FLD (f_src2), FLD (f_src1)));
* FLD (i_dst) = opval;
TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
}
@@ -1781,14 +1949,14 @@ SEM_FN_NAME (i960base,shro3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC
SEM_FN_NAME (i960base,shli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit.f
+#define FLD(f) abuf->fields.fmt_shlo.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- SI opval = SLLSI (* FLD (i_src2), * FLD (i_src1));
+ SI opval = (GEUSI (* FLD (i_src1), 32)) ? (0) : (SLLSI (* FLD (i_src2), * FLD (i_src1)));
* FLD (i_dst) = opval;
TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
}
@@ -1802,14 +1970,14 @@ SEM_FN_NAME (i960base,shli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC
SEM_FN_NAME (i960base,shli1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit1.f
+#define FLD(f) abuf->fields.fmt_shlo1.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- SI opval = SLLSI (* FLD (i_src2), FLD (f_src1));
+ SI opval = (GEUSI (FLD (f_src1), 32)) ? (0) : (SLLSI (* FLD (i_src2), FLD (f_src1)));
* FLD (i_dst) = opval;
TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
}
@@ -1823,14 +1991,14 @@ SEM_FN_NAME (i960base,shli1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC
SEM_FN_NAME (i960base,shli2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit2.f
+#define FLD(f) abuf->fields.fmt_shlo2.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- SI opval = SLLSI (FLD (f_src2), * FLD (i_src1));
+ SI opval = (GEUSI (* FLD (i_src1), 32)) ? (0) : (SLLSI (FLD (f_src2), * FLD (i_src1)));
* FLD (i_dst) = opval;
TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
}
@@ -1844,14 +2012,14 @@ SEM_FN_NAME (i960base,shli2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC
SEM_FN_NAME (i960base,shli3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit3.f
+#define FLD(f) abuf->fields.fmt_shlo3.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- SI opval = SLLSI (FLD (f_src2), FLD (f_src1));
+ SI opval = (GEUSI (FLD (f_src1), 32)) ? (0) : (SLLSI (FLD (f_src2), FLD (f_src1)));
* FLD (i_dst) = opval;
TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
}
@@ -1865,14 +2033,14 @@ SEM_FN_NAME (i960base,shli3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC
SEM_FN_NAME (i960base,shri) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit.f
+#define FLD(f) abuf->fields.fmt_shlo.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- SI opval = SRASI (* FLD (i_src2), * FLD (i_src1));
+ SI opval = (GEUSI (* FLD (i_src1), 32)) ? (SRASI (* FLD (i_src2), 31)) : (SRASI (* FLD (i_src2), * FLD (i_src1)));
* FLD (i_dst) = opval;
TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
}
@@ -1886,14 +2054,14 @@ SEM_FN_NAME (i960base,shri) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC
SEM_FN_NAME (i960base,shri1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit1.f
+#define FLD(f) abuf->fields.fmt_shlo1.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- SI opval = SRASI (* FLD (i_src2), FLD (f_src1));
+ SI opval = (GEUSI (FLD (f_src1), 32)) ? (SRASI (* FLD (i_src2), 31)) : (SRASI (* FLD (i_src2), FLD (f_src1)));
* FLD (i_dst) = opval;
TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
}
@@ -1907,14 +2075,14 @@ SEM_FN_NAME (i960base,shri1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC
SEM_FN_NAME (i960base,shri2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit2.f
+#define FLD(f) abuf->fields.fmt_shlo2.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- SI opval = SRASI (FLD (f_src2), * FLD (i_src1));
+ SI opval = (GEUSI (* FLD (i_src1), 32)) ? (SRASI (FLD (f_src2), 31)) : (SRASI (FLD (f_src2), * FLD (i_src1)));
* FLD (i_dst) = opval;
TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
}
@@ -1928,14 +2096,14 @@ SEM_FN_NAME (i960base,shri2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC
SEM_FN_NAME (i960base,shri3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
-#define FLD(f) abuf->fields.fmt_notbit3.f
+#define FLD(f) abuf->fields.fmt_shlo3.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- SI opval = SRASI (FLD (f_src2), FLD (f_src1));
+ SI opval = (GEUSI (FLD (f_src1), 32)) ? (SRASI (FLD (f_src2), 31)) : (SRASI (FLD (f_src2), FLD (f_src1)));
* FLD (i_dst) = opval;
TRACE_RESULT (current_cpu, abuf, "dst", 'x', opval);
}
@@ -1955,9 +2123,9 @@ SEM_FN_NAME (i960base,emul) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
- SI tmp_dregno;
+{
DI tmp_temp;
+ SI tmp_dregno;
tmp_temp = MULDI (ZEXTSIDI (* FLD (i_src1)), ZEXTSIDI (* FLD (i_src2)));
tmp_dregno = FLD (f_srcdst);
{
@@ -1968,9 +2136,9 @@ do {
{
SI opval = TRUNCDISI (SRLDI (tmp_temp, 32));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -1987,9 +2155,9 @@ SEM_FN_NAME (i960base,emul1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
- SI tmp_dregno;
+{
DI tmp_temp;
+ SI tmp_dregno;
tmp_temp = MULDI (ZEXTSIDI (FLD (f_src1)), ZEXTSIDI (* FLD (i_src2)));
tmp_dregno = FLD (f_srcdst);
{
@@ -2000,9 +2168,9 @@ do {
{
SI opval = TRUNCDISI (SRLDI (tmp_temp, 32));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -2019,9 +2187,9 @@ SEM_FN_NAME (i960base,emul2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
- SI tmp_dregno;
+{
DI tmp_temp;
+ SI tmp_dregno;
tmp_temp = MULDI (ZEXTSIDI (* FLD (i_src1)), ZEXTSIDI (FLD (f_src2)));
tmp_dregno = FLD (f_srcdst);
{
@@ -2032,9 +2200,9 @@ do {
{
SI opval = TRUNCDISI (SRLDI (tmp_temp, 32));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -2051,9 +2219,9 @@ SEM_FN_NAME (i960base,emul3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
- SI tmp_dregno;
+{
DI tmp_temp;
+ SI tmp_dregno;
tmp_temp = MULDI (ZEXTSIDI (FLD (f_src1)), ZEXTSIDI (FLD (f_src2)));
tmp_dregno = FLD (f_srcdst);
{
@@ -2064,9 +2232,9 @@ do {
{
SI opval = TRUNCDISI (SRLDI (tmp_temp, 32));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -2125,9 +2293,9 @@ SEM_FN_NAME (i960base,movl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
- SI tmp_sregno;
+{
SI tmp_dregno;
+ SI tmp_sregno;
tmp_dregno = FLD (f_srcdst);
tmp_sregno = FLD (f_src1);
{
@@ -2138,9 +2306,9 @@ do {
{
SI opval = CPU (h_gr[((FLD (f_src1)) + (1))]);
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -2157,7 +2325,7 @@ SEM_FN_NAME (i960base,movl1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
+{
SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
{
@@ -2168,9 +2336,9 @@ do {
{
SI opval = 0;
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -2187,9 +2355,9 @@ SEM_FN_NAME (i960base,movt) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
- SI tmp_sregno;
+{
SI tmp_dregno;
+ SI tmp_sregno;
tmp_dregno = FLD (f_srcdst);
tmp_sregno = FLD (f_src1);
{
@@ -2200,14 +2368,14 @@ do {
{
SI opval = CPU (h_gr[((FLD (f_src1)) + (1))]);
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
{
SI opval = CPU (h_gr[((FLD (f_src1)) + (2))]);
CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -2224,7 +2392,7 @@ SEM_FN_NAME (i960base,movt1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
+{
SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
{
@@ -2235,14 +2403,14 @@ do {
{
SI opval = 0;
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
{
SI opval = 0;
CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -2259,9 +2427,9 @@ SEM_FN_NAME (i960base,movq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
- SI tmp_sregno;
+{
SI tmp_dregno;
+ SI tmp_sregno;
tmp_dregno = FLD (f_srcdst);
tmp_sregno = FLD (f_src1);
{
@@ -2272,19 +2440,19 @@ do {
{
SI opval = CPU (h_gr[((FLD (f_src1)) + (1))]);
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
{
SI opval = CPU (h_gr[((FLD (f_src1)) + (2))]);
CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval);
}
{
SI opval = CPU (h_gr[((FLD (f_src1)) + (3))]);
CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-3", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -2301,7 +2469,7 @@ SEM_FN_NAME (i960base,movq1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
+{
SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
{
@@ -2312,19 +2480,19 @@ do {
{
SI opval = 0;
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
{
SI opval = 0;
CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval);
}
{
SI opval = 0;
CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-3", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -3391,9 +3559,9 @@ SEM_FN_NAME (i960base,ldl_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = FLD (f_offset);
{
@@ -3404,9 +3572,9 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -3423,9 +3591,9 @@ SEM_FN_NAME (i960base,ldl_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_ar
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = ADDSI (FLD (f_offset), * FLD (i_abase));
{
@@ -3436,9 +3604,9 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -3455,9 +3623,9 @@ SEM_FN_NAME (i960base,ldl_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = * FLD (i_abase);
{
@@ -3468,9 +3636,9 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -3487,9 +3655,9 @@ SEM_FN_NAME (i960base,ldl_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))));
{
@@ -3500,9 +3668,9 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -3519,9 +3687,9 @@ SEM_FN_NAME (i960base,ldl_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = FLD (f_optdisp);
{
@@ -3532,9 +3700,9 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -3551,9 +3719,9 @@ SEM_FN_NAME (i960base,ldl_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = ADDSI (FLD (f_optdisp), * FLD (i_abase));
{
@@ -3564,9 +3732,9 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -3583,9 +3751,9 @@ SEM_FN_NAME (i960base,ldl_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))));
{
@@ -3596,9 +3764,9 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -3615,9 +3783,9 @@ SEM_FN_NAME (i960base,ldl_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG se
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))));
{
@@ -3628,9 +3796,9 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -3647,9 +3815,9 @@ SEM_FN_NAME (i960base,ldt_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = FLD (f_offset);
{
@@ -3660,14 +3828,14 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -3684,9 +3852,9 @@ SEM_FN_NAME (i960base,ldt_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_ar
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = ADDSI (FLD (f_offset), * FLD (i_abase));
{
@@ -3697,14 +3865,14 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -3721,9 +3889,9 @@ SEM_FN_NAME (i960base,ldt_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = * FLD (i_abase);
{
@@ -3734,14 +3902,14 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -3758,9 +3926,9 @@ SEM_FN_NAME (i960base,ldt_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))));
{
@@ -3771,14 +3939,14 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -3795,9 +3963,9 @@ SEM_FN_NAME (i960base,ldt_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = FLD (f_optdisp);
{
@@ -3808,14 +3976,14 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -3832,9 +4000,9 @@ SEM_FN_NAME (i960base,ldt_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = ADDSI (FLD (f_optdisp), * FLD (i_abase));
{
@@ -3845,14 +4013,14 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -3869,9 +4037,9 @@ SEM_FN_NAME (i960base,ldt_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))));
{
@@ -3882,14 +4050,14 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -3906,9 +4074,9 @@ SEM_FN_NAME (i960base,ldt_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG se
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))));
{
@@ -3919,14 +4087,14 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -3943,9 +4111,9 @@ SEM_FN_NAME (i960base,ldq_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = FLD (f_offset);
{
@@ -3956,19 +4124,19 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12));
CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-3", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -3985,9 +4153,9 @@ SEM_FN_NAME (i960base,ldq_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_ar
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = ADDSI (FLD (f_offset), * FLD (i_abase));
{
@@ -3998,19 +4166,19 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12));
CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-3", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -4027,9 +4195,9 @@ SEM_FN_NAME (i960base,ldq_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = * FLD (i_abase);
{
@@ -4040,19 +4208,19 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12));
CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-3", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -4069,9 +4237,9 @@ SEM_FN_NAME (i960base,ldq_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))));
{
@@ -4082,19 +4250,19 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12));
CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-3", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -4111,9 +4279,9 @@ SEM_FN_NAME (i960base,ldq_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = FLD (f_optdisp);
{
@@ -4124,19 +4292,19 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12));
CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-3", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -4153,9 +4321,9 @@ SEM_FN_NAME (i960base,ldq_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = ADDSI (FLD (f_optdisp), * FLD (i_abase));
{
@@ -4166,19 +4334,19 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12));
CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-3", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -4195,9 +4363,9 @@ SEM_FN_NAME (i960base,ldq_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))));
{
@@ -4208,19 +4376,19 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12));
CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-3", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -4237,9 +4405,9 @@ SEM_FN_NAME (i960base,ldq_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG se
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
- SI tmp_dregno;
+{
SI tmp_temp;
+ SI tmp_dregno;
tmp_dregno = FLD (f_srcdst);
tmp_temp = ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))));
{
@@ -4250,19 +4418,19 @@ do {
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 4));
CPU (h_gr[((FLD (f_srcdst)) + (1))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-1", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-1", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 8));
CPU (h_gr[((FLD (f_srcdst)) + (2))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-2", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-2", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, ADDSI (tmp_temp, 12));
CPU (h_gr[((FLD (f_srcdst)) + (3))]) = opval;
- TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-const:-WI-3", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-add:-VM-index-of-dst-3", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -4783,7 +4951,7 @@ SEM_FN_NAME (i960base,stl_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -4796,7 +4964,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (FLD (f_offset), 4), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -4813,7 +4981,7 @@ SEM_FN_NAME (i960base,stl_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_ar
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -4826,7 +4994,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_offset), * FLD (i_abase)), 4), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -4843,7 +5011,7 @@ SEM_FN_NAME (i960base,stl_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -4856,7 +5024,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_abase), 4), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -4873,7 +5041,7 @@ SEM_FN_NAME (i960base,stl_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -4886,7 +5054,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 4), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -4903,7 +5071,7 @@ SEM_FN_NAME (i960base,stl_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -4916,7 +5084,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), 4), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -4933,7 +5101,7 @@ SEM_FN_NAME (i960base,stl_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -4946,7 +5114,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), * FLD (i_abase)), 4), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -4963,7 +5131,7 @@ SEM_FN_NAME (i960base,stl_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -4976,7 +5144,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 4), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -4993,7 +5161,7 @@ SEM_FN_NAME (i960base,stl_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG se
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -5006,7 +5174,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))), 4), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -5023,7 +5191,7 @@ SEM_FN_NAME (i960base,stt_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -5041,7 +5209,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (FLD (f_offset), 8), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -5058,7 +5226,7 @@ SEM_FN_NAME (i960base,stt_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_ar
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -5076,7 +5244,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_offset), * FLD (i_abase)), 8), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -5093,7 +5261,7 @@ SEM_FN_NAME (i960base,stt_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -5111,7 +5279,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_abase), 8), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -5128,7 +5296,7 @@ SEM_FN_NAME (i960base,stt_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -5146,7 +5314,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 8), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -5163,7 +5331,7 @@ SEM_FN_NAME (i960base,stt_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -5181,7 +5349,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), 8), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -5198,7 +5366,7 @@ SEM_FN_NAME (i960base,stt_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -5216,7 +5384,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), * FLD (i_abase)), 8), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -5233,7 +5401,7 @@ SEM_FN_NAME (i960base,stt_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -5251,7 +5419,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 8), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -5268,7 +5436,7 @@ SEM_FN_NAME (i960base,stt_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG se
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -5286,7 +5454,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))), 8), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -5303,7 +5471,7 @@ SEM_FN_NAME (i960base,stq_offset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -5326,7 +5494,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (FLD (f_offset), 12), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -5343,7 +5511,7 @@ SEM_FN_NAME (i960base,stq_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_ar
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -5366,7 +5534,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_offset), * FLD (i_abase)), 12), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -5383,7 +5551,7 @@ SEM_FN_NAME (i960base,stq_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -5406,7 +5574,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_abase), 12), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -5423,7 +5591,7 @@ SEM_FN_NAME (i960base,stq_indirect_index) (SIM_CPU *current_cpu, SEM_ARG sem_arg
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -5446,7 +5614,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 12), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -5463,7 +5631,7 @@ SEM_FN_NAME (i960base,stq_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -5486,7 +5654,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (FLD (f_optdisp), 12), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -5503,7 +5671,7 @@ SEM_FN_NAME (i960base,stq_indirect_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -5526,7 +5694,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), * FLD (i_abase)), 12), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -5543,7 +5711,7 @@ SEM_FN_NAME (i960base,stq_index_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -5566,7 +5734,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale)))), 12), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -5583,7 +5751,7 @@ SEM_FN_NAME (i960base,stq_indirect_index_disp) (SIM_CPU *current_cpu, SEM_ARG se
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
+{
SI tmp_sregno;
tmp_sregno = FLD (f_srcdst);
{
@@ -5606,7 +5774,7 @@ do {
SETMEMSI (current_cpu, pc, ADDSI (ADDSI (FLD (f_optdisp), ADDSI (* FLD (i_abase), MULSI (* FLD (i_index), SLLSI (1, FLD (f_scale))))), 12), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
-} while (0);
+}
return vpc;
#undef FLD
@@ -6382,7 +6550,7 @@ SEM_FN_NAME (i960base,cmpi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
SI opval = (LTSI (* FLD (i_src1), * FLD (i_src2))) ? (4) : (EQSI (* FLD (i_src1), * FLD (i_src2))) ? (2) : (1);
CPU (h_cc) = opval;
- TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "cc", 'x', opval);
}
return vpc;
@@ -6403,7 +6571,7 @@ SEM_FN_NAME (i960base,cmpi1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
SI opval = (LTSI (FLD (f_src1), * FLD (i_src2))) ? (4) : (EQSI (FLD (f_src1), * FLD (i_src2))) ? (2) : (1);
CPU (h_cc) = opval;
- TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "cc", 'x', opval);
}
return vpc;
@@ -6424,7 +6592,7 @@ SEM_FN_NAME (i960base,cmpi2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
SI opval = (LTSI (* FLD (i_src1), FLD (f_src2))) ? (4) : (EQSI (* FLD (i_src1), FLD (f_src2))) ? (2) : (1);
CPU (h_cc) = opval;
- TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "cc", 'x', opval);
}
return vpc;
@@ -6445,7 +6613,7 @@ SEM_FN_NAME (i960base,cmpi3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
SI opval = (LTSI (FLD (f_src1), FLD (f_src2))) ? (4) : (EQSI (FLD (f_src1), FLD (f_src2))) ? (2) : (1);
CPU (h_cc) = opval;
- TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "cc", 'x', opval);
}
return vpc;
@@ -6466,7 +6634,7 @@ SEM_FN_NAME (i960base,cmpo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
SI opval = (LTUSI (* FLD (i_src1), * FLD (i_src2))) ? (4) : (EQSI (* FLD (i_src1), * FLD (i_src2))) ? (2) : (1);
CPU (h_cc) = opval;
- TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "cc", 'x', opval);
}
return vpc;
@@ -6487,7 +6655,7 @@ SEM_FN_NAME (i960base,cmpo1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
SI opval = (LTUSI (FLD (f_src1), * FLD (i_src2))) ? (4) : (EQSI (FLD (f_src1), * FLD (i_src2))) ? (2) : (1);
CPU (h_cc) = opval;
- TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "cc", 'x', opval);
}
return vpc;
@@ -6508,7 +6676,7 @@ SEM_FN_NAME (i960base,cmpo2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
SI opval = (LTUSI (* FLD (i_src1), FLD (f_src2))) ? (4) : (EQSI (* FLD (i_src1), FLD (f_src2))) ? (2) : (1);
CPU (h_cc) = opval;
- TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "cc", 'x', opval);
}
return vpc;
@@ -6529,7 +6697,7 @@ SEM_FN_NAME (i960base,cmpo3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
SI opval = (LTUSI (FLD (f_src1), FLD (f_src2))) ? (4) : (EQSI (FLD (f_src1), FLD (f_src2))) ? (2) : (1);
CPU (h_cc) = opval;
- TRACE_RESULT (current_cpu, abuf, "cc-0", 'x', opval);
+ TRACE_RESULT (current_cpu, abuf, "cc", 'x', opval);
}
return vpc;
@@ -7070,7 +7238,7 @@ SEM_FN_NAME (i960base,callx_disp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_BRANCH_INIT
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
-do {
+{
SI tmp_temp;
tmp_temp = ANDSI (ADDSI (CPU (h_gr[((UINT) 1)]), 63), INVSI (63));
{
@@ -7130,7 +7298,7 @@ CPU (h_gr[((UINT) 15)]) = 0xdeadbeef;
CPU (h_gr[((UINT) 1)]) = opval;
TRACE_RESULT (current_cpu, abuf, "gr-1", 'x', opval);
}
-} while (0);
+}
SEM_BRANCH_FINI (vpc);
return vpc;
@@ -7149,7 +7317,7 @@ SEM_FN_NAME (i960base,callx_indirect) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_BRANCH_INIT
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
+{
SI tmp_temp;
tmp_temp = ANDSI (ADDSI (CPU (h_gr[((UINT) 1)]), 63), INVSI (63));
{
@@ -7209,7 +7377,7 @@ CPU (h_gr[((UINT) 15)]) = 0xdeadbeef;
CPU (h_gr[((UINT) 1)]) = opval;
TRACE_RESULT (current_cpu, abuf, "gr-1", 'x', opval);
}
-} while (0);
+}
SEM_BRANCH_FINI (vpc);
return vpc;
@@ -7228,7 +7396,7 @@ SEM_FN_NAME (i960base,callx_indirect_offset) (SIM_CPU *current_cpu, SEM_ARG sem_
SEM_BRANCH_INIT
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
+{
SI tmp_temp;
tmp_temp = ANDSI (ADDSI (CPU (h_gr[((UINT) 1)]), 63), INVSI (63));
{
@@ -7288,7 +7456,7 @@ CPU (h_gr[((UINT) 15)]) = 0xdeadbeef;
CPU (h_gr[((UINT) 1)]) = opval;
TRACE_RESULT (current_cpu, abuf, "gr-1", 'x', opval);
}
-} while (0);
+}
SEM_BRANCH_FINI (vpc);
return vpc;
@@ -7307,7 +7475,7 @@ SEM_FN_NAME (i960base,ret) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_BRANCH_INIT
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-do {
+{
{
SI opval = CPU (h_gr[((UINT) 0)]);
CPU (h_gr[((UINT) 31)]) = opval;
@@ -7334,7 +7502,7 @@ CPU (h_gr[((UINT) 15)]) = GETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 31
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
-} while (0);
+}
SEM_BRANCH_FINI (vpc);
return vpc;
diff --git a/sim/i960/sim-if.c b/sim/i960/sim-if.c
index 3a58548..6179739 100644
--- a/sim/i960/sim-if.c
+++ b/sim/i960/sim-if.c
@@ -31,7 +31,7 @@ static void free_state (SIM_DESC);
disassembler. */
static CGEN_DISASSEMBLER i960_disassemble_insn;
-/* Records simulator descriptor so utilities like m32r_dump_regs can be
+/* Records simulator descriptor so utilities like i960_dump_regs can be
called from gdb. */
SIM_DESC current_state;
@@ -145,8 +145,8 @@ sim_open (kind, callback, abfd, argv)
/* Open a copy of the cpu descriptor table. */
{
- CGEN_CPU_DESC cd = i960_cgen_cpu_open (STATE_ARCHITECTURE (sd)->mach,
- CGEN_ENDIAN_LITTLE);
+ CGEN_CPU_DESC cd = i960_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name,
+ CGEN_ENDIAN_LITTLE);
for (i = 0; i < MAX_NR_PROCESSORS; ++i)
{
SIM_CPU *cpu = STATE_CPU (sd, i);
@@ -156,10 +156,10 @@ sim_open (kind, callback, abfd, argv)
}
/* Initialize various cgen things not done by common framework.
- Must be done after m32r_cgen_cpu_open. */
+ Must be done after i960_cgen_cpu_open. */
cgen_init (sd);
- /* Store in a global so things like sparc32_dump_regs can be invoked
+ /* Store in a global so things like i960_dump_regs can be invoked
from the gdb command line. */
current_state = sd;
generated by cgit v1.1 at 2024-12-03 19:47:07 +0000