diff options
| author | James Bowman <jamesb@excamera.com> | 2017-11-01 18:34:25 -0700 |
|---|---|---|
| committer | James Bowman <jamesb@excamera.com> | 2017-11-01 18:36:51 -0700 |
| commit | dcc31d286ad05aa93577181f9a8292009622363e (patch) | |
| tree | f455afb6e8e5f4ff9c702fa00d129091f94e9be5 /sim/ft32 | |
| parent | 89f3c4b6b9b565720f88636d966f22923c03e9cb (diff) | |
| download | gdb-dcc31d286ad05aa93577181f9a8292009622363e.zip gdb-dcc31d286ad05aa93577181f9a8292009622363e.tar.gz gdb-dcc31d286ad05aa93577181f9a8292009622363e.tar.bz2 | |
FT32: support for FT32B processor - part 2/2
FT32B is a new FT32 family member.
This patch adds support for the compressed instructions to gdb and sim.
gdb/ChangeLog:
* ft32-tdep.c (ft32_fetch_instruction): New function.
(ft32_analyze_prologue): Use ft32_fetch_instruction().
sim/ChangeLog:
* ft32/interp.c (step_once): Add ft32 shortcode decoder.
Diffstat (limited to 'sim/ft32')
| -rw-r--r-- | sim/ft32/interp.c | 22 |
1 files changed, 15 insertions, 7 deletions
diff --git a/sim/ft32/interp.c b/sim/ft32/interp.c index 3bc08ee..d73d4d0 100644 --- a/sim/ft32/interp.c +++ b/sim/ft32/interp.c @@ -340,16 +340,24 @@ step_once (SIM_DESC sd) uint32_t bit_len; uint32_t upper; uint32_t insnpc; + unsigned int sc[2]; + int isize; - if (cpu->state.cycles >= cpu->state.next_tick_cycle) - { - cpu->state.next_tick_cycle += 100000; - ft32_push (sd, cpu->state.pc); - cpu->state.pc = 12; /* interrupt 1. */ - } inst = ft32_read_item (sd, 2, cpu->state.pc); cpu->state.cycles += 1; + if ((STATE_ARCHITECTURE (sd)->mach == bfd_mach_ft32b) + && ft32_decode_shortcode (cpu->state.pc, inst, sc)) + { + if ((cpu->state.pc & 3) == 0) + inst = sc[0]; + else + inst = sc[1]; + isize = 2; + } + else + isize = 4; + /* Handle "call 8" (which is FT32's "break" equivalent) here. */ if (inst == 0x00340002) { @@ -390,7 +398,7 @@ step_once (SIM_DESC sd) upper = (inst >> 27); insnpc = cpu->state.pc; - cpu->state.pc += 4; + cpu->state.pc += isize; switch (upper) { case FT32_PAT_TOC: |