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| author | Richard Sandiford <rdsandiford@googlemail.com> | 2004-03-01 09:42:33 +0000 |
|---|---|---|
| committer | Richard Sandiford <rdsandiford@googlemail.com> | 2004-03-01 09:42:33 +0000 |
| commit | c7a48b9ac9215f67421a769c2986b6eb2a69780b (patch) | |
| tree | 7b7c194a858c08b0cbf6bff28a4689eda00f46a3 /sim/frv/interrupts.c | |
| parent | 8b73069fed6ec6b73e35eccdf186887d89ecb84b (diff) | |
| download | gdb-c7a48b9ac9215f67421a769c2986b6eb2a69780b.zip gdb-c7a48b9ac9215f67421a769c2986b6eb2a69780b.tar.gz gdb-c7a48b9ac9215f67421a769c2986b6eb2a69780b.tar.bz2 | |
cpu/
* frv.cpu (nsdiv, nudiv, nsdivi, nudivi): Remove fr400 profiling unit.
(scutss): Change unit to I0.
(calll, callil, ccalll): Add missing FR550-MAJOR and profile unit.
(mqsaths): Fix FR400-MAJOR categorization.
(media-quad-multiply-cross-acc, media-quad-cross-multiply-cross-acc)
(media-quad-cross-multiply-acc): Change unit from MDUALACC to FMALL.
* frv.opc (fr400_check_insn_major_constraints): Check for (M-2,M-1)
combinations.
opcodes/
* frv-desc.c, frv-opc.c: Regenerate.
sim/frv/
* cache.c (frv_cache_init): Change fr400 cache statistics to match
the fr405.
(non_cache_access): Add missing breaks.
* interrupts.c (set_exception_status_registers): Always set EAR15
for data_access_errors.
* memory.c (fr400_check_write_address): Remove redundant alignment
check.
* model.c: Regenerate.
Diffstat (limited to 'sim/frv/interrupts.c')
| -rw-r--r-- | sim/frv/interrupts.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/sim/frv/interrupts.c b/sim/frv/interrupts.c index 540ee06..1496fc5 100644 --- a/sim/frv/interrupts.c +++ b/sim/frv/interrupts.c @@ -845,8 +845,7 @@ set_exception_status_registers ( break; case FRV_DATA_ACCESS_ERROR: reg_index = 15; /* Use ESR15, EPCR15. */ - if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr400) - set_ear = 1; + set_ear = 1; break; case FRV_DATA_ACCESS_EXCEPTION: set_daec = 1; |