diff options
| author | Stan Shebs <shebs@codesourcery.com> | 1999-04-26 18:34:20 +0000 |
|---|---|---|
| committer | Stan Shebs <shebs@codesourcery.com> | 1999-04-26 18:34:20 +0000 |
| commit | 7a292a7adf506b866905b06b3024c0fd411c4583 (patch) | |
| tree | 5b208bb48269b8a82d5c3a5f19c87b45a62a22f4 /sim/fr30 | |
| parent | 1996fae84682e8ddd146215dd2959ad1ec924c09 (diff) | |
| download | gdb-7a292a7adf506b866905b06b3024c0fd411c4583.zip gdb-7a292a7adf506b866905b06b3024c0fd411c4583.tar.gz gdb-7a292a7adf506b866905b06b3024c0fd411c4583.tar.bz2 | |
import gdb-19990422 snapshot
Diffstat (limited to 'sim/fr30')
| -rw-r--r-- | sim/fr30/ChangeLog | 41 | ||||
| -rw-r--r-- | sim/fr30/arch.c | 660 | ||||
| -rw-r--r-- | sim/fr30/arch.h | 42 | ||||
| -rw-r--r-- | sim/fr30/configure | 2 | ||||
| -rw-r--r-- | sim/fr30/configure.in | 2 | ||||
| -rw-r--r-- | sim/fr30/cpu.c | 1 | ||||
| -rw-r--r-- | sim/fr30/cpu.h | 66 | ||||
| -rw-r--r-- | sim/fr30/decode.c | 1233 | ||||
| -rw-r--r-- | sim/fr30/devices.c | 13 | ||||
| -rw-r--r-- | sim/fr30/fr30-sim.h | 12 | ||||
| -rw-r--r-- | sim/fr30/fr30.c | 16 | ||||
| -rw-r--r-- | sim/fr30/model.c | 2 | ||||
| -rw-r--r-- | sim/fr30/sem-switch.c | 624 | ||||
| -rw-r--r-- | sim/fr30/sem.c | 624 | ||||
| -rw-r--r-- | sim/fr30/sim-if.c | 4 | ||||
| -rw-r--r-- | sim/fr30/traps.c | 34 |
16 files changed, 1402 insertions, 1974 deletions
diff --git a/sim/fr30/ChangeLog b/sim/fr30/ChangeLog index dd399aa..7d0f18d 100644 --- a/sim/fr30/ChangeLog +++ b/sim/fr30/ChangeLog @@ -1,3 +1,44 @@ +Fri Apr 16 16:50:31 1999 Doug Evans <devans@charmed.cygnus.com> + + * devices.c (device_io_read_buffer): New arg `sd'. + (device_io_write_buffer): New arg `sd'. + (device_error): Give proper arg spec. + +1999-04-10 Doug Evans <devans@casey.cygnus.com> + + * cpu.h,sem-switch.c,sem.c: Rebuild. + +1999-03-27 Doug Evans <devans@casey.cygnus.com> + + * decode.c: Rebuild. + +1999-03-22 Doug Evans <devans@casey.cygnus.com> + + * arch.c,arch.h,model.c: Rebuild. + * fr30.c (fr30bf_fetch_register): Replace calls to a_fr30_h_* with + calls to fr30bf_h_*. + (fr30bf_store_register): Ditto. + * traps.c (setup_int): Ditto. + * sim-if.c (sim_open): Update call to fr30_cgen_cpu_open. + +Mon Mar 22 13:13:05 1999 Dave Brolley <brolley@cygnus.com> + + * configure.in: Use SIM_AC_OPTION_ALIGNMENT(FORCED_ALIGNMENT). + * configure: Regenerate. + * cpu.h: Regenerate. + +1999-03-11 Doug Evans <devans@casey.cygnus.com> + + * arch.c,arch.h,cpu.c,cpu.h: Rebuild. + * fr30-sim.h (GET_H_SBIT,SET_H_SBIT): Delete. + (GET_H_CCR,SET_H_CCR,GET_H_SCR,SET_H_SCR,GET_H_ILM,SET_H_ILM): Delete. + (GET_H_PS,SET_H_PS,GET_H_DR,SET_H_DR): Delete. + * sim-if.c (sim_open): Update call to fr30_cgen_cpu_open. + +1999-02-25 Doug Evans <devans@casey.cygnus.com> + + * cpu.h: Rebuild. + 1999-02-09 Doug Evans <devans@casey.cygnus.com> * Makefile.in (SIM_EXTRA_DEPS): Add fr30-desc.h, delete cpu-opc.h. diff --git a/sim/fr30/arch.c b/sim/fr30/arch.c index db6e23e..55eea0d 100644 --- a/sim/fr30/arch.c +++ b/sim/fr30/arch.c @@ -33,663 +33,3 @@ const MACH *sim_machs[] = 0 }; -/* Get the value of h-pc. */ - -USI -a_fr30_h_pc_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - return fr30bf_h_pc_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-pc. */ - -void -a_fr30_h_pc_set (SIM_CPU *current_cpu, USI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - fr30bf_h_pc_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-gr. */ - -SI -a_fr30_h_gr_get (SIM_CPU *current_cpu, UINT regno) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - return fr30bf_h_gr_get (current_cpu, regno); -#endif - default : - abort (); - } -} - -/* Set a value for h-gr. */ - -void -a_fr30_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - fr30bf_h_gr_set (current_cpu, regno, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-cr. */ - -SI -a_fr30_h_cr_get (SIM_CPU *current_cpu, UINT regno) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - return fr30bf_h_cr_get (current_cpu, regno); -#endif - default : - abort (); - } -} - -/* Set a value for h-cr. */ - -void -a_fr30_h_cr_set (SIM_CPU *current_cpu, UINT regno, SI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - fr30bf_h_cr_set (current_cpu, regno, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-dr. */ - -SI -a_fr30_h_dr_get (SIM_CPU *current_cpu, UINT regno) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - return fr30bf_h_dr_get (current_cpu, regno); -#endif - default : - abort (); - } -} - -/* Set a value for h-dr. */ - -void -a_fr30_h_dr_set (SIM_CPU *current_cpu, UINT regno, SI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - fr30bf_h_dr_set (current_cpu, regno, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-ps. */ - -USI -a_fr30_h_ps_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - return fr30bf_h_ps_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-ps. */ - -void -a_fr30_h_ps_set (SIM_CPU *current_cpu, USI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - fr30bf_h_ps_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-r13. */ - -SI -a_fr30_h_r13_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - return fr30bf_h_r13_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-r13. */ - -void -a_fr30_h_r13_set (SIM_CPU *current_cpu, SI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - fr30bf_h_r13_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-r14. */ - -SI -a_fr30_h_r14_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - return fr30bf_h_r14_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-r14. */ - -void -a_fr30_h_r14_set (SIM_CPU *current_cpu, SI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - fr30bf_h_r14_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-r15. */ - -SI -a_fr30_h_r15_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - return fr30bf_h_r15_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-r15. */ - -void -a_fr30_h_r15_set (SIM_CPU *current_cpu, SI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - fr30bf_h_r15_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-nbit. */ - -BI -a_fr30_h_nbit_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - return fr30bf_h_nbit_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-nbit. */ - -void -a_fr30_h_nbit_set (SIM_CPU *current_cpu, BI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - fr30bf_h_nbit_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-zbit. */ - -BI -a_fr30_h_zbit_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - return fr30bf_h_zbit_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-zbit. */ - -void -a_fr30_h_zbit_set (SIM_CPU *current_cpu, BI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - fr30bf_h_zbit_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-vbit. */ - -BI -a_fr30_h_vbit_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - return fr30bf_h_vbit_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-vbit. */ - -void -a_fr30_h_vbit_set (SIM_CPU *current_cpu, BI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - fr30bf_h_vbit_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-cbit. */ - -BI -a_fr30_h_cbit_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - return fr30bf_h_cbit_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-cbit. */ - -void -a_fr30_h_cbit_set (SIM_CPU *current_cpu, BI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - fr30bf_h_cbit_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-ibit. */ - -BI -a_fr30_h_ibit_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - return fr30bf_h_ibit_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-ibit. */ - -void -a_fr30_h_ibit_set (SIM_CPU *current_cpu, BI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - fr30bf_h_ibit_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-sbit. */ - -BI -a_fr30_h_sbit_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - return fr30bf_h_sbit_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-sbit. */ - -void -a_fr30_h_sbit_set (SIM_CPU *current_cpu, BI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - fr30bf_h_sbit_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-tbit. */ - -BI -a_fr30_h_tbit_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - return fr30bf_h_tbit_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-tbit. */ - -void -a_fr30_h_tbit_set (SIM_CPU *current_cpu, BI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - fr30bf_h_tbit_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-d0bit. */ - -BI -a_fr30_h_d0bit_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - return fr30bf_h_d0bit_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-d0bit. */ - -void -a_fr30_h_d0bit_set (SIM_CPU *current_cpu, BI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - fr30bf_h_d0bit_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-d1bit. */ - -BI -a_fr30_h_d1bit_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - return fr30bf_h_d1bit_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-d1bit. */ - -void -a_fr30_h_d1bit_set (SIM_CPU *current_cpu, BI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - fr30bf_h_d1bit_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-ccr. */ - -UQI -a_fr30_h_ccr_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - return fr30bf_h_ccr_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-ccr. */ - -void -a_fr30_h_ccr_set (SIM_CPU *current_cpu, UQI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - fr30bf_h_ccr_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-scr. */ - -UQI -a_fr30_h_scr_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - return fr30bf_h_scr_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-scr. */ - -void -a_fr30_h_scr_set (SIM_CPU *current_cpu, UQI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - fr30bf_h_scr_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - -/* Get the value of h-ilm. */ - -UQI -a_fr30_h_ilm_get (SIM_CPU *current_cpu) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - return fr30bf_h_ilm_get (current_cpu); -#endif - default : - abort (); - } -} - -/* Set a value for h-ilm. */ - -void -a_fr30_h_ilm_set (SIM_CPU *current_cpu, UQI newval) -{ - switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach) - { -#ifdef HAVE_CPU_FR30BF - case bfd_mach_fr30 : - fr30bf_h_ilm_set (current_cpu, newval); - break; -#endif - default : - abort (); - } -} - diff --git a/sim/fr30/arch.h b/sim/fr30/arch.h index 7bde11d..ffc516e 100644 --- a/sim/fr30/arch.h +++ b/sim/fr30/arch.h @@ -27,48 +27,6 @@ with this program; if not, write to the Free Software Foundation, Inc., #define TARGET_BIG_ENDIAN 1 -/* Cover fns for register access. */ -USI a_fr30_h_pc_get (SIM_CPU *); -void a_fr30_h_pc_set (SIM_CPU *, USI); -SI a_fr30_h_gr_get (SIM_CPU *, UINT); -void a_fr30_h_gr_set (SIM_CPU *, UINT, SI); -SI a_fr30_h_cr_get (SIM_CPU *, UINT); -void a_fr30_h_cr_set (SIM_CPU *, UINT, SI); -SI a_fr30_h_dr_get (SIM_CPU *, UINT); -void a_fr30_h_dr_set (SIM_CPU *, UINT, SI); -USI a_fr30_h_ps_get (SIM_CPU *); -void a_fr30_h_ps_set (SIM_CPU *, USI); -SI a_fr30_h_r13_get (SIM_CPU *); -void a_fr30_h_r13_set (SIM_CPU *, SI); -SI a_fr30_h_r14_get (SIM_CPU *); -void a_fr30_h_r14_set (SIM_CPU *, SI); -SI a_fr30_h_r15_get (SIM_CPU *); -void a_fr30_h_r15_set (SIM_CPU *, SI); -BI a_fr30_h_nbit_get (SIM_CPU *); -void a_fr30_h_nbit_set (SIM_CPU *, BI); -BI a_fr30_h_zbit_get (SIM_CPU *); -void a_fr30_h_zbit_set (SIM_CPU *, BI); -BI a_fr30_h_vbit_get (SIM_CPU *); -void a_fr30_h_vbit_set (SIM_CPU *, BI); -BI a_fr30_h_cbit_get (SIM_CPU *); -void a_fr30_h_cbit_set (SIM_CPU *, BI); -BI a_fr30_h_ibit_get (SIM_CPU *); -void a_fr30_h_ibit_set (SIM_CPU *, BI); -BI a_fr30_h_sbit_get (SIM_CPU *); -void a_fr30_h_sbit_set (SIM_CPU *, BI); -BI a_fr30_h_tbit_get (SIM_CPU *); -void a_fr30_h_tbit_set (SIM_CPU *, BI); -BI a_fr30_h_d0bit_get (SIM_CPU *); -void a_fr30_h_d0bit_set (SIM_CPU *, BI); -BI a_fr30_h_d1bit_get (SIM_CPU *); -void a_fr30_h_d1bit_set (SIM_CPU *, BI); -UQI a_fr30_h_ccr_get (SIM_CPU *); -void a_fr30_h_ccr_set (SIM_CPU *, UQI); -UQI a_fr30_h_scr_get (SIM_CPU *); -void a_fr30_h_scr_set (SIM_CPU *, UQI); -UQI a_fr30_h_ilm_get (SIM_CPU *); -void a_fr30_h_ilm_set (SIM_CPU *, UQI); - /* Enum declaration for model types. */ typedef enum model_type { MODEL_FR30_1, MODEL_MAX diff --git a/sim/fr30/configure b/sim/fr30/configure index 43063ad..b650e0c 100644 --- a/sim/fr30/configure +++ b/sim/fr30/configure @@ -3482,7 +3482,7 @@ else fi fi -wire_alignment="NONSTRICT_ALIGNMENT" +wire_alignment="FORCED_ALIGNMENT" default_alignment="" # Check whether --enable-sim-alignment or --disable-sim-alignment was given. diff --git a/sim/fr30/configure.in b/sim/fr30/configure.in index fc25dfc..cb01e13 100644 --- a/sim/fr30/configure.in +++ b/sim/fr30/configure.in @@ -6,7 +6,7 @@ AC_INIT(Makefile.in) SIM_AC_COMMON SIM_AC_OPTION_ENDIAN(BIG_ENDIAN) -SIM_AC_OPTION_ALIGNMENT(NONSTRICT_ALIGNMENT) +SIM_AC_OPTION_ALIGNMENT(FORCED_ALIGNMENT) SIM_AC_OPTION_HOSTENDIAN SIM_AC_OPTION_SCACHE(16384) SIM_AC_OPTION_DEFAULT_MODEL(fr30-1) diff --git a/sim/fr30/cpu.c b/sim/fr30/cpu.c index c339a93..fb94688 100644 --- a/sim/fr30/cpu.c +++ b/sim/fr30/cpu.c @@ -26,6 +26,7 @@ with this program; if not, write to the Free Software Foundation, Inc., #define WANT_CPU_FR30BF #include "sim-main.h" +#include "cgen-ops.h" /* Get the value of h-pc. */ diff --git a/sim/fr30/cpu.h b/sim/fr30/cpu.h index 9a02863..13aceb4 100644 --- a/sim/fr30/cpu.h +++ b/sim/fr30/cpu.h @@ -50,21 +50,27 @@ typedef struct { #define SET_H_CR(a1, x) (CPU (h_cr)[a1] = (x)) /* dedicated registers */ SI h_dr[6]; -/* GET_H_DR macro user-written */ -/* SET_H_DR macro user-written */ - /* program status */ +#define GET_H_DR(index) fr30bf_h_dr_get_handler (current_cpu, index) +#define SET_H_DR(index, x) \ +do { \ +fr30bf_h_dr_set_handler (current_cpu, (index), (x));\ +} while (0) + /* processor status */ USI h_ps; -/* GET_H_PS macro user-written */ -/* SET_H_PS macro user-written */ - /* General Register 13 explicitely required */ +#define GET_H_PS() fr30bf_h_ps_get_handler (current_cpu) +#define SET_H_PS(x) \ +do { \ +fr30bf_h_ps_set_handler (current_cpu, (x));\ +} while (0) + /* General Register 13 explicitly required */ SI h_r13; #define GET_H_R13() CPU (h_r13) #define SET_H_R13(x) (CPU (h_r13) = (x)) - /* General Register 14 explicitely required */ + /* General Register 14 explicitly required */ SI h_r14; #define GET_H_R14() CPU (h_r14) #define SET_H_R14(x) (CPU (h_r14) = (x)) - /* General Register 15 explicitely required */ + /* General Register 15 explicitly required */ SI h_r15; #define GET_H_R15() CPU (h_r15) #define SET_H_R15(x) (CPU (h_r15) = (x)) @@ -88,10 +94,13 @@ typedef struct { BI h_ibit; #define GET_H_IBIT() CPU (h_ibit) #define SET_H_IBIT(x) (CPU (h_ibit) = (x)) - /* stack bit */ + /* stack bit */ BI h_sbit; -/* GET_H_SBIT macro user-written */ -/* SET_H_SBIT macro user-written */ +#define GET_H_SBIT() fr30bf_h_sbit_get_handler (current_cpu) +#define SET_H_SBIT(x) \ +do { \ +fr30bf_h_sbit_set_handler (current_cpu, (x));\ +} while (0) /* trace trap bit */ BI h_tbit; #define GET_H_TBIT() CPU (h_tbit) @@ -104,18 +113,27 @@ typedef struct { BI h_d1bit; #define GET_H_D1BIT() CPU (h_d1bit) #define SET_H_D1BIT(x) (CPU (h_d1bit) = (x)) - /* condition code bits */ + /* condition code bits */ UQI h_ccr; -/* GET_H_CCR macro user-written */ -/* SET_H_CCR macro user-written */ +#define GET_H_CCR() fr30bf_h_ccr_get_handler (current_cpu) +#define SET_H_CCR(x) \ +do { \ +fr30bf_h_ccr_set_handler (current_cpu, (x));\ +} while (0) /* system condition bits */ UQI h_scr; -/* GET_H_SCR macro user-written */ -/* SET_H_SCR macro user-written */ - /* interrupt level mask */ +#define GET_H_SCR() fr30bf_h_scr_get_handler (current_cpu) +#define SET_H_SCR(x) \ +do { \ +fr30bf_h_scr_set_handler (current_cpu, (x));\ +} while (0) + /* interrupt level mask */ UQI h_ilm; -/* GET_H_ILM macro user-written */ -/* SET_H_ILM macro user-written */ +#define GET_H_ILM() fr30bf_h_ilm_get_handler (current_cpu) +#define SET_H_ILM(x) \ +do { \ +fr30bf_h_ilm_set_handler (current_cpu, (x));\ +} while (0) } hardware; #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware) } FR30BF_CPU_DATA; @@ -918,9 +936,9 @@ struct scache { f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ f_i20_4 = EXTRACT_UINT (insn, 16, 8, 4); \ f_i20_16 = (0|(EXTRACT_UINT (word_1, 16, 0, 16) << 0)); \ -do {\ +{\ f_i20 = ((((f_i20_4) << (16))) | (f_i20_16));\ -} while (0);\ +}\ f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \ f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \ @@ -933,12 +951,14 @@ do {\ UINT f_Ri; \ /* Contents of trailing part of insn. */ \ UINT word_1; \ + UINT word_2; \ unsigned int length; #define EXTRACT_IFMT_LDI32_CODE \ length = 6; \ - word_1 = GETIMEMUSI (current_cpu, pc + 2); \ + word_1 = GETIMEMUHI (current_cpu, pc + 2); \ + word_2 = GETIMEMUHI (current_cpu, pc + 4); \ f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_i32 = (0|(EXTRACT_UINT (word_1, 32, 0, 32) << 0)); \ + f_i32 = (0|(EXTRACT_UINT (word_2, 16, 0, 16) << 0)|(EXTRACT_UINT (word_1, 16, 0, 16) << 16)); \ f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \ f_op3 = EXTRACT_UINT (insn, 16, 8, 4); \ f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \ diff --git a/sim/fr30/decode.c b/sim/fr30/decode.c index c6d1656..e41c45f 100644 --- a/sim/fr30/decode.c +++ b/sim/fr30/decode.c @@ -46,6 +46,11 @@ with this program; if not, write to the Free Software Foundation, Inc., #define FAST(fn) #endif +/* The INSN_ prefix is not here and is instead part of the `insn' argument + to avoid collisions with header files (e.g. `AND' in ansidecl.h). */ +#define IDX(insn) CONCAT2 (FR30BF_,insn) +#define TYPE(insn) CONCAT2 (FR30_,insn) + /* The instruction descriptor array. This is computed at runtime. Space for it is not malloc'd to save a teensy bit of cpu in the decoder. Moving it to malloc space is trivial @@ -53,11 +58,6 @@ with this program; if not, write to the Free Software Foundation, Inc., addition of instructions nor an SMP machine with different cpus). */ static IDESC fr30bf_insn_data[FR30BF_INSN_MAX]; -/* The INSN_ prefix is not here and is instead part of the `insn' argument - to avoid collisions with header files (e.g. `AND' in ansidecl.h). */ -#define IDX(insn) CONCAT2 (FR30BF_,insn) -#define TYPE(insn) CONCAT2 (FR30_,insn) - /* Commas between elements are contained in the macros. Some of these are conditionally compiled out. */ @@ -241,6 +241,9 @@ static const struct insn_sem fr30bf_insn_sem_invalid = VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), FULL (x_invalid) FAST (x_invalid) }; +#undef FMT +#undef FULL +#undef FAST #undef IDX #undef TYPE @@ -302,64 +305,6 @@ fr30bf_init_idesc_table (SIM_CPU *cpu) CPU_IDESC (cpu) = table; } -/* Enum declaration for all instruction semantic formats. */ -typedef enum sfmt { - FMT_EMPTY, FMT_ADD, FMT_ADDI, FMT_ADD2 - , FMT_ADDC, FMT_ADDN, FMT_ADDNI, FMT_ADDN2 - , FMT_CMP, FMT_CMPI, FMT_CMP2, FMT_AND - , FMT_ANDM, FMT_ANDH, FMT_ANDB, FMT_BANDL - , FMT_BTSTL, FMT_MUL, FMT_MULU, FMT_MULH - , FMT_DIV0S, FMT_DIV0U, FMT_DIV1, FMT_DIV2 - , FMT_DIV3, FMT_DIV4S, FMT_LSL, FMT_LSLI - , FMT_LDI8, FMT_LDI20, FMT_LDI32, FMT_LD - , FMT_LDUH, FMT_LDUB, FMT_LDR13, FMT_LDR13UH - , FMT_LDR13UB, FMT_LDR14, FMT_LDR14UH, FMT_LDR14UB - , FMT_LDR15, FMT_LDR15GR, FMT_LDR15DR, FMT_LDR15PS - , FMT_ST, FMT_STH, FMT_STB, FMT_STR13 - , FMT_STR13H, FMT_STR13B, FMT_STR14, FMT_STR14H - , FMT_STR14B, FMT_STR15, FMT_STR15GR, FMT_STR15DR - , FMT_STR15PS, FMT_MOV, FMT_MOVDR, FMT_MOVPS - , FMT_MOV2DR, FMT_MOV2PS, FMT_JMP, FMT_CALLR - , FMT_CALL, FMT_RET, FMT_INT, FMT_INTE - , FMT_RETI, FMT_BRAD, FMT_BNOD, FMT_BEQD - , FMT_BCD, FMT_BND, FMT_BVD, FMT_BLTD - , FMT_BLED, FMT_BLSD, FMT_DMOVR13, FMT_DMOVR13H - , FMT_DMOVR13B, FMT_DMOVR13PI, FMT_DMOVR13PIH, FMT_DMOVR13PIB - , FMT_DMOVR15PI, FMT_DMOV2R13, FMT_DMOV2R13H, FMT_DMOV2R13B - , FMT_DMOV2R13PI, FMT_DMOV2R13PIH, FMT_DMOV2R13PIB, FMT_DMOV2R15PD - , FMT_LDRES, FMT_COPOP, FMT_COPLD, FMT_COPST - , FMT_NOP, FMT_ANDCCR, FMT_STILM, FMT_ADDSP - , FMT_EXTSB, FMT_EXTUB, FMT_EXTSH, FMT_EXTUH - , FMT_LDM0, FMT_LDM1, FMT_STM0, FMT_STM1 - , FMT_ENTER, FMT_LEAVE, FMT_XCHB -} SFMT; - -/* The decoder uses this to record insns and direct extraction handling. */ - -typedef struct { - const IDESC *idesc; -#ifdef __GNUC__ - void *sfmt; -#else - enum sfmt sfmt; -#endif -} DECODE_DESC; - -/* Macro to go from decode phase to extraction phase. */ - -#ifdef __GNUC__ -#define GOTO_EXTRACT(id) goto *(id)->sfmt -#else -#define GOTO_EXTRACT(id) goto extract -#endif - -/* The decoder needs a slightly different computed goto switch control. */ -#ifdef __GNUC__ -#define DECODE_SWITCH(N, X) goto *labels_##N[X]; -#else -#define DECODE_SWITCH(N, X) switch (X) -#endif - /* Given an instruction, return a pointer to its IDESC entry. */ const IDESC * @@ -367,309 +312,342 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, CGEN_INSN_INT base_insn, ARGBUF *abuf) { - /* Result of decoder, used by extractor. */ - const DECODE_DESC *idecode; - - /* First decode the instruction. */ + /* Result of decoder. */ + FR30BF_INSN_TYPE itype; { -#define I(insn) & fr30bf_insn_data[CONCAT2 (FR30BF_,insn)] -#ifdef __GNUC__ -#define E(fmt) && case_ex_##fmt -#else -#define E(fmt) fmt -#endif - CGEN_INSN_INT insn = base_insn; - static const DECODE_DESC idecode_invalid = { I (INSN_X_INVALID), E (FMT_EMPTY) }; - - { -#ifdef __GNUC__ - static const void *labels_0[256] = { - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && case_0_7, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && case_0_23, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && case_0_151, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && case_0_159, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - && default_0, && default_0, && default_0, && default_0, - }; -#endif - static const DECODE_DESC insns[256] = { - { I (INSN_LDR13), E (FMT_LDR13) }, { I (INSN_LDR13UH), E (FMT_LDR13UH) }, - { I (INSN_LDR13UB), E (FMT_LDR13UB) }, { I (INSN_LDR15), E (FMT_LDR15) }, - { I (INSN_LD), E (FMT_LD) }, { I (INSN_LDUH), E (FMT_LDUH) }, - { I (INSN_LDUB), E (FMT_LDUB) }, { 0 }, - { I (INSN_DMOV2R13), E (FMT_DMOV2R13) }, { I (INSN_DMOV2R13H), E (FMT_DMOV2R13H) }, - { I (INSN_DMOV2R13B), E (FMT_DMOV2R13B) }, { I (INSN_DMOV2R15PD), E (FMT_DMOV2R15PD) }, - { I (INSN_DMOV2R13PI), E (FMT_DMOV2R13PI) }, { I (INSN_DMOV2R13PIH), E (FMT_DMOV2R13PIH) }, - { I (INSN_DMOV2R13PIB), E (FMT_DMOV2R13PIB) }, { I (INSN_ENTER), E (FMT_ENTER) }, - { I (INSN_STR13), E (FMT_STR13) }, { I (INSN_STR13H), E (FMT_STR13H) }, - { I (INSN_STR13B), E (FMT_STR13B) }, { I (INSN_STR15), E (FMT_STR15) }, - { I (INSN_ST), E (FMT_ST) }, { I (INSN_STH), E (FMT_STH) }, - { I (INSN_STB), E (FMT_STB) }, { 0 }, - { I (INSN_DMOVR13), E (FMT_DMOVR13) }, { I (INSN_DMOVR13H), E (FMT_DMOVR13H) }, - { I (INSN_DMOVR13B), E (FMT_DMOVR13B) }, { I (INSN_DMOVR15PI), E (FMT_DMOVR15PI) }, - { I (INSN_DMOVR13PI), E (FMT_DMOVR13PI) }, { I (INSN_DMOVR13PIH), E (FMT_DMOVR13PIH) }, - { I (INSN_DMOVR13PIB), E (FMT_DMOVR13PIB) }, { I (INSN_INT), E (FMT_INT) }, - { I (INSN_LDR14), E (FMT_LDR14) }, { I (INSN_LDR14), E (FMT_LDR14) }, - { I (INSN_LDR14), E (FMT_LDR14) }, { I (INSN_LDR14), E (FMT_LDR14) }, - { I (INSN_LDR14), E (FMT_LDR14) }, { I (INSN_LDR14), E (FMT_LDR14) }, - { I (INSN_LDR14), E (FMT_LDR14) }, { I (INSN_LDR14), E (FMT_LDR14) }, - { I (INSN_LDR14), E (FMT_LDR14) }, { I (INSN_LDR14), E (FMT_LDR14) }, - { I (INSN_LDR14), E (FMT_LDR14) }, { I (INSN_LDR14), E (FMT_LDR14) }, - { I (INSN_LDR14), E (FMT_LDR14) }, { I (INSN_LDR14), E (FMT_LDR14) }, - { I (INSN_LDR14), E (FMT_LDR14) }, { I (INSN_LDR14), E (FMT_LDR14) }, - { I (INSN_STR14), E (FMT_STR14) }, { I (INSN_STR14), E (FMT_STR14) }, - { I (INSN_STR14), E (FMT_STR14) }, { I (INSN_STR14), E (FMT_STR14) }, - { I (INSN_STR14), E (FMT_STR14) }, { I (INSN_STR14), E (FMT_STR14) }, - { I (INSN_STR14), E (FMT_STR14) }, { I (INSN_STR14), E (FMT_STR14) }, - { I (INSN_STR14), E (FMT_STR14) }, { I (INSN_STR14), E (FMT_STR14) }, - { I (INSN_STR14), E (FMT_STR14) }, { I (INSN_STR14), E (FMT_STR14) }, - { I (INSN_STR14), E (FMT_STR14) }, { I (INSN_STR14), E (FMT_STR14) }, - { I (INSN_STR14), E (FMT_STR14) }, { I (INSN_STR14), E (FMT_STR14) }, - { I (INSN_LDR14UH), E (FMT_LDR14UH) }, { I (INSN_LDR14UH), E (FMT_LDR14UH) }, - { I (INSN_LDR14UH), E (FMT_LDR14UH) }, { I (INSN_LDR14UH), E (FMT_LDR14UH) }, - { I (INSN_LDR14UH), E (FMT_LDR14UH) }, { I (INSN_LDR14UH), E (FMT_LDR14UH) }, - { I (INSN_LDR14UH), E (FMT_LDR14UH) }, { I (INSN_LDR14UH), E (FMT_LDR14UH) }, - { I (INSN_LDR14UH), E (FMT_LDR14UH) }, { I (INSN_LDR14UH), E (FMT_LDR14UH) }, - { I (INSN_LDR14UH), E (FMT_LDR14UH) }, { I (INSN_LDR14UH), E (FMT_LDR14UH) }, - { I (INSN_LDR14UH), E (FMT_LDR14UH) }, { I (INSN_LDR14UH), E (FMT_LDR14UH) }, - { I (INSN_LDR14UH), E (FMT_LDR14UH) }, { I (INSN_LDR14UH), E (FMT_LDR14UH) }, - { I (INSN_STR14H), E (FMT_STR14H) }, { I (INSN_STR14H), E (FMT_STR14H) }, - { I (INSN_STR14H), E (FMT_STR14H) }, { I (INSN_STR14H), E (FMT_STR14H) }, - { I (INSN_STR14H), E (FMT_STR14H) }, { I (INSN_STR14H), E (FMT_STR14H) }, - { I (INSN_STR14H), E (FMT_STR14H) }, { I (INSN_STR14H), E (FMT_STR14H) }, - { I (INSN_STR14H), E (FMT_STR14H) }, { I (INSN_STR14H), E (FMT_STR14H) }, - { I (INSN_STR14H), E (FMT_STR14H) }, { I (INSN_STR14H), E (FMT_STR14H) }, - { I (INSN_STR14H), E (FMT_STR14H) }, { I (INSN_STR14H), E (FMT_STR14H) }, - { I (INSN_STR14H), E (FMT_STR14H) }, { I (INSN_STR14H), E (FMT_STR14H) }, - { I (INSN_LDR14UB), E (FMT_LDR14UB) }, { I (INSN_LDR14UB), E (FMT_LDR14UB) }, - { I (INSN_LDR14UB), E (FMT_LDR14UB) }, { I (INSN_LDR14UB), E (FMT_LDR14UB) }, - { I (INSN_LDR14UB), E (FMT_LDR14UB) }, { I (INSN_LDR14UB), E (FMT_LDR14UB) }, - { I (INSN_LDR14UB), E (FMT_LDR14UB) }, { I (INSN_LDR14UB), E (FMT_LDR14UB) }, - { I (INSN_LDR14UB), E (FMT_LDR14UB) }, { I (INSN_LDR14UB), E (FMT_LDR14UB) }, - { I (INSN_LDR14UB), E (FMT_LDR14UB) }, { I (INSN_LDR14UB), E (FMT_LDR14UB) }, - { I (INSN_LDR14UB), E (FMT_LDR14UB) }, { I (INSN_LDR14UB), E (FMT_LDR14UB) }, - { I (INSN_LDR14UB), E (FMT_LDR14UB) }, { I (INSN_LDR14UB), E (FMT_LDR14UB) }, - { I (INSN_STR14B), E (FMT_STR14B) }, { I (INSN_STR14B), E (FMT_STR14B) }, - { I (INSN_STR14B), E (FMT_STR14B) }, { I (INSN_STR14B), E (FMT_STR14B) }, - { I (INSN_STR14B), E (FMT_STR14B) }, { I (INSN_STR14B), E (FMT_STR14B) }, - { I (INSN_STR14B), E (FMT_STR14B) }, { I (INSN_STR14B), E (FMT_STR14B) }, - { I (INSN_STR14B), E (FMT_STR14B) }, { I (INSN_STR14B), E (FMT_STR14B) }, - { I (INSN_STR14B), E (FMT_STR14B) }, { I (INSN_STR14B), E (FMT_STR14B) }, - { I (INSN_STR14B), E (FMT_STR14B) }, { I (INSN_STR14B), E (FMT_STR14B) }, - { I (INSN_STR14B), E (FMT_STR14B) }, { I (INSN_STR14B), E (FMT_STR14B) }, - { I (INSN_BANDL), E (FMT_BANDL) }, { I (INSN_BANDH), E (FMT_BANDL) }, - { I (INSN_AND), E (FMT_AND) }, { I (INSN_ANDCCR), E (FMT_ANDCCR) }, - { I (INSN_ANDM), E (FMT_ANDM) }, { I (INSN_ANDH), E (FMT_ANDH) }, - { I (INSN_ANDB), E (FMT_ANDB) }, { I (INSN_STILM), E (FMT_STILM) }, - { I (INSN_BTSTL), E (FMT_BTSTL) }, { I (INSN_BTSTH), E (FMT_BTSTL) }, - { I (INSN_XCHB), E (FMT_XCHB) }, { I (INSN_MOV), E (FMT_MOV) }, - { I (INSN_LDM0), E (FMT_LDM0) }, { I (INSN_LDM1), E (FMT_LDM1) }, - { I (INSN_STM0), E (FMT_STM0) }, { I (INSN_STM1), E (FMT_STM1) }, - { I (INSN_BORL), E (FMT_BANDL) }, { I (INSN_BORH), E (FMT_BANDL) }, - { I (INSN_OR), E (FMT_AND) }, { I (INSN_ORCCR), E (FMT_ANDCCR) }, - { I (INSN_ORM), E (FMT_ANDM) }, { I (INSN_ORH), E (FMT_ANDH) }, - { I (INSN_ORB), E (FMT_ANDB) }, { 0 }, - { I (INSN_BEORL), E (FMT_BANDL) }, { I (INSN_BEORH), E (FMT_BANDL) }, - { I (INSN_EOR), E (FMT_AND) }, { I (INSN_LDI20), E (FMT_LDI20) }, - { I (INSN_EORM), E (FMT_ANDM) }, { I (INSN_EORH), E (FMT_ANDH) }, - { I (INSN_EORB), E (FMT_ANDB) }, { 0 }, - { I (INSN_ADDNI), E (FMT_ADDNI) }, { I (INSN_ADDN2), E (FMT_ADDN2) }, - { I (INSN_ADDN), E (FMT_ADDN) }, { I (INSN_ADDSP), E (FMT_ADDSP) }, - { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADD2), E (FMT_ADD2) }, - { I (INSN_ADD), E (FMT_ADD) }, { I (INSN_ADDC), E (FMT_ADDC) }, - { I (INSN_CMPI), E (FMT_CMPI) }, { I (INSN_CMP2), E (FMT_CMP2) }, - { I (INSN_CMP), E (FMT_CMP) }, { I (INSN_MULU), E (FMT_MULU) }, - { I (INSN_SUB), E (FMT_ADD) }, { I (INSN_SUBC), E (FMT_ADDC) }, - { I (INSN_SUBN), E (FMT_ADDN) }, { I (INSN_MUL), E (FMT_MUL) }, - { I (INSN_LSRI), E (FMT_LSLI) }, { I (INSN_LSR2), E (FMT_LSLI) }, - { I (INSN_LSR), E (FMT_LSL) }, { I (INSN_MOV2DR), E (FMT_MOV2DR) }, - { I (INSN_LSLI), E (FMT_LSLI) }, { I (INSN_LSL2), E (FMT_LSLI) }, - { I (INSN_LSL), E (FMT_LSL) }, { I (INSN_MOVDR), E (FMT_MOVDR) }, - { I (INSN_ASRI), E (FMT_LSLI) }, { I (INSN_ASR2), E (FMT_LSLI) }, - { I (INSN_ASR), E (FMT_LSL) }, { I (INSN_MULUH), E (FMT_MULH) }, - { I (INSN_LDRES), E (FMT_LDRES) }, { I (INSN_STRES), E (FMT_LDRES) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_MULH), E (FMT_MULH) }, - { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, - { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, - { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, - { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, - { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, - { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, - { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, - { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) }, - { I (INSN_CALL), E (FMT_CALL) }, { I (INSN_CALL), E (FMT_CALL) }, - { I (INSN_CALL), E (FMT_CALL) }, { I (INSN_CALL), E (FMT_CALL) }, - { I (INSN_CALL), E (FMT_CALL) }, { I (INSN_CALL), E (FMT_CALL) }, - { I (INSN_CALL), E (FMT_CALL) }, { I (INSN_CALL), E (FMT_CALL) }, - { I (INSN_CALLD), E (FMT_CALL) }, { I (INSN_CALLD), E (FMT_CALL) }, - { I (INSN_CALLD), E (FMT_CALL) }, { I (INSN_CALLD), E (FMT_CALL) }, - { I (INSN_CALLD), E (FMT_CALL) }, { I (INSN_CALLD), E (FMT_CALL) }, - { I (INSN_CALLD), E (FMT_CALL) }, { I (INSN_CALLD), E (FMT_CALL) }, - { I (INSN_BRA), E (FMT_BRAD) }, { I (INSN_BNO), E (FMT_BNOD) }, - { I (INSN_BEQ), E (FMT_BEQD) }, { I (INSN_BNE), E (FMT_BEQD) }, - { I (INSN_BC), E (FMT_BCD) }, { I (INSN_BNC), E (FMT_BCD) }, - { I (INSN_BN), E (FMT_BND) }, { I (INSN_BP), E (FMT_BND) }, - { I (INSN_BV), E (FMT_BVD) }, { I (INSN_BNV), E (FMT_BVD) }, - { I (INSN_BLT), E (FMT_BLTD) }, { I (INSN_BGE), E (FMT_BLTD) }, - { I (INSN_BLE), E (FMT_BLED) }, { I (INSN_BGT), E (FMT_BLED) }, - { I (INSN_BLS), E (FMT_BLSD) }, { I (INSN_BHI), E (FMT_BLSD) }, - { I (INSN_BRAD), E (FMT_BRAD) }, { I (INSN_BNOD), E (FMT_BNOD) }, - { I (INSN_BEQD), E (FMT_BEQD) }, { I (INSN_BNED), E (FMT_BEQD) }, - { I (INSN_BCD), E (FMT_BCD) }, { I (INSN_BNCD), E (FMT_BCD) }, - { I (INSN_BND), E (FMT_BND) }, { I (INSN_BPD), E (FMT_BND) }, - { I (INSN_BVD), E (FMT_BVD) }, { I (INSN_BNVD), E (FMT_BVD) }, - { I (INSN_BLTD), E (FMT_BLTD) }, { I (INSN_BGED), E (FMT_BLTD) }, - { I (INSN_BLED), E (FMT_BLED) }, { I (INSN_BGTD), E (FMT_BLED) }, - { I (INSN_BLSD), E (FMT_BLSD) }, { I (INSN_BHID), E (FMT_BLSD) }, - }; - unsigned int val; - val = (((insn >> 8) & (255 << 0))); - DECODE_SWITCH (0, val) + CGEN_INSN_INT insn = base_insn; + + { + unsigned int val = (((insn >> 8) & (255 << 0))); + switch (val) + { + case 0 : itype = FR30BF_INSN_LDR13; goto extract_fmt_ldr13; + case 1 : itype = FR30BF_INSN_LDR13UH; goto extract_fmt_ldr13uh; + case 2 : itype = FR30BF_INSN_LDR13UB; goto extract_fmt_ldr13ub; + case 3 : itype = FR30BF_INSN_LDR15; goto extract_fmt_ldr15; + case 4 : itype = FR30BF_INSN_LD; goto extract_fmt_ld; + case 5 : itype = FR30BF_INSN_LDUH; goto extract_fmt_lduh; + case 6 : itype = FR30BF_INSN_LDUB; goto extract_fmt_ldub; + case 7 : { - CASE (0, 7) : + unsigned int val = (((insn >> 4) & (15 << 0))); + switch (val) { - static const DECODE_DESC insns[16] = { - { I (INSN_LDR15GR), E (FMT_LDR15GR) }, { I (INSN_MOV2PS), E (FMT_MOV2PS) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_LDR15DR), E (FMT_LDR15DR) }, { I (INSN_LDR15PS), E (FMT_LDR15PS) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 4) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : itype = FR30BF_INSN_LDR15GR; goto extract_fmt_ldr15gr; + case 1 : itype = FR30BF_INSN_MOV2PS; goto extract_fmt_mov2ps; + case 8 : itype = FR30BF_INSN_LDR15DR; goto extract_fmt_ldr15dr; + case 9 : itype = FR30BF_INSN_LDR15PS; goto extract_fmt_ldr15ps; + default : itype = FR30BF_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 23) : + } + case 8 : itype = FR30BF_INSN_DMOV2R13; goto extract_fmt_dmov2r13; + case 9 : itype = FR30BF_INSN_DMOV2R13H; goto extract_fmt_dmov2r13h; + case 10 : itype = FR30BF_INSN_DMOV2R13B; goto extract_fmt_dmov2r13b; + case 11 : itype = FR30BF_INSN_DMOV2R15PD; goto extract_fmt_dmov2r15pd; + case 12 : itype = FR30BF_INSN_DMOV2R13PI; goto extract_fmt_dmov2r13pi; + case 13 : itype = FR30BF_INSN_DMOV2R13PIH; goto extract_fmt_dmov2r13pih; + case 14 : itype = FR30BF_INSN_DMOV2R13PIB; goto extract_fmt_dmov2r13pib; + case 15 : itype = FR30BF_INSN_ENTER; goto extract_fmt_enter; + case 16 : itype = FR30BF_INSN_STR13; goto extract_fmt_str13; + case 17 : itype = FR30BF_INSN_STR13H; goto extract_fmt_str13h; + case 18 : itype = FR30BF_INSN_STR13B; goto extract_fmt_str13b; + case 19 : itype = FR30BF_INSN_STR15; goto extract_fmt_str15; + case 20 : itype = FR30BF_INSN_ST; goto extract_fmt_st; + case 21 : itype = FR30BF_INSN_STH; goto extract_fmt_sth; + case 22 : itype = FR30BF_INSN_STB; goto extract_fmt_stb; + case 23 : + { + unsigned int val = (((insn >> 4) & (15 << 0))); + switch (val) { - static const DECODE_DESC insns[16] = { - { I (INSN_STR15GR), E (FMT_STR15GR) }, { I (INSN_MOVPS), E (FMT_MOVPS) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_STR15DR), E (FMT_STR15DR) }, { I (INSN_STR15PS), E (FMT_STR15PS) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 4) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : itype = FR30BF_INSN_STR15GR; goto extract_fmt_str15gr; + case 1 : itype = FR30BF_INSN_MOVPS; goto extract_fmt_movps; + case 8 : itype = FR30BF_INSN_STR15DR; goto extract_fmt_str15dr; + case 9 : itype = FR30BF_INSN_STR15PS; goto extract_fmt_str15ps; + default : itype = FR30BF_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 151) : + } + case 24 : itype = FR30BF_INSN_DMOVR13; goto extract_fmt_dmovr13; + case 25 : itype = FR30BF_INSN_DMOVR13H; goto extract_fmt_dmovr13h; + case 26 : itype = FR30BF_INSN_DMOVR13B; goto extract_fmt_dmovr13b; + case 27 : itype = FR30BF_INSN_DMOVR15PI; goto extract_fmt_dmovr15pi; + case 28 : itype = FR30BF_INSN_DMOVR13PI; goto extract_fmt_dmovr13pi; + case 29 : itype = FR30BF_INSN_DMOVR13PIH; goto extract_fmt_dmovr13pih; + case 30 : itype = FR30BF_INSN_DMOVR13PIB; goto extract_fmt_dmovr13pib; + case 31 : itype = FR30BF_INSN_INT; goto extract_fmt_int; + case 32 : /* fall through */ + case 33 : /* fall through */ + case 34 : /* fall through */ + case 35 : /* fall through */ + case 36 : /* fall through */ + case 37 : /* fall through */ + case 38 : /* fall through */ + case 39 : /* fall through */ + case 40 : /* fall through */ + case 41 : /* fall through */ + case 42 : /* fall through */ + case 43 : /* fall through */ + case 44 : /* fall through */ + case 45 : /* fall through */ + case 46 : /* fall through */ + case 47 : itype = FR30BF_INSN_LDR14; goto extract_fmt_ldr14; + case 48 : /* fall through */ + case 49 : /* fall through */ + case 50 : /* fall through */ + case 51 : /* fall through */ + case 52 : /* fall through */ + case 53 : /* fall through */ + case 54 : /* fall through */ + case 55 : /* fall through */ + case 56 : /* fall through */ + case 57 : /* fall through */ + case 58 : /* fall through */ + case 59 : /* fall through */ + case 60 : /* fall through */ + case 61 : /* fall through */ + case 62 : /* fall through */ + case 63 : itype = FR30BF_INSN_STR14; goto extract_fmt_str14; + case 64 : /* fall through */ + case 65 : /* fall through */ + case 66 : /* fall through */ + case 67 : /* fall through */ + case 68 : /* fall through */ + case 69 : /* fall through */ + case 70 : /* fall through */ + case 71 : /* fall through */ + case 72 : /* fall through */ + case 73 : /* fall through */ + case 74 : /* fall through */ + case 75 : /* fall through */ + case 76 : /* fall through */ + case 77 : /* fall through */ + case 78 : /* fall through */ + case 79 : itype = FR30BF_INSN_LDR14UH; goto extract_fmt_ldr14uh; + case 80 : /* fall through */ + case 81 : /* fall through */ + case 82 : /* fall through */ + case 83 : /* fall through */ + case 84 : /* fall through */ + case 85 : /* fall through */ + case 86 : /* fall through */ + case 87 : /* fall through */ + case 88 : /* fall through */ + case 89 : /* fall through */ + case 90 : /* fall through */ + case 91 : /* fall through */ + case 92 : /* fall through */ + case 93 : /* fall through */ + case 94 : /* fall through */ + case 95 : itype = FR30BF_INSN_STR14H; goto extract_fmt_str14h; + case 96 : /* fall through */ + case 97 : /* fall through */ + case 98 : /* fall through */ + case 99 : /* fall through */ + case 100 : /* fall through */ + case 101 : /* fall through */ + case 102 : /* fall through */ + case 103 : /* fall through */ + case 104 : /* fall through */ + case 105 : /* fall through */ + case 106 : /* fall through */ + case 107 : /* fall through */ + case 108 : /* fall through */ + case 109 : /* fall through */ + case 110 : /* fall through */ + case 111 : itype = FR30BF_INSN_LDR14UB; goto extract_fmt_ldr14ub; + case 112 : /* fall through */ + case 113 : /* fall through */ + case 114 : /* fall through */ + case 115 : /* fall through */ + case 116 : /* fall through */ + case 117 : /* fall through */ + case 118 : /* fall through */ + case 119 : /* fall through */ + case 120 : /* fall through */ + case 121 : /* fall through */ + case 122 : /* fall through */ + case 123 : /* fall through */ + case 124 : /* fall through */ + case 125 : /* fall through */ + case 126 : /* fall through */ + case 127 : itype = FR30BF_INSN_STR14B; goto extract_fmt_str14b; + case 128 : itype = FR30BF_INSN_BANDL; goto extract_fmt_bandl; + case 129 : itype = FR30BF_INSN_BANDH; goto extract_fmt_bandl; + case 130 : itype = FR30BF_INSN_AND; goto extract_fmt_and; + case 131 : itype = FR30BF_INSN_ANDCCR; goto extract_fmt_andccr; + case 132 : itype = FR30BF_INSN_ANDM; goto extract_fmt_andm; + case 133 : itype = FR30BF_INSN_ANDH; goto extract_fmt_andh; + case 134 : itype = FR30BF_INSN_ANDB; goto extract_fmt_andb; + case 135 : itype = FR30BF_INSN_STILM; goto extract_fmt_stilm; + case 136 : itype = FR30BF_INSN_BTSTL; goto extract_fmt_btstl; + case 137 : itype = FR30BF_INSN_BTSTH; goto extract_fmt_btstl; + case 138 : itype = FR30BF_INSN_XCHB; goto extract_fmt_xchb; + case 139 : itype = FR30BF_INSN_MOV; goto extract_fmt_mov; + case 140 : itype = FR30BF_INSN_LDM0; goto extract_fmt_ldm0; + case 141 : itype = FR30BF_INSN_LDM1; goto extract_fmt_ldm1; + case 142 : itype = FR30BF_INSN_STM0; goto extract_fmt_stm0; + case 143 : itype = FR30BF_INSN_STM1; goto extract_fmt_stm1; + case 144 : itype = FR30BF_INSN_BORL; goto extract_fmt_bandl; + case 145 : itype = FR30BF_INSN_BORH; goto extract_fmt_bandl; + case 146 : itype = FR30BF_INSN_OR; goto extract_fmt_and; + case 147 : itype = FR30BF_INSN_ORCCR; goto extract_fmt_andccr; + case 148 : itype = FR30BF_INSN_ORM; goto extract_fmt_andm; + case 149 : itype = FR30BF_INSN_ORH; goto extract_fmt_andh; + case 150 : itype = FR30BF_INSN_ORB; goto extract_fmt_andb; + case 151 : + { + unsigned int val = (((insn >> 4) & (15 << 0))); + switch (val) { - static const DECODE_DESC insns[16] = { - { I (INSN_JMP), E (FMT_JMP) }, { I (INSN_CALLR), E (FMT_CALLR) }, - { I (INSN_RET), E (FMT_RET) }, { I (INSN_RETI), E (FMT_RETI) }, - { I (INSN_DIV0S), E (FMT_DIV0S) }, { I (INSN_DIV0U), E (FMT_DIV0U) }, - { I (INSN_DIV1), E (FMT_DIV1) }, { I (INSN_DIV2), E (FMT_DIV2) }, - { I (INSN_EXTSB), E (FMT_EXTSB) }, { I (INSN_EXTUB), E (FMT_EXTUB) }, - { I (INSN_EXTSH), E (FMT_EXTSH) }, { I (INSN_EXTUH), E (FMT_EXTUH) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - }; - unsigned int val = (((insn >> 4) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : itype = FR30BF_INSN_JMP; goto extract_fmt_jmp; + case 1 : itype = FR30BF_INSN_CALLR; goto extract_fmt_callr; + case 2 : itype = FR30BF_INSN_RET; goto extract_fmt_ret; + case 3 : itype = FR30BF_INSN_RETI; goto extract_fmt_reti; + case 4 : itype = FR30BF_INSN_DIV0S; goto extract_fmt_div0s; + case 5 : itype = FR30BF_INSN_DIV0U; goto extract_fmt_div0u; + case 6 : itype = FR30BF_INSN_DIV1; goto extract_fmt_div1; + case 7 : itype = FR30BF_INSN_DIV2; goto extract_fmt_div2; + case 8 : itype = FR30BF_INSN_EXTSB; goto extract_fmt_extsb; + case 9 : itype = FR30BF_INSN_EXTUB; goto extract_fmt_extub; + case 10 : itype = FR30BF_INSN_EXTSH; goto extract_fmt_extsh; + case 11 : itype = FR30BF_INSN_EXTUH; goto extract_fmt_extuh; + default : itype = FR30BF_INSN_X_INVALID; goto extract_fmt_empty; } - CASE (0, 159) : + } + case 152 : itype = FR30BF_INSN_BEORL; goto extract_fmt_bandl; + case 153 : itype = FR30BF_INSN_BEORH; goto extract_fmt_bandl; + case 154 : itype = FR30BF_INSN_EOR; goto extract_fmt_and; + case 155 : itype = FR30BF_INSN_LDI20; goto extract_fmt_ldi20; + case 156 : itype = FR30BF_INSN_EORM; goto extract_fmt_andm; + case 157 : itype = FR30BF_INSN_EORH; goto extract_fmt_andh; + case 158 : itype = FR30BF_INSN_EORB; goto extract_fmt_andb; + case 159 : + { + unsigned int val = (((insn >> 4) & (15 << 0))); + switch (val) { - static const DECODE_DESC insns[16] = { - { I (INSN_JMPD), E (FMT_JMP) }, { I (INSN_CALLRD), E (FMT_CALLR) }, - { I (INSN_RET_D), E (FMT_RET) }, { I (INSN_INTE), E (FMT_INTE) }, - { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_DIV3), E (FMT_DIV3) }, { I (INSN_DIV4S), E (FMT_DIV4S) }, - { I (INSN_LDI32), E (FMT_LDI32) }, { I (INSN_LEAVE), E (FMT_LEAVE) }, - { I (INSN_NOP), E (FMT_NOP) }, { I (INSN_X_INVALID), E (FMT_EMPTY) }, - { I (INSN_COPOP), E (FMT_COPOP) }, { I (INSN_COPLD), E (FMT_COPLD) }, - { I (INSN_COPST), E (FMT_COPST) }, { I (INSN_COPSV), E (FMT_COPST) }, - }; - unsigned int val = (((insn >> 4) & (15 << 0))); - idecode = &insns[val]; - GOTO_EXTRACT (idecode); + case 0 : itype = FR30BF_INSN_JMPD; goto extract_fmt_jmp; + case 1 : itype = FR30BF_INSN_CALLRD; goto extract_fmt_callr; + case 2 : itype = FR30BF_INSN_RET_D; goto extract_fmt_ret; + case 3 : itype = FR30BF_INSN_INTE; goto extract_fmt_inte; + case 6 : itype = FR30BF_INSN_DIV3; goto extract_fmt_div3; + case 7 : itype = FR30BF_INSN_DIV4S; goto extract_fmt_div4s; + case 8 : itype = FR30BF_INSN_LDI32; goto extract_fmt_ldi32; + case 9 : itype = FR30BF_INSN_LEAVE; goto extract_fmt_leave; + case 10 : itype = FR30BF_INSN_NOP; goto extract_fmt_nop; + case 12 : itype = FR30BF_INSN_COPOP; goto extract_fmt_copop; + case 13 : itype = FR30BF_INSN_COPLD; goto extract_fmt_copld; + case 14 : itype = FR30BF_INSN_COPST; goto extract_fmt_copst; + case 15 : itype = FR30BF_INSN_COPSV; goto extract_fmt_copst; + default : itype = FR30BF_INSN_X_INVALID; goto extract_fmt_empty; } - DEFAULT (0) : - idecode = &insns[val]; - GOTO_EXTRACT (idecode); } - ENDSWITCH (0) + case 160 : itype = FR30BF_INSN_ADDNI; goto extract_fmt_addni; + case 161 : itype = FR30BF_INSN_ADDN2; goto extract_fmt_addn2; + case 162 : itype = FR30BF_INSN_ADDN; goto extract_fmt_addn; + case 163 : itype = FR30BF_INSN_ADDSP; goto extract_fmt_addsp; + case 164 : itype = FR30BF_INSN_ADDI; goto extract_fmt_addi; + case 165 : itype = FR30BF_INSN_ADD2; goto extract_fmt_add2; + case 166 : itype = FR30BF_INSN_ADD; goto extract_fmt_add; + case 167 : itype = FR30BF_INSN_ADDC; goto extract_fmt_addc; + case 168 : itype = FR30BF_INSN_CMPI; goto extract_fmt_cmpi; + case 169 : itype = FR30BF_INSN_CMP2; goto extract_fmt_cmp2; + case 170 : itype = FR30BF_INSN_CMP; goto extract_fmt_cmp; + case 171 : itype = FR30BF_INSN_MULU; goto extract_fmt_mulu; + case 172 : itype = FR30BF_INSN_SUB; goto extract_fmt_add; + case 173 : itype = FR30BF_INSN_SUBC; goto extract_fmt_addc; + case 174 : itype = FR30BF_INSN_SUBN; goto extract_fmt_addn; + case 175 : itype = FR30BF_INSN_MUL; goto extract_fmt_mul; + case 176 : itype = FR30BF_INSN_LSRI; goto extract_fmt_lsli; + case 177 : itype = FR30BF_INSN_LSR2; goto extract_fmt_lsli; + case 178 : itype = FR30BF_INSN_LSR; goto extract_fmt_lsl; + case 179 : itype = FR30BF_INSN_MOV2DR; goto extract_fmt_mov2dr; + case 180 : itype = FR30BF_INSN_LSLI; goto extract_fmt_lsli; + case 181 : itype = FR30BF_INSN_LSL2; goto extract_fmt_lsli; + case 182 : itype = FR30BF_INSN_LSL; goto extract_fmt_lsl; + case 183 : itype = FR30BF_INSN_MOVDR; goto extract_fmt_movdr; + case 184 : itype = FR30BF_INSN_ASRI; goto extract_fmt_lsli; + case 185 : itype = FR30BF_INSN_ASR2; goto extract_fmt_lsli; + case 186 : itype = FR30BF_INSN_ASR; goto extract_fmt_lsl; + case 187 : itype = FR30BF_INSN_MULUH; goto extract_fmt_mulh; + case 188 : itype = FR30BF_INSN_LDRES; goto extract_fmt_ldres; + case 189 : itype = FR30BF_INSN_STRES; goto extract_fmt_ldres; + case 191 : itype = FR30BF_INSN_MULH; goto extract_fmt_mulh; + case 192 : /* fall through */ + case 193 : /* fall through */ + case 194 : /* fall through */ + case 195 : /* fall through */ + case 196 : /* fall through */ + case 197 : /* fall through */ + case 198 : /* fall through */ + case 199 : /* fall through */ + case 200 : /* fall through */ + case 201 : /* fall through */ + case 202 : /* fall through */ + case 203 : /* fall through */ + case 204 : /* fall through */ + case 205 : /* fall through */ + case 206 : /* fall through */ + case 207 : itype = FR30BF_INSN_LDI8; goto extract_fmt_ldi8; + case 208 : /* fall through */ + case 209 : /* fall through */ + case 210 : /* fall through */ + case 211 : /* fall through */ + case 212 : /* fall through */ + case 213 : /* fall through */ + case 214 : /* fall through */ + case 215 : itype = FR30BF_INSN_CALL; goto extract_fmt_call; + case 216 : /* fall through */ + case 217 : /* fall through */ + case 218 : /* fall through */ + case 219 : /* fall through */ + case 220 : /* fall through */ + case 221 : /* fall through */ + case 222 : /* fall through */ + case 223 : itype = FR30BF_INSN_CALLD; goto extract_fmt_call; + case 224 : itype = FR30BF_INSN_BRA; goto extract_fmt_brad; + case 225 : itype = FR30BF_INSN_BNO; goto extract_fmt_bnod; + case 226 : itype = FR30BF_INSN_BEQ; goto extract_fmt_beqd; + case 227 : itype = FR30BF_INSN_BNE; goto extract_fmt_beqd; + case 228 : itype = FR30BF_INSN_BC; goto extract_fmt_bcd; + case 229 : itype = FR30BF_INSN_BNC; goto extract_fmt_bcd; + case 230 : itype = FR30BF_INSN_BN; goto extract_fmt_bnd; + case 231 : itype = FR30BF_INSN_BP; goto extract_fmt_bnd; + case 232 : itype = FR30BF_INSN_BV; goto extract_fmt_bvd; + case 233 : itype = FR30BF_INSN_BNV; goto extract_fmt_bvd; + case 234 : itype = FR30BF_INSN_BLT; goto extract_fmt_bltd; + case 235 : itype = FR30BF_INSN_BGE; goto extract_fmt_bltd; + case 236 : itype = FR30BF_INSN_BLE; goto extract_fmt_bled; + case 237 : itype = FR30BF_INSN_BGT; goto extract_fmt_bled; + case 238 : itype = FR30BF_INSN_BLS; goto extract_fmt_blsd; + case 239 : itype = FR30BF_INSN_BHI; goto extract_fmt_blsd; + case 240 : itype = FR30BF_INSN_BRAD; goto extract_fmt_brad; + case 241 : itype = FR30BF_INSN_BNOD; goto extract_fmt_bnod; + case 242 : itype = FR30BF_INSN_BEQD; goto extract_fmt_beqd; + case 243 : itype = FR30BF_INSN_BNED; goto extract_fmt_beqd; + case 244 : itype = FR30BF_INSN_BCD; goto extract_fmt_bcd; + case 245 : itype = FR30BF_INSN_BNCD; goto extract_fmt_bcd; + case 246 : itype = FR30BF_INSN_BND; goto extract_fmt_bnd; + case 247 : itype = FR30BF_INSN_BPD; goto extract_fmt_bnd; + case 248 : itype = FR30BF_INSN_BVD; goto extract_fmt_bvd; + case 249 : itype = FR30BF_INSN_BNVD; goto extract_fmt_bvd; + case 250 : itype = FR30BF_INSN_BLTD; goto extract_fmt_bltd; + case 251 : itype = FR30BF_INSN_BGED; goto extract_fmt_bltd; + case 252 : itype = FR30BF_INSN_BLED; goto extract_fmt_bled; + case 253 : itype = FR30BF_INSN_BGTD; goto extract_fmt_bled; + case 254 : itype = FR30BF_INSN_BLSD; goto extract_fmt_blsd; + case 255 : itype = FR30BF_INSN_BHID; goto extract_fmt_blsd; + default : itype = FR30BF_INSN_X_INVALID; goto extract_fmt_empty; + } } -#undef I -#undef E } /* The instruction has been decoded, now extract the fields. */ - extract: - { -#ifndef __GNUC__ - switch (idecode->sfmt) -#endif - { - - CASE (ex, FMT_EMPTY) : + extract_fmt_empty: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_empty.f EXTRACT_IFMT_EMPTY_VARS /* */ @@ -680,11 +658,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_empty", (char *) 0)); #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ADD) : + extract_fmt_add: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_add.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -706,11 +685,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ADDI) : + extract_fmt_addi: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_addi.f EXTRACT_IFMT_ADDI_VARS /* f-op1 f-op2 f-u4 f-Ri */ @@ -731,11 +711,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ADD2) : + extract_fmt_add2: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_add2.f EXTRACT_IFMT_ADD2_VARS /* f-op1 f-op2 f-m4 f-Ri */ @@ -756,11 +737,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ADDC) : + extract_fmt_addc: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_addc.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -782,11 +764,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ADDN) : + extract_fmt_addn: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_addn.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -808,11 +791,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ADDNI) : + extract_fmt_addni: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_addni.f EXTRACT_IFMT_ADDI_VARS /* f-op1 f-op2 f-u4 f-Ri */ @@ -833,11 +817,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ADDN2) : + extract_fmt_addn2: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_addn2.f EXTRACT_IFMT_ADD2_VARS /* f-op1 f-op2 f-m4 f-Ri */ @@ -858,11 +843,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_CMP) : + extract_fmt_cmp: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_cmp.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -883,11 +869,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_CMPI) : + extract_fmt_cmpi: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_cmpi.f EXTRACT_IFMT_ADDI_VARS /* f-op1 f-op2 f-u4 f-Ri */ @@ -907,11 +894,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_CMP2) : + extract_fmt_cmp2: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_cmp2.f EXTRACT_IFMT_ADD2_VARS /* f-op1 f-op2 f-m4 f-Ri */ @@ -931,11 +919,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_AND) : + extract_fmt_and: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_and.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -957,11 +946,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ANDM) : + extract_fmt_andm: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_andm.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -982,11 +972,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ANDH) : + extract_fmt_andh: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_andh.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -1007,11 +998,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ANDB) : + extract_fmt_andb: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_andb.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -1032,11 +1024,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_BANDL) : + extract_fmt_bandl: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_bandl.f EXTRACT_IFMT_ADDI_VARS /* f-op1 f-op2 f-u4 f-Ri */ @@ -1056,11 +1049,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_BTSTL) : + extract_fmt_btstl: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_btstl.f EXTRACT_IFMT_ADDI_VARS /* f-op1 f-op2 f-u4 f-Ri */ @@ -1080,11 +1074,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_MUL) : + extract_fmt_mul: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_mul.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -1105,11 +1100,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_MULU) : + extract_fmt_mulu: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_mulu.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -1130,11 +1126,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_MULH) : + extract_fmt_mulh: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_mulh.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -1155,11 +1152,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_DIV0S) : + extract_fmt_div0s: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_div0s.f EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */ @@ -1178,11 +1176,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_DIV0U) : + extract_fmt_div0u: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_div0u.f EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */ @@ -1193,11 +1192,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_div0u", (char *) 0)); #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_DIV1) : + extract_fmt_div1: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_div1.f EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */ @@ -1216,11 +1216,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_DIV2) : + extract_fmt_div2: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_div2.f EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */ @@ -1239,11 +1240,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_DIV3) : + extract_fmt_div3: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_div3.f EXTRACT_IFMT_DIV3_VARS /* f-op1 f-op2 f-op3 f-op4 */ @@ -1254,11 +1256,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_div3", (char *) 0)); #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_DIV4S) : + extract_fmt_div4s: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_div4s.f EXTRACT_IFMT_DIV3_VARS /* f-op1 f-op2 f-op3 f-op4 */ @@ -1269,11 +1272,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_div4s", (char *) 0)); #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LSL) : + extract_fmt_lsl: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_lsl.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -1295,11 +1299,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LSLI) : + extract_fmt_lsli: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_lsli.f EXTRACT_IFMT_ADDI_VARS /* f-op1 f-op2 f-u4 f-Ri */ @@ -1320,11 +1325,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDI8) : + extract_fmt_ldi8: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldi8.f EXTRACT_IFMT_LDI8_VARS /* f-op1 f-i8 f-Ri */ @@ -1344,11 +1350,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDI20) : + extract_fmt_ldi20: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldi20.f EXTRACT_IFMT_LDI20_VARS /* f-op1 f-i20 f-op2 f-Ri */ @@ -1368,11 +1375,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDI32) : + extract_fmt_ldi32: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldi32.f EXTRACT_IFMT_LDI32_VARS /* f-op1 f-i32 f-op2 f-op3 f-Ri */ @@ -1392,11 +1400,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LD) : + extract_fmt_ld: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ld.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -1417,11 +1426,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDUH) : + extract_fmt_lduh: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_lduh.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -1442,11 +1452,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDUB) : + extract_fmt_ldub: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldub.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -1467,11 +1478,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDR13) : + extract_fmt_ldr13: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldr13.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -1493,11 +1505,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDR13UH) : + extract_fmt_ldr13uh: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldr13uh.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -1519,11 +1532,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDR13UB) : + extract_fmt_ldr13ub: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldr13ub.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -1545,11 +1559,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDR14) : + extract_fmt_ldr14: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldr14.f EXTRACT_IFMT_LDR14_VARS /* f-op1 f-disp10 f-Ri */ @@ -1570,11 +1585,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDR14UH) : + extract_fmt_ldr14uh: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldr14uh.f EXTRACT_IFMT_LDR14UH_VARS /* f-op1 f-disp9 f-Ri */ @@ -1595,11 +1611,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDR14UB) : + extract_fmt_ldr14ub: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldr14ub.f EXTRACT_IFMT_LDR14UB_VARS /* f-op1 f-disp8 f-Ri */ @@ -1620,11 +1637,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDR15) : + extract_fmt_ldr15: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldr15.f EXTRACT_IFMT_LDR15_VARS /* f-op1 f-op2 f-udisp6 f-Ri */ @@ -1645,11 +1663,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDR15GR) : + extract_fmt_ldr15gr: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldr15gr.f EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */ @@ -1671,11 +1690,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDR15DR) : + extract_fmt_ldr15dr: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldr15dr.f EXTRACT_IFMT_LDR15DR_VARS /* f-op1 f-op2 f-op3 f-Rs2 */ @@ -1695,11 +1715,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDR15PS) : + extract_fmt_ldr15ps: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldr15ps.f EXTRACT_IFMT_DIV3_VARS /* f-op1 f-op2 f-op3 f-op4 */ @@ -1718,11 +1739,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ST) : + extract_fmt_st: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_st.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -1743,11 +1765,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STH) : + extract_fmt_sth: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_sth.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -1768,11 +1791,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STB) : + extract_fmt_stb: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stb.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -1793,11 +1817,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STR13) : + extract_fmt_str13: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_str13.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -1819,11 +1844,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STR13H) : + extract_fmt_str13h: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_str13h.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -1845,11 +1871,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STR13B) : + extract_fmt_str13b: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_str13b.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -1871,11 +1898,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STR14) : + extract_fmt_str14: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_str14.f EXTRACT_IFMT_LDR14_VARS /* f-op1 f-disp10 f-Ri */ @@ -1896,11 +1924,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STR14H) : + extract_fmt_str14h: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_str14h.f EXTRACT_IFMT_LDR14UH_VARS /* f-op1 f-disp9 f-Ri */ @@ -1921,11 +1950,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STR14B) : + extract_fmt_str14b: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_str14b.f EXTRACT_IFMT_LDR14UB_VARS /* f-op1 f-disp8 f-Ri */ @@ -1946,11 +1976,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STR15) : + extract_fmt_str15: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_str15.f EXTRACT_IFMT_LDR15_VARS /* f-op1 f-op2 f-udisp6 f-Ri */ @@ -1971,11 +2002,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STR15GR) : + extract_fmt_str15gr: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_str15gr.f EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */ @@ -1996,11 +2028,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STR15DR) : + extract_fmt_str15dr: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_str15dr.f EXTRACT_IFMT_LDR15DR_VARS /* f-op1 f-op2 f-op3 f-Rs2 */ @@ -2020,11 +2053,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STR15PS) : + extract_fmt_str15ps: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_str15ps.f EXTRACT_IFMT_DIV3_VARS /* f-op1 f-op2 f-op3 f-op4 */ @@ -2043,11 +2077,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_MOV) : + extract_fmt_mov: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_mov.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -2068,11 +2103,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_MOVDR) : + extract_fmt_movdr: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_movdr.f EXTRACT_IFMT_MOVDR_VARS /* f-op1 f-op2 f-Rs1 f-Ri */ @@ -2092,11 +2128,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_MOVPS) : + extract_fmt_movps: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_movps.f EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */ @@ -2115,11 +2152,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_MOV2DR) : + extract_fmt_mov2dr: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_mov2dr.f EXTRACT_IFMT_MOVDR_VARS /* f-op1 f-op2 f-Rs1 f-Ri */ @@ -2139,11 +2177,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_MOV2PS) : + extract_fmt_mov2ps: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_mov2ps.f EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */ @@ -2162,11 +2201,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_JMP) : + extract_fmt_jmp: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_jmp.f EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */ @@ -2186,11 +2226,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_CALLR) : + extract_fmt_callr: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_callr.f EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */ @@ -2210,11 +2251,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_CALL) : + extract_fmt_call: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_call.f EXTRACT_IFMT_CALL_VARS /* f-op1 f-op5 f-rel12 */ @@ -2233,11 +2275,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_RET) : + extract_fmt_ret: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_ret.f EXTRACT_IFMT_DIV3_VARS /* f-op1 f-op2 f-op3 f-op4 */ @@ -2255,11 +2298,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_INT) : + extract_fmt_int: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_int.f EXTRACT_IFMT_INT_VARS /* f-op1 f-op2 f-u8 */ @@ -2278,11 +2322,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_INTE) : + extract_fmt_inte: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_inte.f EXTRACT_IFMT_DIV3_VARS /* f-op1 f-op2 f-op3 f-op4 */ @@ -2300,11 +2345,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_RETI) : + extract_fmt_reti: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_reti.f EXTRACT_IFMT_DIV3_VARS /* f-op1 f-op2 f-op3 f-op4 */ @@ -2322,11 +2368,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_BRAD) : + extract_fmt_brad: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_brad.f EXTRACT_IFMT_BRAD_VARS /* f-op1 f-cc f-rel9 */ @@ -2345,11 +2392,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_BNOD) : + extract_fmt_bnod: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_bnod.f EXTRACT_IFMT_BRAD_VARS /* f-op1 f-cc f-rel9 */ @@ -2360,11 +2408,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bnod", (char *) 0)); #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_BEQD) : + extract_fmt_beqd: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_beqd.f EXTRACT_IFMT_BRAD_VARS /* f-op1 f-cc f-rel9 */ @@ -2383,11 +2432,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_BCD) : + extract_fmt_bcd: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_bcd.f EXTRACT_IFMT_BRAD_VARS /* f-op1 f-cc f-rel9 */ @@ -2406,11 +2456,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_BND) : + extract_fmt_bnd: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_bnd.f EXTRACT_IFMT_BRAD_VARS /* f-op1 f-cc f-rel9 */ @@ -2429,11 +2480,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_BVD) : + extract_fmt_bvd: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_bvd.f EXTRACT_IFMT_BRAD_VARS /* f-op1 f-cc f-rel9 */ @@ -2452,11 +2504,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_BLTD) : + extract_fmt_bltd: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_bltd.f EXTRACT_IFMT_BRAD_VARS /* f-op1 f-cc f-rel9 */ @@ -2475,11 +2528,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_BLED) : + extract_fmt_bled: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_bled.f EXTRACT_IFMT_BRAD_VARS /* f-op1 f-cc f-rel9 */ @@ -2498,11 +2552,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_BLSD) : + extract_fmt_blsd: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.cti.fields.fmt_blsd.f EXTRACT_IFMT_BRAD_VARS /* f-op1 f-cc f-rel9 */ @@ -2521,11 +2576,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_DMOVR13) : + extract_fmt_dmovr13: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_dmovr13.f EXTRACT_IFMT_DMOVR13_VARS /* f-op1 f-op2 f-dir10 */ @@ -2544,11 +2600,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_DMOVR13H) : + extract_fmt_dmovr13h: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_dmovr13h.f EXTRACT_IFMT_DMOVR13H_VARS /* f-op1 f-op2 f-dir9 */ @@ -2567,11 +2624,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_DMOVR13B) : + extract_fmt_dmovr13b: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_dmovr13b.f EXTRACT_IFMT_DMOVR13B_VARS /* f-op1 f-op2 f-dir8 */ @@ -2590,11 +2648,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_DMOVR13PI) : + extract_fmt_dmovr13pi: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_dmovr13pi.f EXTRACT_IFMT_DMOVR13_VARS /* f-op1 f-op2 f-dir10 */ @@ -2614,11 +2673,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_DMOVR13PIH) : + extract_fmt_dmovr13pih: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_dmovr13pih.f EXTRACT_IFMT_DMOVR13H_VARS /* f-op1 f-op2 f-dir9 */ @@ -2638,11 +2698,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_DMOVR13PIB) : + extract_fmt_dmovr13pib: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_dmovr13pib.f EXTRACT_IFMT_DMOVR13B_VARS /* f-op1 f-op2 f-dir8 */ @@ -2662,11 +2723,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_DMOVR15PI) : + extract_fmt_dmovr15pi: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_dmovr15pi.f EXTRACT_IFMT_DMOVR13_VARS /* f-op1 f-op2 f-dir10 */ @@ -2686,11 +2748,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_DMOV2R13) : + extract_fmt_dmov2r13: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_dmov2r13.f EXTRACT_IFMT_DMOVR13_VARS /* f-op1 f-op2 f-dir10 */ @@ -2709,11 +2772,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_DMOV2R13H) : + extract_fmt_dmov2r13h: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_dmov2r13h.f EXTRACT_IFMT_DMOVR13H_VARS /* f-op1 f-op2 f-dir9 */ @@ -2732,11 +2796,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_DMOV2R13B) : + extract_fmt_dmov2r13b: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_dmov2r13b.f EXTRACT_IFMT_DMOVR13B_VARS /* f-op1 f-op2 f-dir8 */ @@ -2755,11 +2820,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_DMOV2R13PI) : + extract_fmt_dmov2r13pi: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_dmov2r13pi.f EXTRACT_IFMT_DMOVR13_VARS /* f-op1 f-op2 f-dir10 */ @@ -2779,11 +2845,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_DMOV2R13PIH) : + extract_fmt_dmov2r13pih: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_dmov2r13pih.f EXTRACT_IFMT_DMOVR13H_VARS /* f-op1 f-op2 f-dir9 */ @@ -2803,11 +2870,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_DMOV2R13PIB) : + extract_fmt_dmov2r13pib: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_dmov2r13pib.f EXTRACT_IFMT_DMOVR13B_VARS /* f-op1 f-op2 f-dir8 */ @@ -2827,11 +2895,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_DMOV2R15PD) : + extract_fmt_dmov2r15pd: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_dmov2r15pd.f EXTRACT_IFMT_DMOVR13_VARS /* f-op1 f-op2 f-dir10 */ @@ -2851,11 +2920,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDRES) : + extract_fmt_ldres: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldres.f EXTRACT_IFMT_ADDI_VARS /* f-op1 f-op2 f-u4 f-Ri */ @@ -2875,11 +2945,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_COPOP) : + extract_fmt_copop: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_copop.f EXTRACT_IFMT_COPOP_VARS /* f-op1 f-ccc f-op2 f-op3 f-CRj f-u4c f-CRi */ @@ -2890,11 +2961,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_copop", (char *) 0)); #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_COPLD) : + extract_fmt_copld: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_copld.f EXTRACT_IFMT_COPLD_VARS /* f-op1 f-ccc f-op2 f-op3 f-Rjc f-u4c f-CRi */ @@ -2905,11 +2977,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_copld", (char *) 0)); #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_COPST) : + extract_fmt_copst: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_copst.f EXTRACT_IFMT_COPST_VARS /* f-op1 f-ccc f-op2 f-op3 f-CRj f-u4c f-Ric */ @@ -2920,11 +2993,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_copst", (char *) 0)); #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_NOP) : + extract_fmt_nop: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_nop.f EXTRACT_IFMT_DIV3_VARS /* f-op1 f-op2 f-op3 f-op4 */ @@ -2935,11 +3009,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_nop", (char *) 0)); #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ANDCCR) : + extract_fmt_andccr: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_andccr.f EXTRACT_IFMT_INT_VARS /* f-op1 f-op2 f-u8 */ @@ -2951,11 +3026,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_andccr", "f_u8 0x%x", 'x', f_u8, (char *) 0)); #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STILM) : + extract_fmt_stilm: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stilm.f EXTRACT_IFMT_INT_VARS /* f-op1 f-op2 f-u8 */ @@ -2967,11 +3043,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stilm", "f_u8 0x%x", 'x', f_u8, (char *) 0)); #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ADDSP) : + extract_fmt_addsp: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_addsp.f EXTRACT_IFMT_ADDSP_VARS /* f-op1 f-op2 f-s10 */ @@ -2991,11 +3068,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_EXTSB) : + extract_fmt_extsb: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_extsb.f EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */ @@ -3015,11 +3093,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_EXTUB) : + extract_fmt_extub: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_extub.f EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */ @@ -3039,11 +3118,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_EXTSH) : + extract_fmt_extsh: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_extsh.f EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */ @@ -3063,11 +3143,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_EXTUH) : + extract_fmt_extuh: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_extuh.f EXTRACT_IFMT_DIV0S_VARS /* f-op1 f-op2 f-op3 f-Ri */ @@ -3087,11 +3168,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDM0) : + extract_fmt_ldm0: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldm0.f EXTRACT_IFMT_LDM0_VARS /* f-op1 f-op2 f-reglist_low_ld */ @@ -3119,11 +3201,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LDM1) : + extract_fmt_ldm1: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_ldm1.f EXTRACT_IFMT_LDM1_VARS /* f-op1 f-op2 f-reglist_hi_ld */ @@ -3150,11 +3233,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STM0) : + extract_fmt_stm0: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stm0.f EXTRACT_IFMT_STM0_VARS /* f-op1 f-op2 f-reglist_low_st */ @@ -3182,11 +3266,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_STM1) : + extract_fmt_stm1: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_stm1.f EXTRACT_IFMT_STM1_VARS /* f-op1 f-op2 f-reglist_hi_st */ @@ -3213,11 +3298,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_ENTER) : + extract_fmt_enter: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_enter.f EXTRACT_IFMT_ENTER_VARS /* f-op1 f-op2 f-u10 */ @@ -3239,11 +3325,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_LEAVE) : + extract_fmt_leave: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_leave.f EXTRACT_IFMT_DIV3_VARS /* f-op1 f-op2 f-op3 f-op4 */ @@ -3264,11 +3351,12 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); + return idesc; } - CASE (ex, FMT_XCHB) : + extract_fmt_xchb: { + const IDESC *idesc = &fr30bf_insn_data[itype]; CGEN_INSN_INT insn = base_insn; #define FLD(f) abuf->fields.fmt_xchb.f EXTRACT_IFMT_ADD_VARS /* f-op1 f-op2 f-Rj f-Ri */ @@ -3290,14 +3378,7 @@ fr30bf_decode (SIM_CPU *current_cpu, IADDR pc, } #endif #undef FLD - BREAK (ex); - } - - - } - ENDSWITCH (ex) - + return idesc; } - return idecode->idesc; } diff --git a/sim/fr30/devices.c b/sim/fr30/devices.c index f378a52..a3d47cf 100644 --- a/sim/fr30/devices.c +++ b/sim/fr30/devices.c @@ -31,10 +31,8 @@ device fr30_devices; int device_io_read_buffer (device *me, void *source, int space, address_word addr, unsigned nr_bytes, - SIM_CPU *cpu, sim_cia cia) + SIM_DESC sd, SIM_CPU *cpu, sim_cia cia) { - SIM_DESC sd = CPU_STATE (cpu); - if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT) return nr_bytes; @@ -69,10 +67,8 @@ device_io_read_buffer (device *me, void *source, int space, int device_io_write_buffer (device *me, const void *source, int space, address_word addr, unsigned nr_bytes, - SIM_CPU *cpu, sim_cia cia) + SIM_DESC sd, SIM_CPU *cpu, sim_cia cia) { - SIM_DESC sd = CPU_STATE (cpu); - #if WITH_SCACHE if (addr == MCCR_ADDR) { @@ -96,4 +92,7 @@ device_io_write_buffer (device *me, const void *source, int space, return nr_bytes; } -void device_error () {} +void +device_error (device *me, char *message, ...) +{ +} diff --git a/sim/fr30/fr30-sim.h b/sim/fr30/fr30-sim.h index b9018ef..dbb8117 100644 --- a/sim/fr30/fr30-sim.h +++ b/sim/fr30/fr30-sim.h @@ -33,33 +33,21 @@ with this program; if not, write to the Free Software Foundation, Inc., extern BI fr30bf_h_sbit_get_handler (SIM_CPU *); extern void fr30bf_h_sbit_set_handler (SIM_CPU *, BI); -#define GET_H_SBIT() fr30bf_h_sbit_get_handler (current_cpu) -#define SET_H_SBIT(val) fr30bf_h_sbit_set_handler (current_cpu, (val)) extern UQI fr30bf_h_ccr_get_handler (SIM_CPU *); extern void fr30bf_h_ccr_set_handler (SIM_CPU *, UQI); -#define GET_H_CCR() fr30bf_h_ccr_get_handler (current_cpu) -#define SET_H_CCR(val) fr30bf_h_ccr_set_handler (current_cpu, (val)) extern UQI fr30bf_h_scr_get_handler (SIM_CPU *); extern void fr30bf_h_scr_set_handler (SIM_CPU *, UQI); -#define GET_H_SCR() fr30bf_h_scr_get_handler (current_cpu) -#define SET_H_SCR(val) fr30bf_h_scr_set_handler (current_cpu, (val)) extern UQI fr30bf_h_ilm_get_handler (SIM_CPU *); extern void fr30bf_h_ilm_set_handler (SIM_CPU *, UQI); -#define GET_H_ILM() fr30bf_h_ilm_get_handler (current_cpu) -#define SET_H_ILM(val) fr30bf_h_ilm_set_handler (current_cpu, (val)) extern USI fr30bf_h_ps_get_handler (SIM_CPU *); extern void fr30bf_h_ps_set_handler (SIM_CPU *, USI); -#define GET_H_PS() fr30bf_h_ps_get_handler (current_cpu) -#define SET_H_PS(val) fr30bf_h_ps_set_handler (current_cpu, (val)) extern SI fr30bf_h_dr_get_handler (SIM_CPU *, UINT); extern void fr30bf_h_dr_set_handler (SIM_CPU *, UINT, SI); -#define GET_H_DR(regno) fr30bf_h_dr_get_handler (current_cpu, (regno)) -#define SET_H_DR(regno, val) fr30bf_h_dr_set_handler (current_cpu, (regno), (val)) #define GETTWI GETTSI #define SETTWI SETTSI diff --git a/sim/fr30/fr30.c b/sim/fr30/fr30.c index 78b9b7ce..5133654 100644 --- a/sim/fr30/fr30.c +++ b/sim/fr30/fr30.c @@ -48,15 +48,15 @@ int fr30bf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len) { if (rn < 16) - SETTWI (buf, a_fr30_h_gr_get (current_cpu, rn)); + SETTWI (buf, fr30bf_h_gr_get (current_cpu, rn)); else switch (rn) { case PC_REGNUM : - SETTWI (buf, a_fr30_h_pc_get (current_cpu)); + SETTWI (buf, fr30bf_h_pc_get (current_cpu)); break; case PS_REGNUM : - SETTWI (buf, a_fr30_h_ps_get (current_cpu)); + SETTWI (buf, fr30bf_h_ps_get (current_cpu)); break; case TBR_REGNUM : case RP_REGNUM : @@ -64,7 +64,7 @@ fr30bf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len case USP_REGNUM : case MDH_REGNUM : case MDL_REGNUM : - SETTWI (buf, a_fr30_h_dr_get (current_cpu, + SETTWI (buf, fr30bf_h_dr_get (current_cpu, decode_gdb_dr_regnum (rn))); break; default : @@ -80,15 +80,15 @@ int fr30bf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len) { if (rn < 16) - a_fr30_h_gr_set (current_cpu, rn, GETTWI (buf)); + fr30bf_h_gr_set (current_cpu, rn, GETTWI (buf)); else switch (rn) { case PC_REGNUM : - a_fr30_h_pc_set (current_cpu, GETTWI (buf)); + fr30bf_h_pc_set (current_cpu, GETTWI (buf)); break; case PS_REGNUM : - a_fr30_h_ps_set (current_cpu, GETTWI (buf)); + fr30bf_h_ps_set (current_cpu, GETTWI (buf)); break; case TBR_REGNUM : case RP_REGNUM : @@ -96,7 +96,7 @@ fr30bf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len case USP_REGNUM : case MDH_REGNUM : case MDL_REGNUM : - a_fr30_h_dr_set (current_cpu, + fr30bf_h_dr_set (current_cpu, decode_gdb_dr_regnum (rn), GETTWI (buf)); break; diff --git a/sim/fr30/model.c b/sim/fr30/model.c index 7be6305..a4d0714 100644 --- a/sim/fr30/model.c +++ b/sim/fr30/model.c @@ -3996,7 +3996,7 @@ fr30_init_cpu (SIM_CPU *cpu) const MACH fr30_mach = { - "fr30", "fr30", + "fr30", "fr30", MACH_FR30, 32, 32, & fr30_models[0], & fr30bf_imp_properties, fr30_init_cpu, fr30bf_prepare_run diff --git a/sim/fr30/sem-switch.c b/sim/fr30/sem-switch.c index 86950b2..ace4bca 100644 --- a/sim/fr30/sem-switch.c +++ b/sim/fr30/sem-switch.c @@ -403,7 +403,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { BI opval = ADDOFSI (* FLD (i_Ri), * FLD (i_Rj), 0); CPU (h_vbit) = opval; @@ -419,7 +419,7 @@ do { * FLD (i_Ri) = opval; TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -do { +{ { BI opval = EQSI (* FLD (i_Ri), 0); CPU (h_zbit) = opval; @@ -430,8 +430,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} #undef FLD } @@ -446,7 +446,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { BI opval = ADDOFSI (* FLD (i_Ri), FLD (f_u4), 0); CPU (h_vbit) = opval; @@ -462,7 +462,7 @@ do { * FLD (i_Ri) = opval; TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -do { +{ { BI opval = EQSI (* FLD (i_Ri), 0); CPU (h_zbit) = opval; @@ -473,8 +473,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} #undef FLD } @@ -489,7 +489,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { BI opval = ADDOFSI (* FLD (i_Ri), FLD (f_m4), 0); CPU (h_vbit) = opval; @@ -505,7 +505,7 @@ do { * FLD (i_Ri) = opval; TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -do { +{ { BI opval = EQSI (* FLD (i_Ri), 0); CPU (h_zbit) = opval; @@ -516,8 +516,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} #undef FLD } @@ -532,7 +532,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; tmp_tmp = ADDCSI (* FLD (i_Ri), * FLD (i_Rj), CPU (h_cbit)); { @@ -550,7 +550,7 @@ do { * FLD (i_Ri) = opval; TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -do { +{ { BI opval = EQSI (* FLD (i_Ri), 0); CPU (h_zbit) = opval; @@ -561,8 +561,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} #undef FLD } @@ -634,7 +634,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { BI opval = SUBOFSI (* FLD (i_Ri), * FLD (i_Rj), 0); CPU (h_vbit) = opval; @@ -650,7 +650,7 @@ do { * FLD (i_Ri) = opval; TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -do { +{ { BI opval = EQSI (* FLD (i_Ri), 0); CPU (h_zbit) = opval; @@ -661,8 +661,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} #undef FLD } @@ -677,7 +677,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; tmp_tmp = SUBCSI (* FLD (i_Ri), * FLD (i_Rj), CPU (h_cbit)); { @@ -695,7 +695,7 @@ do { * FLD (i_Ri) = opval; TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -do { +{ { BI opval = EQSI (* FLD (i_Ri), 0); CPU (h_zbit) = opval; @@ -706,8 +706,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} #undef FLD } @@ -741,7 +741,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp1; { BI opval = SUBOFSI (* FLD (i_Ri), * FLD (i_Rj), 0); @@ -754,7 +754,7 @@ do { TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); } tmp_tmp1 = SUBSI (* FLD (i_Ri), * FLD (i_Rj)); -do { +{ { BI opval = EQSI (tmp_tmp1, 0); CPU (h_zbit) = opval; @@ -765,8 +765,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} #undef FLD } @@ -781,7 +781,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp1; { BI opval = SUBOFSI (* FLD (i_Ri), FLD (f_u4), 0); @@ -794,7 +794,7 @@ do { TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); } tmp_tmp1 = SUBSI (* FLD (i_Ri), FLD (f_u4)); -do { +{ { BI opval = EQSI (tmp_tmp1, 0); CPU (h_zbit) = opval; @@ -805,8 +805,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} #undef FLD } @@ -821,7 +821,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp1; { BI opval = SUBOFSI (* FLD (i_Ri), FLD (f_m4), 0); @@ -834,7 +834,7 @@ do { TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); } tmp_tmp1 = SUBSI (* FLD (i_Ri), FLD (f_m4)); -do { +{ { BI opval = EQSI (tmp_tmp1, 0); CPU (h_zbit) = opval; @@ -845,8 +845,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} #undef FLD } @@ -861,13 +861,13 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = ANDSI (* FLD (i_Ri), * FLD (i_Rj)); * FLD (i_Ri) = opval; TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -do { +{ { BI opval = EQSI (* FLD (i_Ri), 0); CPU (h_zbit) = opval; @@ -878,8 +878,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} #undef FLD } @@ -894,13 +894,13 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = ORSI (* FLD (i_Ri), * FLD (i_Rj)); * FLD (i_Ri) = opval; TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -do { +{ { BI opval = EQSI (* FLD (i_Ri), 0); CPU (h_zbit) = opval; @@ -911,8 +911,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} #undef FLD } @@ -927,13 +927,13 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = XORSI (* FLD (i_Ri), * FLD (i_Rj)); * FLD (i_Ri) = opval; TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -do { +{ { BI opval = EQSI (* FLD (i_Ri), 0); CPU (h_zbit) = opval; @@ -944,8 +944,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} #undef FLD } @@ -960,10 +960,10 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; tmp_tmp = ANDSI (GETMEMSI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj)); -do { +{ { BI opval = EQSI (tmp_tmp, 0); CPU (h_zbit) = opval; @@ -974,13 +974,13 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} { SI opval = tmp_tmp; SETMEMSI (current_cpu, pc, * FLD (i_Ri), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -995,10 +995,10 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ HI tmp_tmp; tmp_tmp = ANDHI (GETMEMHI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj)); -do { +{ { BI opval = EQHI (tmp_tmp, 0); CPU (h_zbit) = opval; @@ -1009,13 +1009,13 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} { HI opval = tmp_tmp; SETMEMHI (current_cpu, pc, * FLD (i_Ri), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -1030,10 +1030,10 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ QI tmp_tmp; tmp_tmp = ANDQI (GETMEMQI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj)); -do { +{ { BI opval = EQQI (tmp_tmp, 0); CPU (h_zbit) = opval; @@ -1044,13 +1044,13 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} { QI opval = tmp_tmp; SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -1065,10 +1065,10 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; tmp_tmp = ORSI (GETMEMSI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj)); -do { +{ { BI opval = EQSI (tmp_tmp, 0); CPU (h_zbit) = opval; @@ -1079,13 +1079,13 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} { SI opval = tmp_tmp; SETMEMSI (current_cpu, pc, * FLD (i_Ri), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -1100,10 +1100,10 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ HI tmp_tmp; tmp_tmp = ORHI (GETMEMHI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj)); -do { +{ { BI opval = EQHI (tmp_tmp, 0); CPU (h_zbit) = opval; @@ -1114,13 +1114,13 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} { HI opval = tmp_tmp; SETMEMHI (current_cpu, pc, * FLD (i_Ri), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -1135,10 +1135,10 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ QI tmp_tmp; tmp_tmp = ORQI (GETMEMQI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj)); -do { +{ { BI opval = EQQI (tmp_tmp, 0); CPU (h_zbit) = opval; @@ -1149,13 +1149,13 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} { QI opval = tmp_tmp; SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -1170,10 +1170,10 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; tmp_tmp = XORSI (GETMEMSI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj)); -do { +{ { BI opval = EQSI (tmp_tmp, 0); CPU (h_zbit) = opval; @@ -1184,13 +1184,13 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} { SI opval = tmp_tmp; SETMEMSI (current_cpu, pc, * FLD (i_Ri), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -1205,10 +1205,10 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ HI tmp_tmp; tmp_tmp = XORHI (GETMEMHI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj)); -do { +{ { BI opval = EQHI (tmp_tmp, 0); CPU (h_zbit) = opval; @@ -1219,13 +1219,13 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} { HI opval = tmp_tmp; SETMEMHI (current_cpu, pc, * FLD (i_Ri), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -1240,10 +1240,10 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ QI tmp_tmp; tmp_tmp = XORQI (GETMEMQI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj)); -do { +{ { BI opval = EQQI (tmp_tmp, 0); CPU (h_zbit) = opval; @@ -1254,13 +1254,13 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} { QI opval = tmp_tmp; SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -1389,7 +1389,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ QI tmp_tmp; tmp_tmp = ANDQI (FLD (f_u4), GETMEMQI (current_cpu, pc, * FLD (i_Ri))); { @@ -1402,7 +1402,7 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} #undef FLD } @@ -1417,7 +1417,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ QI tmp_tmp; tmp_tmp = ANDQI (SLLQI (FLD (f_u4), 4), GETMEMQI (current_cpu, pc, * FLD (i_Ri))); { @@ -1430,7 +1430,7 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} #undef FLD } @@ -1445,7 +1445,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ DI tmp_tmp; tmp_tmp = MULDI (EXTSIDI (* FLD (i_Rj)), EXTSIDI (* FLD (i_Ri))); { @@ -1473,7 +1473,7 @@ do { CPU (h_vbit) = opval; TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); } -} while (0); +} #undef FLD } @@ -1488,7 +1488,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ DI tmp_tmp; tmp_tmp = MULDI (ZEXTSIDI (* FLD (i_Rj)), ZEXTSIDI (* FLD (i_Ri))); { @@ -1516,7 +1516,7 @@ do { CPU (h_vbit) = opval; TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); } -} while (0); +} #undef FLD } @@ -1531,7 +1531,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = MULHI (TRUNCSIHI (* FLD (i_Rj)), TRUNCSIHI (* FLD (i_Ri))); SET_H_DR (((UINT) 5), opval); @@ -1547,7 +1547,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} #undef FLD } @@ -1562,7 +1562,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = MULSI (ANDSI (* FLD (i_Rj), 65535), ANDSI (* FLD (i_Ri), 65535)); SET_H_DR (((UINT) 5), opval); @@ -1578,7 +1578,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} #undef FLD } @@ -1593,7 +1593,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { BI opval = LTSI (GET_H_DR (((UINT) 5)), 0); CPU (h_d0bit) = opval; @@ -1619,7 +1619,7 @@ if (NEBI (CPU (h_d0bit), 0)) { TRACE_RESULT (current_cpu, abuf, "dr-4", 'x', opval); } } -} while (0); +} abuf->written = written; #undef FLD @@ -1635,7 +1635,7 @@ if (NEBI (CPU (h_d0bit), 0)) { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { BI opval = 0; CPU (h_d0bit) = opval; @@ -1651,7 +1651,7 @@ do { SET_H_DR (((UINT) 4), opval); TRACE_RESULT (current_cpu, abuf, "dr-4", 'x', opval); } -} while (0); +} #undef FLD } @@ -1666,7 +1666,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; { SI opval = SLLSI (GET_H_DR (((UINT) 4)), 1); @@ -1686,7 +1686,7 @@ if (LTSI (GET_H_DR (((UINT) 5)), 0)) { TRACE_RESULT (current_cpu, abuf, "dr-5", 'x', opval); } if (EQBI (CPU (h_d1bit), 1)) { -do { +{ tmp_tmp = ADDSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri)); { BI opval = ADDCFSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri), 0); @@ -1694,9 +1694,9 @@ do { written |= (1 << 6); TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); } -} while (0); +} } else { -do { +{ tmp_tmp = SUBSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri)); { BI opval = SUBCFSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri), 0); @@ -1704,10 +1704,10 @@ do { written |= (1 << 6); TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); } -} while (0); +} } if (NOTBI (XORBI (XORBI (CPU (h_d0bit), CPU (h_d1bit)), CPU (h_cbit)))) { -do { +{ { SI opval = tmp_tmp; SET_H_DR (((UINT) 4), opval); @@ -1718,14 +1718,14 @@ do { SET_H_DR (((UINT) 5), opval); TRACE_RESULT (current_cpu, abuf, "dr-5", 'x', opval); } -} while (0); +} } { BI opval = EQSI (GET_H_DR (((UINT) 4)), 0); CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} abuf->written = written; #undef FLD @@ -1741,10 +1741,10 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; if (EQBI (CPU (h_d1bit), 1)) { -do { +{ tmp_tmp = ADDSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri)); { BI opval = ADDCFSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri), 0); @@ -1752,9 +1752,9 @@ do { written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); } -} while (0); +} } else { -do { +{ tmp_tmp = SUBSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri)); { BI opval = SUBCFSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri), 0); @@ -1762,10 +1762,10 @@ do { written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); } -} while (0); +} } if (EQSI (tmp_tmp, 0)) { -do { +{ { BI opval = 1; CPU (h_zbit) = opval; @@ -1778,7 +1778,7 @@ do { written |= (1 << 4); TRACE_RESULT (current_cpu, abuf, "dr-4", 'x', opval); } -} while (0); +} } else { { BI opval = 0; @@ -1787,7 +1787,7 @@ do { TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } } -} while (0); +} abuf->written = written; #undef FLD @@ -1849,11 +1849,11 @@ if (EQBI (CPU (h_d1bit), 1)) { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_shift; tmp_shift = ANDSI (* FLD (i_Rj), 31); if (NESI (tmp_shift, 0)) { -do { +{ { BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (32, tmp_shift))), 0); CPU (h_cbit) = opval; @@ -1866,7 +1866,7 @@ do { written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -} while (0); +} } else { { BI opval = 0; @@ -1885,7 +1885,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} abuf->written = written; #undef FLD @@ -1901,11 +1901,11 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_shift; tmp_shift = FLD (f_u4); if (NESI (tmp_shift, 0)) { -do { +{ { BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (32, tmp_shift))), 0); CPU (h_cbit) = opval; @@ -1918,7 +1918,7 @@ do { written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -} while (0); +} } else { { BI opval = 0; @@ -1937,7 +1937,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} abuf->written = written; #undef FLD @@ -1953,11 +1953,11 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_shift; tmp_shift = ADDSI (FLD (f_u4), 16); if (NESI (tmp_shift, 0)) { -do { +{ { BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (32, tmp_shift))), 0); CPU (h_cbit) = opval; @@ -1970,7 +1970,7 @@ do { written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -} while (0); +} } else { { BI opval = 0; @@ -1989,7 +1989,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} abuf->written = written; #undef FLD @@ -2005,11 +2005,11 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_shift; tmp_shift = ANDSI (* FLD (i_Rj), 31); if (NESI (tmp_shift, 0)) { -do { +{ { BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0); CPU (h_cbit) = opval; @@ -2022,7 +2022,7 @@ do { written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -} while (0); +} } else { { BI opval = 0; @@ -2041,7 +2041,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} abuf->written = written; #undef FLD @@ -2057,11 +2057,11 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_shift; tmp_shift = FLD (f_u4); if (NESI (tmp_shift, 0)) { -do { +{ { BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0); CPU (h_cbit) = opval; @@ -2074,7 +2074,7 @@ do { written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -} while (0); +} } else { { BI opval = 0; @@ -2093,7 +2093,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} abuf->written = written; #undef FLD @@ -2109,11 +2109,11 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_shift; tmp_shift = ADDSI (FLD (f_u4), 16); if (NESI (tmp_shift, 0)) { -do { +{ { BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0); CPU (h_cbit) = opval; @@ -2126,7 +2126,7 @@ do { written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -} while (0); +} } else { { BI opval = 0; @@ -2145,7 +2145,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} abuf->written = written; #undef FLD @@ -2161,11 +2161,11 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_shift; tmp_shift = ANDSI (* FLD (i_Rj), 31); if (NESI (tmp_shift, 0)) { -do { +{ { BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0); CPU (h_cbit) = opval; @@ -2178,7 +2178,7 @@ do { written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -} while (0); +} } else { { BI opval = 0; @@ -2197,7 +2197,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} abuf->written = written; #undef FLD @@ -2213,11 +2213,11 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_shift; tmp_shift = FLD (f_u4); if (NESI (tmp_shift, 0)) { -do { +{ { BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0); CPU (h_cbit) = opval; @@ -2230,7 +2230,7 @@ do { written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -} while (0); +} } else { { BI opval = 0; @@ -2249,7 +2249,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} abuf->written = written; #undef FLD @@ -2265,11 +2265,11 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_shift; tmp_shift = ADDSI (FLD (f_u4), 16); if (NESI (tmp_shift, 0)) { -do { +{ { BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0); CPU (h_cbit) = opval; @@ -2282,7 +2282,7 @@ do { written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -} while (0); +} } else { { BI opval = 0; @@ -2301,7 +2301,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} abuf->written = written; #undef FLD @@ -2564,7 +2564,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); * FLD (i_Ri) = opval; @@ -2578,7 +2578,7 @@ if (NESI (FLD (f_Ri), 15)) { TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } } -} while (0); +} abuf->written = written; #undef FLD @@ -2594,7 +2594,7 @@ if (NESI (FLD (f_Ri), 15)) { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; tmp_tmp = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); { @@ -2607,7 +2607,7 @@ do { SET_H_DR (FLD (f_Rs2), opval); TRACE_RESULT (current_cpu, abuf, "Rs2", 'x', opval); } -} while (0); +} #undef FLD } @@ -2622,7 +2622,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { USI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); SET_H_PS (opval); @@ -2633,7 +2633,7 @@ do { CPU (h_gr[((UINT) 15)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} #undef FLD } @@ -2838,7 +2838,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; tmp_tmp = * FLD (i_Ri); { @@ -2851,7 +2851,7 @@ do { SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -2866,7 +2866,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; tmp_tmp = GET_H_DR (FLD (f_Rs2)); { @@ -2879,7 +2879,7 @@ do { SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -2894,7 +2894,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -2905,7 +2905,7 @@ do { SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -3037,13 +3037,13 @@ do { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { USI opval = * FLD (i_Ri); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); #undef FLD @@ -3060,7 +3060,7 @@ do { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = ADDSI (pc, 2); SET_H_DR (((UINT) 1), opval); @@ -3071,7 +3071,7 @@ do { SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); #undef FLD @@ -3088,8 +3088,8 @@ do { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { -do { +{ +{ { SI opval = ADDSI (pc, 4); SET_H_DR (((UINT) 1), opval); @@ -3100,8 +3100,8 @@ do { SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); -} while (0); +} +} SEM_BRANCH_FINI (vpc); #undef FLD @@ -3118,7 +3118,7 @@ do { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = ADDSI (pc, 2); SET_H_DR (((UINT) 1), opval); @@ -3129,7 +3129,7 @@ do { SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); #undef FLD @@ -3146,8 +3146,8 @@ do { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { -do { +{ +{ { SI opval = ADDSI (pc, 4); SET_H_DR (((UINT) 1), opval); @@ -3158,8 +3158,8 @@ do { SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); -} while (0); +} +} SEM_BRANCH_FINI (vpc); #undef FLD @@ -3197,13 +3197,13 @@ do { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { USI opval = GET_H_DR (((UINT) 1)); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); #undef FLD @@ -3220,7 +3220,7 @@ do { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ ; /*clobber*/ ; /*clobber*/ ; /*clobber*/ @@ -3229,7 +3229,7 @@ do { SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); #undef FLD @@ -3246,7 +3246,7 @@ do { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ ; /*clobber*/ ; /*clobber*/ ; /*clobber*/ @@ -3255,7 +3255,7 @@ do { SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); #undef FLD @@ -3273,7 +3273,7 @@ do { vpc = SEM_NEXT_VPC (sem_arg, pc, 2); if (EQBI (GET_H_SBIT (), 0)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, GET_H_DR (((UINT) 2))); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); @@ -3298,9 +3298,9 @@ do { written |= (1 << 5); TRACE_RESULT (current_cpu, abuf, "dr-2", 'x', opval); } -} while (0); +} } else { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, GET_H_DR (((UINT) 3))); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); @@ -3325,7 +3325,7 @@ do { written |= (1 << 6); TRACE_RESULT (current_cpu, abuf, "dr-3", 'x', opval); } -} while (0); +} } abuf->written = written; @@ -3344,13 +3344,13 @@ do { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { USI opval = FLD (i_label9); SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); #undef FLD @@ -3387,9 +3387,9 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ do { } while (0); /*nop*/ -} while (0); +} #undef FLD } @@ -3420,7 +3420,7 @@ do { } while (0); /*nop*/ SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (CPU (h_zbit)) { { USI opval = FLD (i_label9); @@ -3429,7 +3429,7 @@ if (CPU (h_zbit)) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3472,7 +3472,7 @@ if (CPU (h_zbit)) { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (NOTBI (CPU (h_zbit))) { { USI opval = FLD (i_label9); @@ -3481,7 +3481,7 @@ if (NOTBI (CPU (h_zbit))) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3524,7 +3524,7 @@ if (NOTBI (CPU (h_zbit))) { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (CPU (h_cbit)) { { USI opval = FLD (i_label9); @@ -3533,7 +3533,7 @@ if (CPU (h_cbit)) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3576,7 +3576,7 @@ if (CPU (h_cbit)) { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (NOTBI (CPU (h_cbit))) { { USI opval = FLD (i_label9); @@ -3585,7 +3585,7 @@ if (NOTBI (CPU (h_cbit))) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3628,7 +3628,7 @@ if (NOTBI (CPU (h_cbit))) { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (CPU (h_nbit)) { { USI opval = FLD (i_label9); @@ -3637,7 +3637,7 @@ if (CPU (h_nbit)) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3680,7 +3680,7 @@ if (CPU (h_nbit)) { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (NOTBI (CPU (h_nbit))) { { USI opval = FLD (i_label9); @@ -3689,7 +3689,7 @@ if (NOTBI (CPU (h_nbit))) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3732,7 +3732,7 @@ if (NOTBI (CPU (h_nbit))) { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (CPU (h_vbit)) { { USI opval = FLD (i_label9); @@ -3741,7 +3741,7 @@ if (CPU (h_vbit)) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3784,7 +3784,7 @@ if (CPU (h_vbit)) { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (NOTBI (CPU (h_vbit))) { { USI opval = FLD (i_label9); @@ -3793,7 +3793,7 @@ if (NOTBI (CPU (h_vbit))) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3836,7 +3836,7 @@ if (NOTBI (CPU (h_vbit))) { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (XORBI (CPU (h_vbit), CPU (h_nbit))) { { USI opval = FLD (i_label9); @@ -3845,7 +3845,7 @@ if (XORBI (CPU (h_vbit), CPU (h_nbit))) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3888,7 +3888,7 @@ if (XORBI (CPU (h_vbit), CPU (h_nbit))) { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)))) { { USI opval = FLD (i_label9); @@ -3897,7 +3897,7 @@ if (NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)))) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3940,7 +3940,7 @@ if (NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)))) { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit))) { { USI opval = FLD (i_label9); @@ -3949,7 +3949,7 @@ if (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit))) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3992,7 +3992,7 @@ if (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit))) { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)))) { { USI opval = FLD (i_label9); @@ -4001,7 +4001,7 @@ if (NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)))) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -4044,7 +4044,7 @@ if (NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)))) { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (ORBI (CPU (h_cbit), CPU (h_zbit))) { { USI opval = FLD (i_label9); @@ -4053,7 +4053,7 @@ if (ORBI (CPU (h_cbit), CPU (h_zbit))) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -4096,7 +4096,7 @@ if (ORBI (CPU (h_cbit), CPU (h_zbit))) { SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) { { USI opval = FLD (i_label9); @@ -4105,7 +4105,7 @@ if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -4204,7 +4204,7 @@ if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 13)])); SETMEMSI (current_cpu, pc, FLD (f_dir10), opval); @@ -4215,7 +4215,7 @@ do { CPU (h_gr[((UINT) 13)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval); } -} while (0); +} #undef FLD } @@ -4230,7 +4230,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { HI opval = GETMEMHI (current_cpu, pc, CPU (h_gr[((UINT) 13)])); SETMEMHI (current_cpu, pc, FLD (f_dir9), opval); @@ -4241,7 +4241,7 @@ do { CPU (h_gr[((UINT) 13)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval); } -} while (0); +} #undef FLD } @@ -4256,7 +4256,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { QI opval = GETMEMQI (current_cpu, pc, CPU (h_gr[((UINT) 13)])); SETMEMQI (current_cpu, pc, FLD (f_dir8), opval); @@ -4267,7 +4267,7 @@ do { CPU (h_gr[((UINT) 13)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval); } -} while (0); +} #undef FLD } @@ -4282,7 +4282,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); SETMEMSI (current_cpu, pc, FLD (f_dir10), opval); @@ -4293,7 +4293,7 @@ do { CPU (h_gr[((UINT) 15)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} #undef FLD } @@ -4365,7 +4365,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = GETMEMSI (current_cpu, pc, FLD (f_dir10)); SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 13)]), opval); @@ -4376,7 +4376,7 @@ do { CPU (h_gr[((UINT) 13)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval); } -} while (0); +} #undef FLD } @@ -4391,7 +4391,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { HI opval = GETMEMHI (current_cpu, pc, FLD (f_dir9)); SETMEMHI (current_cpu, pc, CPU (h_gr[((UINT) 13)]), opval); @@ -4402,7 +4402,7 @@ do { CPU (h_gr[((UINT) 13)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval); } -} while (0); +} #undef FLD } @@ -4417,7 +4417,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { QI opval = GETMEMQI (current_cpu, pc, FLD (f_dir8)); SETMEMQI (current_cpu, pc, CPU (h_gr[((UINT) 13)]), opval); @@ -4428,7 +4428,7 @@ do { CPU (h_gr[((UINT) 13)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval); } -} while (0); +} #undef FLD } @@ -4443,7 +4443,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -4454,7 +4454,7 @@ do { SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } @@ -4734,9 +4734,9 @@ do { } while (0); /*nop*/ IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (ANDSI (FLD (f_reglist_low_ld), 1)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 0)]) = opval; @@ -4749,10 +4749,10 @@ do { written |= (1 << 5); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_ld), 2)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 1)]) = opval; @@ -4765,10 +4765,10 @@ do { written |= (1 << 5); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_ld), 4)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 2)]) = opval; @@ -4781,10 +4781,10 @@ do { written |= (1 << 5); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_ld), 8)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 3)]) = opval; @@ -4797,10 +4797,10 @@ do { written |= (1 << 5); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_ld), 16)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 4)]) = opval; @@ -4813,10 +4813,10 @@ do { written |= (1 << 5); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_ld), 32)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 5)]) = opval; @@ -4829,10 +4829,10 @@ do { written |= (1 << 5); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_ld), 64)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 6)]) = opval; @@ -4845,10 +4845,10 @@ do { written |= (1 << 5); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_ld), 128)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 7)]) = opval; @@ -4861,9 +4861,9 @@ do { written |= (1 << 5); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); } -} while (0); +} +} abuf->written = written; #undef FLD @@ -4879,9 +4879,9 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (ANDSI (FLD (f_reglist_hi_ld), 1)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 8)]) = opval; @@ -4894,10 +4894,10 @@ do { written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_ld), 2)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 9)]) = opval; @@ -4910,10 +4910,10 @@ do { written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_ld), 4)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 10)]) = opval; @@ -4926,10 +4926,10 @@ do { written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_ld), 8)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 11)]) = opval; @@ -4942,10 +4942,10 @@ do { written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_ld), 16)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 12)]) = opval; @@ -4958,10 +4958,10 @@ do { written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_ld), 32)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 13)]) = opval; @@ -4974,10 +4974,10 @@ do { written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_ld), 64)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 14)]) = opval; @@ -4990,7 +4990,7 @@ do { written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_ld), 128)) { { @@ -5000,7 +5000,7 @@ if (ANDSI (FLD (f_reglist_hi_ld), 128)) { TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } } -} while (0); +} abuf->written = written; #undef FLD @@ -5016,9 +5016,9 @@ if (ANDSI (FLD (f_reglist_hi_ld), 128)) { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (ANDSI (FLD (f_reglist_low_st), 1)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5031,10 +5031,10 @@ do { written |= (1 << 11); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_st), 2)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5047,10 +5047,10 @@ do { written |= (1 << 11); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_st), 4)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5063,10 +5063,10 @@ do { written |= (1 << 11); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_st), 8)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5079,10 +5079,10 @@ do { written |= (1 << 11); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_st), 16)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5095,10 +5095,10 @@ do { written |= (1 << 11); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_st), 32)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5111,10 +5111,10 @@ do { written |= (1 << 11); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_st), 64)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5127,10 +5127,10 @@ do { written |= (1 << 11); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_st), 128)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5143,9 +5143,9 @@ do { written |= (1 << 11); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); } -} while (0); +} +} abuf->written = written; #undef FLD @@ -5161,9 +5161,9 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (ANDSI (FLD (f_reglist_hi_st), 1)) { -do { +{ SI tmp_save_r15; tmp_save_r15 = CPU (h_gr[((UINT) 15)]); { @@ -5178,10 +5178,10 @@ do { written |= (1 << 10); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_st), 2)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5194,10 +5194,10 @@ do { written |= (1 << 10); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_st), 4)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5210,10 +5210,10 @@ do { written |= (1 << 10); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_st), 8)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5226,10 +5226,10 @@ do { written |= (1 << 10); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_st), 16)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5242,10 +5242,10 @@ do { written |= (1 << 10); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_st), 32)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5258,10 +5258,10 @@ do { written |= (1 << 10); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_st), 64)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5274,10 +5274,10 @@ do { written |= (1 << 10); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_st), 128)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5290,9 +5290,9 @@ do { written |= (1 << 10); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); } -} while (0); +} +} abuf->written = written; #undef FLD @@ -5308,7 +5308,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; tmp_tmp = SUBSI (CPU (h_gr[((UINT) 15)]), 4); { @@ -5326,7 +5326,7 @@ do { CPU (h_gr[((UINT) 15)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} #undef FLD } @@ -5341,7 +5341,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = ADDSI (CPU (h_gr[((UINT) 14)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5352,7 +5352,7 @@ do { CPU (h_gr[((UINT) 14)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval); } -} while (0); +} #undef FLD } @@ -5367,7 +5367,7 @@ do { IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; tmp_tmp = * FLD (i_Ri); { @@ -5380,7 +5380,7 @@ do { SETMEMUQI (current_cpu, pc, * FLD (i_Rj), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} #undef FLD } diff --git a/sim/fr30/sem.c b/sim/fr30/sem.c index 8224c33..e35c421 100644 --- a/sim/fr30/sem.c +++ b/sim/fr30/sem.c @@ -191,7 +191,7 @@ SEM_FN_NAME (fr30bf,add) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { BI opval = ADDOFSI (* FLD (i_Ri), * FLD (i_Rj), 0); CPU (h_vbit) = opval; @@ -207,7 +207,7 @@ do { * FLD (i_Ri) = opval; TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -do { +{ { BI opval = EQSI (* FLD (i_Ri), 0); CPU (h_zbit) = opval; @@ -218,8 +218,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} return vpc; #undef FLD @@ -236,7 +236,7 @@ SEM_FN_NAME (fr30bf,addi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { BI opval = ADDOFSI (* FLD (i_Ri), FLD (f_u4), 0); CPU (h_vbit) = opval; @@ -252,7 +252,7 @@ do { * FLD (i_Ri) = opval; TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -do { +{ { BI opval = EQSI (* FLD (i_Ri), 0); CPU (h_zbit) = opval; @@ -263,8 +263,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} return vpc; #undef FLD @@ -281,7 +281,7 @@ SEM_FN_NAME (fr30bf,add2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { BI opval = ADDOFSI (* FLD (i_Ri), FLD (f_m4), 0); CPU (h_vbit) = opval; @@ -297,7 +297,7 @@ do { * FLD (i_Ri) = opval; TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -do { +{ { BI opval = EQSI (* FLD (i_Ri), 0); CPU (h_zbit) = opval; @@ -308,8 +308,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} return vpc; #undef FLD @@ -326,7 +326,7 @@ SEM_FN_NAME (fr30bf,addc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; tmp_tmp = ADDCSI (* FLD (i_Ri), * FLD (i_Rj), CPU (h_cbit)); { @@ -344,7 +344,7 @@ do { * FLD (i_Ri) = opval; TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -do { +{ { BI opval = EQSI (* FLD (i_Ri), 0); CPU (h_zbit) = opval; @@ -355,8 +355,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} return vpc; #undef FLD @@ -436,7 +436,7 @@ SEM_FN_NAME (fr30bf,sub) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { BI opval = SUBOFSI (* FLD (i_Ri), * FLD (i_Rj), 0); CPU (h_vbit) = opval; @@ -452,7 +452,7 @@ do { * FLD (i_Ri) = opval; TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -do { +{ { BI opval = EQSI (* FLD (i_Ri), 0); CPU (h_zbit) = opval; @@ -463,8 +463,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} return vpc; #undef FLD @@ -481,7 +481,7 @@ SEM_FN_NAME (fr30bf,subc) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; tmp_tmp = SUBCSI (* FLD (i_Ri), * FLD (i_Rj), CPU (h_cbit)); { @@ -499,7 +499,7 @@ do { * FLD (i_Ri) = opval; TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -do { +{ { BI opval = EQSI (* FLD (i_Ri), 0); CPU (h_zbit) = opval; @@ -510,8 +510,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} return vpc; #undef FLD @@ -549,7 +549,7 @@ SEM_FN_NAME (fr30bf,cmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp1; { BI opval = SUBOFSI (* FLD (i_Ri), * FLD (i_Rj), 0); @@ -562,7 +562,7 @@ do { TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); } tmp_tmp1 = SUBSI (* FLD (i_Ri), * FLD (i_Rj)); -do { +{ { BI opval = EQSI (tmp_tmp1, 0); CPU (h_zbit) = opval; @@ -573,8 +573,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} return vpc; #undef FLD @@ -591,7 +591,7 @@ SEM_FN_NAME (fr30bf,cmpi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp1; { BI opval = SUBOFSI (* FLD (i_Ri), FLD (f_u4), 0); @@ -604,7 +604,7 @@ do { TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); } tmp_tmp1 = SUBSI (* FLD (i_Ri), FLD (f_u4)); -do { +{ { BI opval = EQSI (tmp_tmp1, 0); CPU (h_zbit) = opval; @@ -615,8 +615,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} return vpc; #undef FLD @@ -633,7 +633,7 @@ SEM_FN_NAME (fr30bf,cmp2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp1; { BI opval = SUBOFSI (* FLD (i_Ri), FLD (f_m4), 0); @@ -646,7 +646,7 @@ do { TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); } tmp_tmp1 = SUBSI (* FLD (i_Ri), FLD (f_m4)); -do { +{ { BI opval = EQSI (tmp_tmp1, 0); CPU (h_zbit) = opval; @@ -657,8 +657,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} return vpc; #undef FLD @@ -675,13 +675,13 @@ SEM_FN_NAME (fr30bf,and) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = ANDSI (* FLD (i_Ri), * FLD (i_Rj)); * FLD (i_Ri) = opval; TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -do { +{ { BI opval = EQSI (* FLD (i_Ri), 0); CPU (h_zbit) = opval; @@ -692,8 +692,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} return vpc; #undef FLD @@ -710,13 +710,13 @@ SEM_FN_NAME (fr30bf,or) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = ORSI (* FLD (i_Ri), * FLD (i_Rj)); * FLD (i_Ri) = opval; TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -do { +{ { BI opval = EQSI (* FLD (i_Ri), 0); CPU (h_zbit) = opval; @@ -727,8 +727,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} return vpc; #undef FLD @@ -745,13 +745,13 @@ SEM_FN_NAME (fr30bf,eor) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = XORSI (* FLD (i_Ri), * FLD (i_Rj)); * FLD (i_Ri) = opval; TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -do { +{ { BI opval = EQSI (* FLD (i_Ri), 0); CPU (h_zbit) = opval; @@ -762,8 +762,8 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); -} while (0); +} +} return vpc; #undef FLD @@ -780,10 +780,10 @@ SEM_FN_NAME (fr30bf,andm) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; tmp_tmp = ANDSI (GETMEMSI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj)); -do { +{ { BI opval = EQSI (tmp_tmp, 0); CPU (h_zbit) = opval; @@ -794,13 +794,13 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} { SI opval = tmp_tmp; SETMEMSI (current_cpu, pc, * FLD (i_Ri), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -817,10 +817,10 @@ SEM_FN_NAME (fr30bf,andh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ HI tmp_tmp; tmp_tmp = ANDHI (GETMEMHI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj)); -do { +{ { BI opval = EQHI (tmp_tmp, 0); CPU (h_zbit) = opval; @@ -831,13 +831,13 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} { HI opval = tmp_tmp; SETMEMHI (current_cpu, pc, * FLD (i_Ri), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -854,10 +854,10 @@ SEM_FN_NAME (fr30bf,andb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ QI tmp_tmp; tmp_tmp = ANDQI (GETMEMQI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj)); -do { +{ { BI opval = EQQI (tmp_tmp, 0); CPU (h_zbit) = opval; @@ -868,13 +868,13 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} { QI opval = tmp_tmp; SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -891,10 +891,10 @@ SEM_FN_NAME (fr30bf,orm) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; tmp_tmp = ORSI (GETMEMSI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj)); -do { +{ { BI opval = EQSI (tmp_tmp, 0); CPU (h_zbit) = opval; @@ -905,13 +905,13 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} { SI opval = tmp_tmp; SETMEMSI (current_cpu, pc, * FLD (i_Ri), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -928,10 +928,10 @@ SEM_FN_NAME (fr30bf,orh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ HI tmp_tmp; tmp_tmp = ORHI (GETMEMHI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj)); -do { +{ { BI opval = EQHI (tmp_tmp, 0); CPU (h_zbit) = opval; @@ -942,13 +942,13 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} { HI opval = tmp_tmp; SETMEMHI (current_cpu, pc, * FLD (i_Ri), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -965,10 +965,10 @@ SEM_FN_NAME (fr30bf,orb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ QI tmp_tmp; tmp_tmp = ORQI (GETMEMQI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj)); -do { +{ { BI opval = EQQI (tmp_tmp, 0); CPU (h_zbit) = opval; @@ -979,13 +979,13 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} { QI opval = tmp_tmp; SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -1002,10 +1002,10 @@ SEM_FN_NAME (fr30bf,eorm) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; tmp_tmp = XORSI (GETMEMSI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj)); -do { +{ { BI opval = EQSI (tmp_tmp, 0); CPU (h_zbit) = opval; @@ -1016,13 +1016,13 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} { SI opval = tmp_tmp; SETMEMSI (current_cpu, pc, * FLD (i_Ri), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -1039,10 +1039,10 @@ SEM_FN_NAME (fr30bf,eorh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ HI tmp_tmp; tmp_tmp = XORHI (GETMEMHI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj)); -do { +{ { BI opval = EQHI (tmp_tmp, 0); CPU (h_zbit) = opval; @@ -1053,13 +1053,13 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} { HI opval = tmp_tmp; SETMEMHI (current_cpu, pc, * FLD (i_Ri), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -1076,10 +1076,10 @@ SEM_FN_NAME (fr30bf,eorb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ QI tmp_tmp; tmp_tmp = XORQI (GETMEMQI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj)); -do { +{ { BI opval = EQQI (tmp_tmp, 0); CPU (h_zbit) = opval; @@ -1090,13 +1090,13 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} { QI opval = tmp_tmp; SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -1239,7 +1239,7 @@ SEM_FN_NAME (fr30bf,btstl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ QI tmp_tmp; tmp_tmp = ANDQI (FLD (f_u4), GETMEMQI (current_cpu, pc, * FLD (i_Ri))); { @@ -1252,7 +1252,7 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -1269,7 +1269,7 @@ SEM_FN_NAME (fr30bf,btsth) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ QI tmp_tmp; tmp_tmp = ANDQI (SLLQI (FLD (f_u4), 4), GETMEMQI (current_cpu, pc, * FLD (i_Ri))); { @@ -1282,7 +1282,7 @@ do { CPU (h_nbit) = opval; TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -1299,7 +1299,7 @@ SEM_FN_NAME (fr30bf,mul) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ DI tmp_tmp; tmp_tmp = MULDI (EXTSIDI (* FLD (i_Rj)), EXTSIDI (* FLD (i_Ri))); { @@ -1327,7 +1327,7 @@ do { CPU (h_vbit) = opval; TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -1344,7 +1344,7 @@ SEM_FN_NAME (fr30bf,mulu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ DI tmp_tmp; tmp_tmp = MULDI (ZEXTSIDI (* FLD (i_Rj)), ZEXTSIDI (* FLD (i_Ri))); { @@ -1372,7 +1372,7 @@ do { CPU (h_vbit) = opval; TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -1389,7 +1389,7 @@ SEM_FN_NAME (fr30bf,mulh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = MULHI (TRUNCSIHI (* FLD (i_Rj)), TRUNCSIHI (* FLD (i_Ri))); SET_H_DR (((UINT) 5), opval); @@ -1405,7 +1405,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -1422,7 +1422,7 @@ SEM_FN_NAME (fr30bf,muluh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = MULSI (ANDSI (* FLD (i_Rj), 65535), ANDSI (* FLD (i_Ri), 65535)); SET_H_DR (((UINT) 5), opval); @@ -1438,7 +1438,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -1455,7 +1455,7 @@ SEM_FN_NAME (fr30bf,div0s) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { BI opval = LTSI (GET_H_DR (((UINT) 5)), 0); CPU (h_d0bit) = opval; @@ -1481,7 +1481,7 @@ if (NEBI (CPU (h_d0bit), 0)) { TRACE_RESULT (current_cpu, abuf, "dr-4", 'x', opval); } } -} while (0); +} abuf->written = written; return vpc; @@ -1499,7 +1499,7 @@ SEM_FN_NAME (fr30bf,div0u) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { BI opval = 0; CPU (h_d0bit) = opval; @@ -1515,7 +1515,7 @@ do { SET_H_DR (((UINT) 4), opval); TRACE_RESULT (current_cpu, abuf, "dr-4", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -1532,7 +1532,7 @@ SEM_FN_NAME (fr30bf,div1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; { SI opval = SLLSI (GET_H_DR (((UINT) 4)), 1); @@ -1552,7 +1552,7 @@ if (LTSI (GET_H_DR (((UINT) 5)), 0)) { TRACE_RESULT (current_cpu, abuf, "dr-5", 'x', opval); } if (EQBI (CPU (h_d1bit), 1)) { -do { +{ tmp_tmp = ADDSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri)); { BI opval = ADDCFSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri), 0); @@ -1560,9 +1560,9 @@ do { written |= (1 << 6); TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); } -} while (0); +} } else { -do { +{ tmp_tmp = SUBSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri)); { BI opval = SUBCFSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri), 0); @@ -1570,10 +1570,10 @@ do { written |= (1 << 6); TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); } -} while (0); +} } if (NOTBI (XORBI (XORBI (CPU (h_d0bit), CPU (h_d1bit)), CPU (h_cbit)))) { -do { +{ { SI opval = tmp_tmp; SET_H_DR (((UINT) 4), opval); @@ -1584,14 +1584,14 @@ do { SET_H_DR (((UINT) 5), opval); TRACE_RESULT (current_cpu, abuf, "dr-5", 'x', opval); } -} while (0); +} } { BI opval = EQSI (GET_H_DR (((UINT) 4)), 0); CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} abuf->written = written; return vpc; @@ -1609,10 +1609,10 @@ SEM_FN_NAME (fr30bf,div2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; if (EQBI (CPU (h_d1bit), 1)) { -do { +{ tmp_tmp = ADDSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri)); { BI opval = ADDCFSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri), 0); @@ -1620,9 +1620,9 @@ do { written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); } -} while (0); +} } else { -do { +{ tmp_tmp = SUBSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri)); { BI opval = SUBCFSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri), 0); @@ -1630,10 +1630,10 @@ do { written |= (1 << 3); TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); } -} while (0); +} } if (EQSI (tmp_tmp, 0)) { -do { +{ { BI opval = 1; CPU (h_zbit) = opval; @@ -1646,7 +1646,7 @@ do { written |= (1 << 4); TRACE_RESULT (current_cpu, abuf, "dr-4", 'x', opval); } -} while (0); +} } else { { BI opval = 0; @@ -1655,7 +1655,7 @@ do { TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } } -} while (0); +} abuf->written = written; return vpc; @@ -1723,11 +1723,11 @@ SEM_FN_NAME (fr30bf,lsl) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_shift; tmp_shift = ANDSI (* FLD (i_Rj), 31); if (NESI (tmp_shift, 0)) { -do { +{ { BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (32, tmp_shift))), 0); CPU (h_cbit) = opval; @@ -1740,7 +1740,7 @@ do { written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -} while (0); +} } else { { BI opval = 0; @@ -1759,7 +1759,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} abuf->written = written; return vpc; @@ -1777,11 +1777,11 @@ SEM_FN_NAME (fr30bf,lsli) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_shift; tmp_shift = FLD (f_u4); if (NESI (tmp_shift, 0)) { -do { +{ { BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (32, tmp_shift))), 0); CPU (h_cbit) = opval; @@ -1794,7 +1794,7 @@ do { written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -} while (0); +} } else { { BI opval = 0; @@ -1813,7 +1813,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} abuf->written = written; return vpc; @@ -1831,11 +1831,11 @@ SEM_FN_NAME (fr30bf,lsl2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_shift; tmp_shift = ADDSI (FLD (f_u4), 16); if (NESI (tmp_shift, 0)) { -do { +{ { BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (32, tmp_shift))), 0); CPU (h_cbit) = opval; @@ -1848,7 +1848,7 @@ do { written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -} while (0); +} } else { { BI opval = 0; @@ -1867,7 +1867,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} abuf->written = written; return vpc; @@ -1885,11 +1885,11 @@ SEM_FN_NAME (fr30bf,lsr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_shift; tmp_shift = ANDSI (* FLD (i_Rj), 31); if (NESI (tmp_shift, 0)) { -do { +{ { BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0); CPU (h_cbit) = opval; @@ -1902,7 +1902,7 @@ do { written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -} while (0); +} } else { { BI opval = 0; @@ -1921,7 +1921,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} abuf->written = written; return vpc; @@ -1939,11 +1939,11 @@ SEM_FN_NAME (fr30bf,lsri) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_shift; tmp_shift = FLD (f_u4); if (NESI (tmp_shift, 0)) { -do { +{ { BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0); CPU (h_cbit) = opval; @@ -1956,7 +1956,7 @@ do { written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -} while (0); +} } else { { BI opval = 0; @@ -1975,7 +1975,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} abuf->written = written; return vpc; @@ -1993,11 +1993,11 @@ SEM_FN_NAME (fr30bf,lsr2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_shift; tmp_shift = ADDSI (FLD (f_u4), 16); if (NESI (tmp_shift, 0)) { -do { +{ { BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0); CPU (h_cbit) = opval; @@ -2010,7 +2010,7 @@ do { written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -} while (0); +} } else { { BI opval = 0; @@ -2029,7 +2029,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} abuf->written = written; return vpc; @@ -2047,11 +2047,11 @@ SEM_FN_NAME (fr30bf,asr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_shift; tmp_shift = ANDSI (* FLD (i_Rj), 31); if (NESI (tmp_shift, 0)) { -do { +{ { BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0); CPU (h_cbit) = opval; @@ -2064,7 +2064,7 @@ do { written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -} while (0); +} } else { { BI opval = 0; @@ -2083,7 +2083,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} abuf->written = written; return vpc; @@ -2101,11 +2101,11 @@ SEM_FN_NAME (fr30bf,asri) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_shift; tmp_shift = FLD (f_u4); if (NESI (tmp_shift, 0)) { -do { +{ { BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0); CPU (h_cbit) = opval; @@ -2118,7 +2118,7 @@ do { written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -} while (0); +} } else { { BI opval = 0; @@ -2137,7 +2137,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} abuf->written = written; return vpc; @@ -2155,11 +2155,11 @@ SEM_FN_NAME (fr30bf,asr2) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_shift; tmp_shift = ADDSI (FLD (f_u4), 16); if (NESI (tmp_shift, 0)) { -do { +{ { BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0); CPU (h_cbit) = opval; @@ -2172,7 +2172,7 @@ do { written |= (1 << 2); TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval); } -} while (0); +} } else { { BI opval = 0; @@ -2191,7 +2191,7 @@ do { CPU (h_zbit) = opval; TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); } -} while (0); +} abuf->written = written; return vpc; @@ -2482,7 +2482,7 @@ SEM_FN_NAME (fr30bf,ldr15gr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); * FLD (i_Ri) = opval; @@ -2496,7 +2496,7 @@ if (NESI (FLD (f_Ri), 15)) { TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } } -} while (0); +} abuf->written = written; return vpc; @@ -2514,7 +2514,7 @@ SEM_FN_NAME (fr30bf,ldr15dr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; tmp_tmp = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); { @@ -2527,7 +2527,7 @@ do { SET_H_DR (FLD (f_Rs2), opval); TRACE_RESULT (current_cpu, abuf, "Rs2", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -2544,7 +2544,7 @@ SEM_FN_NAME (fr30bf,ldr15ps) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { USI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); SET_H_PS (opval); @@ -2555,7 +2555,7 @@ do { CPU (h_gr[((UINT) 15)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -2782,7 +2782,7 @@ SEM_FN_NAME (fr30bf,str15gr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; tmp_tmp = * FLD (i_Ri); { @@ -2795,7 +2795,7 @@ do { SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -2812,7 +2812,7 @@ SEM_FN_NAME (fr30bf,str15dr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; tmp_tmp = GET_H_DR (FLD (f_Rs2)); { @@ -2825,7 +2825,7 @@ do { SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -2842,7 +2842,7 @@ SEM_FN_NAME (fr30bf,str15ps) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -2853,7 +2853,7 @@ do { SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -2999,13 +2999,13 @@ SEM_FN_NAME (fr30bf,jmpd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { USI opval = * FLD (i_Ri); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); return vpc; @@ -3024,7 +3024,7 @@ SEM_FN_NAME (fr30bf,callr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = ADDSI (pc, 2); SET_H_DR (((UINT) 1), opval); @@ -3035,7 +3035,7 @@ do { SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); return vpc; @@ -3054,8 +3054,8 @@ SEM_FN_NAME (fr30bf,callrd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { -do { +{ +{ { SI opval = ADDSI (pc, 4); SET_H_DR (((UINT) 1), opval); @@ -3066,8 +3066,8 @@ do { SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); -} while (0); +} +} SEM_BRANCH_FINI (vpc); return vpc; @@ -3086,7 +3086,7 @@ SEM_FN_NAME (fr30bf,call) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = ADDSI (pc, 2); SET_H_DR (((UINT) 1), opval); @@ -3097,7 +3097,7 @@ do { SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); return vpc; @@ -3116,8 +3116,8 @@ SEM_FN_NAME (fr30bf,calld) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { -do { +{ +{ { SI opval = ADDSI (pc, 4); SET_H_DR (((UINT) 1), opval); @@ -3128,8 +3128,8 @@ do { SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); -} while (0); +} +} SEM_BRANCH_FINI (vpc); return vpc; @@ -3171,13 +3171,13 @@ SEM_FN_NAME (fr30bf,ret_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { USI opval = GET_H_DR (((UINT) 1)); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); return vpc; @@ -3196,7 +3196,7 @@ SEM_FN_NAME (fr30bf,int) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ ; /*clobber*/ ; /*clobber*/ ; /*clobber*/ @@ -3205,7 +3205,7 @@ do { SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); return vpc; @@ -3224,7 +3224,7 @@ SEM_FN_NAME (fr30bf,inte) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ ; /*clobber*/ ; /*clobber*/ ; /*clobber*/ @@ -3233,7 +3233,7 @@ do { SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); return vpc; @@ -3253,7 +3253,7 @@ SEM_FN_NAME (fr30bf,reti) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); if (EQBI (GET_H_SBIT (), 0)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, GET_H_DR (((UINT) 2))); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); @@ -3278,9 +3278,9 @@ do { written |= (1 << 5); TRACE_RESULT (current_cpu, abuf, "dr-2", 'x', opval); } -} while (0); +} } else { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, GET_H_DR (((UINT) 3))); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); @@ -3305,7 +3305,7 @@ do { written |= (1 << 6); TRACE_RESULT (current_cpu, abuf, "dr-3", 'x', opval); } -} while (0); +} } abuf->written = written; @@ -3326,13 +3326,13 @@ SEM_FN_NAME (fr30bf,brad) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { USI opval = FLD (i_label9); SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg)); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } -} while (0); +} SEM_BRANCH_FINI (vpc); return vpc; @@ -3373,9 +3373,9 @@ SEM_FN_NAME (fr30bf,bnod) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ do { } while (0); /*nop*/ -} while (0); +} return vpc; #undef FLD @@ -3410,7 +3410,7 @@ SEM_FN_NAME (fr30bf,beqd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (CPU (h_zbit)) { { USI opval = FLD (i_label9); @@ -3419,7 +3419,7 @@ if (CPU (h_zbit)) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3466,7 +3466,7 @@ SEM_FN_NAME (fr30bf,bned) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (NOTBI (CPU (h_zbit))) { { USI opval = FLD (i_label9); @@ -3475,7 +3475,7 @@ if (NOTBI (CPU (h_zbit))) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3522,7 +3522,7 @@ SEM_FN_NAME (fr30bf,bcd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (CPU (h_cbit)) { { USI opval = FLD (i_label9); @@ -3531,7 +3531,7 @@ if (CPU (h_cbit)) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3578,7 +3578,7 @@ SEM_FN_NAME (fr30bf,bncd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (NOTBI (CPU (h_cbit))) { { USI opval = FLD (i_label9); @@ -3587,7 +3587,7 @@ if (NOTBI (CPU (h_cbit))) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3634,7 +3634,7 @@ SEM_FN_NAME (fr30bf,bnd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (CPU (h_nbit)) { { USI opval = FLD (i_label9); @@ -3643,7 +3643,7 @@ if (CPU (h_nbit)) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3690,7 +3690,7 @@ SEM_FN_NAME (fr30bf,bpd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (NOTBI (CPU (h_nbit))) { { USI opval = FLD (i_label9); @@ -3699,7 +3699,7 @@ if (NOTBI (CPU (h_nbit))) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3746,7 +3746,7 @@ SEM_FN_NAME (fr30bf,bvd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (CPU (h_vbit)) { { USI opval = FLD (i_label9); @@ -3755,7 +3755,7 @@ if (CPU (h_vbit)) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3802,7 +3802,7 @@ SEM_FN_NAME (fr30bf,bnvd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (NOTBI (CPU (h_vbit))) { { USI opval = FLD (i_label9); @@ -3811,7 +3811,7 @@ if (NOTBI (CPU (h_vbit))) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3858,7 +3858,7 @@ SEM_FN_NAME (fr30bf,bltd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (XORBI (CPU (h_vbit), CPU (h_nbit))) { { USI opval = FLD (i_label9); @@ -3867,7 +3867,7 @@ if (XORBI (CPU (h_vbit), CPU (h_nbit))) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3914,7 +3914,7 @@ SEM_FN_NAME (fr30bf,bged) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)))) { { USI opval = FLD (i_label9); @@ -3923,7 +3923,7 @@ if (NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)))) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -3970,7 +3970,7 @@ SEM_FN_NAME (fr30bf,bled) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit))) { { USI opval = FLD (i_label9); @@ -3979,7 +3979,7 @@ if (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit))) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -4026,7 +4026,7 @@ SEM_FN_NAME (fr30bf,bgtd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)))) { { USI opval = FLD (i_label9); @@ -4035,7 +4035,7 @@ if (NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)))) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -4082,7 +4082,7 @@ SEM_FN_NAME (fr30bf,blsd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (ORBI (CPU (h_cbit), CPU (h_zbit))) { { USI opval = FLD (i_label9); @@ -4091,7 +4091,7 @@ if (ORBI (CPU (h_cbit), CPU (h_zbit))) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -4138,7 +4138,7 @@ SEM_FN_NAME (fr30bf,bhid) (SIM_CPU *current_cpu, SEM_ARG sem_arg) SEM_BRANCH_INIT SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) { { USI opval = FLD (i_label9); @@ -4147,7 +4147,7 @@ if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) { TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } } -} while (0); +} abuf->written = written; SEM_BRANCH_FINI (vpc); @@ -4256,7 +4256,7 @@ SEM_FN_NAME (fr30bf,dmovr13pi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 13)])); SETMEMSI (current_cpu, pc, FLD (f_dir10), opval); @@ -4267,7 +4267,7 @@ do { CPU (h_gr[((UINT) 13)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -4284,7 +4284,7 @@ SEM_FN_NAME (fr30bf,dmovr13pih) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { HI opval = GETMEMHI (current_cpu, pc, CPU (h_gr[((UINT) 13)])); SETMEMHI (current_cpu, pc, FLD (f_dir9), opval); @@ -4295,7 +4295,7 @@ do { CPU (h_gr[((UINT) 13)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -4312,7 +4312,7 @@ SEM_FN_NAME (fr30bf,dmovr13pib) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { QI opval = GETMEMQI (current_cpu, pc, CPU (h_gr[((UINT) 13)])); SETMEMQI (current_cpu, pc, FLD (f_dir8), opval); @@ -4323,7 +4323,7 @@ do { CPU (h_gr[((UINT) 13)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -4340,7 +4340,7 @@ SEM_FN_NAME (fr30bf,dmovr15pi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); SETMEMSI (current_cpu, pc, FLD (f_dir10), opval); @@ -4351,7 +4351,7 @@ do { CPU (h_gr[((UINT) 15)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -4431,7 +4431,7 @@ SEM_FN_NAME (fr30bf,dmov2r13pi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = GETMEMSI (current_cpu, pc, FLD (f_dir10)); SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 13)]), opval); @@ -4442,7 +4442,7 @@ do { CPU (h_gr[((UINT) 13)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -4459,7 +4459,7 @@ SEM_FN_NAME (fr30bf,dmov2r13pih) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { HI opval = GETMEMHI (current_cpu, pc, FLD (f_dir9)); SETMEMHI (current_cpu, pc, CPU (h_gr[((UINT) 13)]), opval); @@ -4470,7 +4470,7 @@ do { CPU (h_gr[((UINT) 13)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -4487,7 +4487,7 @@ SEM_FN_NAME (fr30bf,dmov2r13pib) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { QI opval = GETMEMQI (current_cpu, pc, FLD (f_dir8)); SETMEMQI (current_cpu, pc, CPU (h_gr[((UINT) 13)]), opval); @@ -4498,7 +4498,7 @@ do { CPU (h_gr[((UINT) 13)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -4515,7 +4515,7 @@ SEM_FN_NAME (fr30bf,dmov2r15pd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -4526,7 +4526,7 @@ do { SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -4838,9 +4838,9 @@ SEM_FN_NAME (fr30bf,ldm0) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (ANDSI (FLD (f_reglist_low_ld), 1)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 0)]) = opval; @@ -4853,10 +4853,10 @@ do { written |= (1 << 5); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_ld), 2)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 1)]) = opval; @@ -4869,10 +4869,10 @@ do { written |= (1 << 5); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_ld), 4)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 2)]) = opval; @@ -4885,10 +4885,10 @@ do { written |= (1 << 5); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_ld), 8)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 3)]) = opval; @@ -4901,10 +4901,10 @@ do { written |= (1 << 5); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_ld), 16)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 4)]) = opval; @@ -4917,10 +4917,10 @@ do { written |= (1 << 5); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_ld), 32)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 5)]) = opval; @@ -4933,10 +4933,10 @@ do { written |= (1 << 5); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_ld), 64)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 6)]) = opval; @@ -4949,10 +4949,10 @@ do { written |= (1 << 5); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_ld), 128)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 7)]) = opval; @@ -4965,9 +4965,9 @@ do { written |= (1 << 5); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); } -} while (0); +} +} abuf->written = written; return vpc; @@ -4985,9 +4985,9 @@ SEM_FN_NAME (fr30bf,ldm1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (ANDSI (FLD (f_reglist_hi_ld), 1)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 8)]) = opval; @@ -5000,10 +5000,10 @@ do { written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_ld), 2)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 9)]) = opval; @@ -5016,10 +5016,10 @@ do { written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_ld), 4)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 10)]) = opval; @@ -5032,10 +5032,10 @@ do { written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_ld), 8)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 11)]) = opval; @@ -5048,10 +5048,10 @@ do { written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_ld), 16)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 12)]) = opval; @@ -5064,10 +5064,10 @@ do { written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_ld), 32)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 13)]) = opval; @@ -5080,10 +5080,10 @@ do { written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_ld), 64)) { -do { +{ { SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)])); CPU (h_gr[((UINT) 14)]) = opval; @@ -5096,7 +5096,7 @@ do { written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_ld), 128)) { { @@ -5106,7 +5106,7 @@ if (ANDSI (FLD (f_reglist_hi_ld), 128)) { TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } } -} while (0); +} abuf->written = written; return vpc; @@ -5124,9 +5124,9 @@ SEM_FN_NAME (fr30bf,stm0) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (ANDSI (FLD (f_reglist_low_st), 1)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5139,10 +5139,10 @@ do { written |= (1 << 11); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_st), 2)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5155,10 +5155,10 @@ do { written |= (1 << 11); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_st), 4)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5171,10 +5171,10 @@ do { written |= (1 << 11); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_st), 8)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5187,10 +5187,10 @@ do { written |= (1 << 11); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_st), 16)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5203,10 +5203,10 @@ do { written |= (1 << 11); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_st), 32)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5219,10 +5219,10 @@ do { written |= (1 << 11); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_st), 64)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5235,10 +5235,10 @@ do { written |= (1 << 11); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_low_st), 128)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5251,9 +5251,9 @@ do { written |= (1 << 11); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); } -} while (0); +} +} abuf->written = written; return vpc; @@ -5271,9 +5271,9 @@ SEM_FN_NAME (fr30bf,stm1) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ if (ANDSI (FLD (f_reglist_hi_st), 1)) { -do { +{ SI tmp_save_r15; tmp_save_r15 = CPU (h_gr[((UINT) 15)]); { @@ -5288,10 +5288,10 @@ do { written |= (1 << 10); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_st), 2)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5304,10 +5304,10 @@ do { written |= (1 << 10); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_st), 4)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5320,10 +5320,10 @@ do { written |= (1 << 10); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_st), 8)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5336,10 +5336,10 @@ do { written |= (1 << 10); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_st), 16)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5352,10 +5352,10 @@ do { written |= (1 << 10); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_st), 32)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5368,10 +5368,10 @@ do { written |= (1 << 10); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_st), 64)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5384,10 +5384,10 @@ do { written |= (1 << 10); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} } if (ANDSI (FLD (f_reglist_hi_st), 128)) { -do { +{ { SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5400,9 +5400,9 @@ do { written |= (1 << 10); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); } -} while (0); +} +} abuf->written = written; return vpc; @@ -5420,7 +5420,7 @@ SEM_FN_NAME (fr30bf,enter) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; tmp_tmp = SUBSI (CPU (h_gr[((UINT) 15)]), 4); { @@ -5438,7 +5438,7 @@ do { CPU (h_gr[((UINT) 15)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -5455,7 +5455,7 @@ SEM_FN_NAME (fr30bf,leave) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ { SI opval = ADDSI (CPU (h_gr[((UINT) 14)]), 4); CPU (h_gr[((UINT) 15)]) = opval; @@ -5466,7 +5466,7 @@ do { CPU (h_gr[((UINT) 14)]) = opval; TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval); } -} while (0); +} return vpc; #undef FLD @@ -5483,7 +5483,7 @@ SEM_FN_NAME (fr30bf,xchb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); -do { +{ SI tmp_tmp; tmp_tmp = * FLD (i_Ri); { @@ -5496,7 +5496,7 @@ do { SETMEMUQI (current_cpu, pc, * FLD (i_Rj), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } -} while (0); +} return vpc; #undef FLD diff --git a/sim/fr30/sim-if.c b/sim/fr30/sim-if.c index 5df0f83..28b344d 100644 --- a/sim/fr30/sim-if.c +++ b/sim/fr30/sim-if.c @@ -143,8 +143,8 @@ sim_open (kind, callback, abfd, argv) /* Open a copy of the cpu descriptor table. */ { - CGEN_CPU_DESC cd = fr30_cgen_cpu_open (STATE_ARCHITECTURE (sd)->mach, - CGEN_ENDIAN_BIG); + CGEN_CPU_DESC cd = fr30_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name, + CGEN_ENDIAN_BIG); for (i = 0; i < MAX_NR_PROCESSORS; ++i) { SIM_CPU *cpu = STATE_CPU (sd, i); diff --git a/sim/fr30/traps.c b/sim/fr30/traps.c index 599bca2..11f7a30 100644 --- a/sim/fr30/traps.c +++ b/sim/fr30/traps.c @@ -104,15 +104,15 @@ syscall_write_mem (host_callback *cb, struct cb_syscall *sc, static void setup_int (SIM_CPU *current_cpu, PCADDR pc) { - USI ssp = a_fr30_h_dr_get (current_cpu, H_DR_SSP); - USI ps = a_fr30_h_ps_get (current_cpu); + USI ssp = fr30bf_h_dr_get (current_cpu, H_DR_SSP); + USI ps = fr30bf_h_ps_get (current_cpu); ssp -= 4; SETMEMSI (current_cpu, pc, ssp, ps); ssp -= 4; SETMEMSI (current_cpu, pc, ssp, pc + 2); - a_fr30_h_dr_set (current_cpu, H_DR_SSP, ssp); - a_fr30_h_sbit_set (current_cpu, 0); + fr30bf_h_dr_set (current_cpu, H_DR_SSP, ssp); + fr30bf_h_sbit_set (current_cpu, 0); } /* Trap support. @@ -143,9 +143,9 @@ fr30_int (SIM_CPU *current_cpu, PCADDR pc, int num) We assume there's a branch there to some handler. */ USI new_pc; setup_int (current_cpu, pc); - a_fr30_h_ibit_set (current_cpu, 0); + fr30bf_h_ibit_set (current_cpu, 0); new_pc = GETMEMSI (current_cpu, pc, - a_fr30_h_dr_get (current_cpu, H_DR_TBR) + fr30bf_h_dr_get (current_cpu, H_DR_TBR) + 1024 - ((num + 1) * 4)); return new_pc; } @@ -158,10 +158,10 @@ fr30_int (SIM_CPU *current_cpu, PCADDR pc, int num) CB_SYSCALL s; CB_SYSCALL_INIT (&s); - s.func = a_fr30_h_gr_get (current_cpu, 0); - s.arg1 = a_fr30_h_gr_get (current_cpu, 4); - s.arg2 = a_fr30_h_gr_get (current_cpu, 5); - s.arg3 = a_fr30_h_gr_get (current_cpu, 6); + s.func = fr30bf_h_gr_get (current_cpu, 0); + s.arg1 = fr30bf_h_gr_get (current_cpu, 4); + s.arg2 = fr30bf_h_gr_get (current_cpu, 5); + s.arg3 = fr30bf_h_gr_get (current_cpu, 6); if (s.func == TARGET_SYS_exit) { @@ -173,9 +173,9 @@ fr30_int (SIM_CPU *current_cpu, PCADDR pc, int num) s.read_mem = syscall_read_mem; s.write_mem = syscall_write_mem; cb_syscall (cb, &s); - a_fr30_h_gr_set (current_cpu, 2, s.errcode); /* TODO: check this one */ - a_fr30_h_gr_set (current_cpu, 4, s.result); - a_fr30_h_gr_set (current_cpu, 1, s.result2); /* TODO: check this one */ + fr30bf_h_gr_set (current_cpu, 2, s.errcode); /* TODO: check this one */ + fr30bf_h_gr_set (current_cpu, 4, s.result); + fr30bf_h_gr_set (current_cpu, 1, s.result2); /* TODO: check this one */ break; } @@ -188,9 +188,9 @@ fr30_int (SIM_CPU *current_cpu, PCADDR pc, int num) { USI new_pc; setup_int (current_cpu, pc); - a_fr30_h_ibit_set (current_cpu, 0); + fr30bf_h_ibit_set (current_cpu, 0); new_pc = GETMEMSI (current_cpu, pc, - a_fr30_h_dr_get (current_cpu, H_DR_TBR) + fr30bf_h_dr_get (current_cpu, H_DR_TBR) + 1024 - ((num + 1) * 4)); return new_pc; } @@ -209,9 +209,9 @@ fr30_inte (SIM_CPU *current_cpu, PCADDR pc, int num) We assume there's a branch there to some handler. */ USI new_pc; setup_int (current_cpu, pc); - a_fr30_h_ilm_set (current_cpu, 4); + fr30bf_h_ilm_set (current_cpu, 4); new_pc = GETMEMSI (current_cpu, pc, - a_fr30_h_dr_get (current_cpu, H_DR_TBR) + fr30bf_h_dr_get (current_cpu, H_DR_TBR) + 1024 - ((9 + 1) * 4)); return new_pc; } |