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author | Jiri Gaisler <jiri@gaisler.se> | 2015-04-03 22:35:48 +0200 |
---|---|---|
committer | Mike Frysinger <vapier@gentoo.org> | 2015-04-19 02:29:44 -0400 |
commit | d3e9b40afb8e7bd09522044951cdce4710676c3e (patch) | |
tree | 23020a66ff49d500c422b506c5891c998089e64b /sim/erc32/interf.c | |
parent | 09b29ece9abb652983d4718aac0ff666d62d6790 (diff) | |
download | gdb-d3e9b40afb8e7bd09522044951cdce4710676c3e.zip gdb-d3e9b40afb8e7bd09522044951cdce4710676c3e.tar.gz gdb-d3e9b40afb8e7bd09522044951cdce4710676c3e.tar.bz2 |
sim/erc32: Switched emulated memory to host endian order.
Change data ordering in emulated memory from target order (big endian)
to host order. Improves performance and simplifies most memory
operations. Requires some byte twisting during stores on little
endian hosts (intel). Also removed support for little-endian binaries.
Diffstat (limited to 'sim/erc32/interf.c')
-rw-r--r-- | sim/erc32/interf.c | 39 |
1 files changed, 20 insertions, 19 deletions
diff --git a/sim/erc32/interf.c b/sim/erc32/interf.c index 59fb635..235af8b 100644 --- a/sim/erc32/interf.c +++ b/sim/erc32/interf.c @@ -40,7 +40,6 @@ extern struct disassemble_info dinfo; extern struct pstate sregs; extern struct estate ebase; -extern int current_target_byte_order; extern int ctrl_c; extern int nfp; extern int ift; @@ -252,7 +251,11 @@ sim_open (kind, callback, abfd, argv) sregs.freq = freq ? freq : 15; termsave = fcntl(0, F_GETFL, 0); INIT_DISASSEMBLE_INFO(dinfo, stdout,(fprintf_ftype)fprintf); +#ifdef HOST_LITTLE_ENDIAN + dinfo.endian = BFD_ENDIAN_LITTLE; +#else dinfo.endian = BFD_ENDIAN_BIG; +#endif reset_all(); ebase.simtime = 0; init_sim(); @@ -311,14 +314,10 @@ sim_store_register(sd, regno, value, length) unsigned char *value; int length; { - /* FIXME: Review the computation of regval. */ int regval; - if (current_target_byte_order == BIG_ENDIAN) - regval = (value[0] << 24) | (value[1] << 16) + + regval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3]; - else - regval = (value[3] << 24) | (value[2] << 16) - | (value[1] << 8) | value[0]; set_regi(&sregs, regno, regval); return length; } @@ -336,23 +335,25 @@ sim_fetch_register(sd, regno, buf, length) } int -sim_write(sd, mem, buf, length) - SIM_DESC sd; - SIM_ADDR mem; - const unsigned char *buf; - int length; +sim_write (SIM_DESC sd, SIM_ADDR mem, const unsigned char *buf, int length) { - return sis_memory_write (mem, buf, length); + int i, len; + + for (i = 0; i < length; i++) { + sis_memory_write ((mem + i) ^ EBT, &buf[i], 1); + } + return length; } int -sim_read(sd, mem, buf, length) - SIM_DESC sd; - SIM_ADDR mem; - unsigned char *buf; - int length; +sim_read (SIM_DESC sd, SIM_ADDR mem, unsigned char *buf, int length) { - return sis_memory_read (mem, buf, length); + int i, len; + + for (i = 0; i < length; i++) { + sis_memory_read ((mem + i) ^ EBT, &buf[i], 1); + } + return length; } void |