import gdb-19990422 snapshot

5 files changed, 25 insertions, 7 deletions

diff --git a/sim/d30v/ChangeLog b/sim/d30v/ChangeLog
index 668d89e..7687595 100644
--- a/sim/d30v/ChangeLog
+++ b/sim/d30v/ChangeLog
@@ -1,3 +1,16 @@
+1999-03-16  Martin Hunt  <hunt@cygnus.com>
+	From Frank Ch. Eigler  <fche@cygnus.com>
+
+        * cpu.h (mvtsys_left_p): New flag for MVTSYS instruction history.
+        * d30v-insns (mvtsys): Set this flag instead of left_kills_right_p.
+        (do_sath): Detect MVTSYS by new flag.
+        * engine.c (unqueue_writes): Detect MVTSYS by new flag.
+        (do_2_short, do_parallel): Initialize new flag.
+       
+1999-02-26  Frank Ch. Eigler  <fche@cygnus.com>
+
+	* tconfig.in (SIM_HANDLES_LMA): Make it so.
+
 1999-01-12  Frank Ch. Eigler  <fche@cygnus.com>
 
 	* engine.c (unqueue_writes): Make PSW conflict resolution code
diff --git a/sim/d30v/cpu.h b/sim/d30v/cpu.h
index 6190e61..d24a4ac 100644
--- a/sim/d30v/cpu.h
+++ b/sim/d30v/cpu.h
@@ -115,6 +115,7 @@ struct _sim_cpu {
   int trace_trap_p;			/* If unknown traps dump out the regs */
   int trace_action;			/* trace bits at end of instructions */
   int left_kills_right_p;               /* left insn kills insn in right slot of -> */
+  int mvtsys_left_p;			/* left insn was mvtsys */
   int did_trap;				/* we did a trap & need to finish it */
   struct _write32 write32;		/* queued up 32-bit writes */
   struct _write64 write64;		/* queued up 64-bit writes */
diff --git a/sim/d30v/d30v-insns b/sim/d30v/d30v-insns
index 6dc4f6b..5b34e80 100644
--- a/sim/d30v/d30v-insns
+++ b/sim/d30v/d30v-insns
@@ -1520,11 +1520,11 @@ _BRA,01110,00,6.CR,6.RB,6.ID:BRA:short:mu:MVTSYS
 	  else
 	    {
 	      unsigned32 value = Rb;
+	      CPU->mvtsys_left_p = 1;
 	      if (CR == processor_status_word_cr)
 		{
 		  unsigned32 ds = PSW & BIT32 (PSW_DS);	/* preserve ds */
 		  value = ds | (value & PSW_VALID);
-		  CPU->left_kills_right_p = 1;
 		}
 	      else if (CR == backup_processor_status_word_cr
 		       || CR == debug_backup_processor_status_word_cr)
@@ -1537,19 +1537,16 @@ _BRA,01110,00,6.CR,6.RB,6.ID:BRA:short:mu:MVTSYS
 	case 1:			/* PSWL */
 	  WRITE32_QUEUE_MASK (&PSW, EXTRACTED32(Rb, 16, 31),
 			      PSW_VALID & 0x0000ffff);
-	  CPU->left_kills_right_p = 1;
 	  break;
 	case 2:			/* PSWH */
 	  {
 	    unsigned32 ds = PSW & BIT32 (PSW_DS);	/* preserve ds */
 	    WRITE32_QUEUE_MASK (&PSW, (EXTRACTED32(Rb, 16, 31) << 16) | ds,
 				(PSW_VALID | ds) & 0xffff0000);
-	    CPU->left_kills_right_p = 1;
 	  }
 	  break;
 	case 3:			/* FLAG */
 	  PSW_FLAG_SET_QUEUE(CR, Rb & 1);
-	  CPU->left_kills_right_p = 1;
 	  break;
 	default:
 	  sim_engine_abort (SD, CPU, cia, "FIXME - illegal ID");
@@ -1745,7 +1742,7 @@ void::function::do_sath:signed32 *ra, signed32 rb, signed32 src, int high, int u
 	if (updates_f4)
 	  {
 	    /* if MU instruction was a MVTSYS (lkr), unqueue register writes now */
-	    if(STATE_CPU (sd, 0)->left_kills_right_p)
+	    if(STATE_CPU (sd, 0)->mvtsys_left_p)
 	      unqueue_writes (sd, STATE_CPU (sd, 0), cia);
 	    PSW_FLAG_SET_QUEUE(PSW_S_FLAG, PSW_FLAG_VAL(PSW_S_FLAG) ^ (value & 1));
 	  }
diff --git a/sim/d30v/engine.c b/sim/d30v/engine.c
index 402a2f5..2bbaad1 100644
--- a/sim/d30v/engine.c
+++ b/sim/d30v/engine.c
@@ -134,9 +134,9 @@ unqueue_writes (SIM_DESC sd,
 
       if (ptr == psw_addr)
        {
-	  /* If MU instruction was not a MVTSYS (lkr), resolve PSW
+	 /* If MU instruction was not a MVTSYS, resolve PSW
              contention in favour of IU. */
-	  if(! STATE_CPU (sd, 0)->left_kills_right_p)
+	  if(! STATE_CPU (sd, 0)->mvtsys_left_p)
 	    {
 	      /* Detect contention in parallel writes to the same PSW flags.
 		 The hardware allows the updates from IU to prevail over
@@ -249,6 +249,7 @@ do_2_short (SIM_DESC sd,
   /* run the first instruction */
   STATE_CPU (sd, 0)->unit = unit;
   STATE_CPU (sd, 0)->left_kills_right_p = 0;
+  STATE_CPU (sd, 0)->mvtsys_left_p = 0;
   nia = s_idecode_issue(sd,
 			insn1,
 			cia);
@@ -267,6 +268,7 @@ do_2_short (SIM_DESC sd,
   }
 
   STATE_CPU (sd, 0)->left_kills_right_p = 0;
+  STATE_CPU (sd, 0)->mvtsys_left_p = 0;
   return nia;
 }
 
@@ -283,6 +285,7 @@ do_parallel (SIM_DESC sd,
   /* run the first instruction */
   STATE_CPU (sd, 0)->unit = memory_unit;
   STATE_CPU (sd, 0)->left_kills_right_p = 0;
+  STATE_CPU (sd, 0)->mvtsys_left_p = 0;
   nia_left = s_idecode_issue(sd,
 			     left_insn,
 			     cia);
diff --git a/sim/d30v/tconfig.in b/sim/d30v/tconfig.in
index c742b36..4efbb91 100644
--- a/sim/d30v/tconfig.in
+++ b/sim/d30v/tconfig.in
@@ -2,3 +2,7 @@
 
 /* Define this to enable the intrinsic breakpoint mechanism. */
 #define SIM_HAVE_BREAKPOINTS
+
+/* See sim-hload.c.  We properly handle LMA. */
+#define SIM_HANDLES_LMA 1
+