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author | Jason Molenda <jmolenda@apple.com> | 1999-09-22 03:28:34 +0000 |
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committer | Jason Molenda <jmolenda@apple.com> | 1999-09-22 03:28:34 +0000 |
commit | c2c6d25f0d5eea4f834420870021a8c52db24018 (patch) | |
tree | f4b3d5e9e3207fa8118db4085f9c6a0cbc2bdaf6 /sim/d10v | |
parent | 54af6ff67571ba569b94e26d558d02f9955e6844 (diff) | |
download | gdb-c2c6d25f0d5eea4f834420870021a8c52db24018.zip gdb-c2c6d25f0d5eea4f834420870021a8c52db24018.tar.gz gdb-c2c6d25f0d5eea4f834420870021a8c52db24018.tar.bz2 |
import gdb-1999-09-21
Diffstat (limited to 'sim/d10v')
-rw-r--r-- | sim/d10v/ChangeLog | 4 | ||||
-rw-r--r-- | sim/d10v/simops.c | 8 |
2 files changed, 5 insertions, 7 deletions
diff --git a/sim/d10v/ChangeLog b/sim/d10v/ChangeLog index 0695db2..6fa21b1 100644 --- a/sim/d10v/ChangeLog +++ b/sim/d10v/ChangeLog @@ -1,3 +1,7 @@ +1999-09-14 Nick Clifton <nickc@cygnus.com> + + * simops.c: Disable setting of DM bit in PSW. + Wed Sep 8 19:34:55 MDT 1999 Diego Novillo <dnovillo@cygnus.com> * simops.c (op_types): Added new memory indirect type OP_MEMREF3. diff --git a/sim/d10v/simops.c b/sim/d10v/simops.c index 22bdd91..9d77943 100644 --- a/sim/d10v/simops.c +++ b/sim/d10v/simops.c @@ -48,7 +48,6 @@ enum { PSW_MASK = (PSW_SM_BIT | PSW_EA_BIT | PSW_DB_BIT - | PSW_DM_BIT | PSW_IE_BIT | PSW_RP_BIT | PSW_MD_BIT @@ -1097,7 +1096,7 @@ OP_5F20 () trace_input ("dbt", OP_VOID, OP_VOID, OP_VOID); SET_DPC (PC + 1); SET_DPSW (PSW); - SET_PSW (PSW_DM_BIT | (PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT))); + SET_PSW (PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT)); JMP (DBT_VECTOR_START); trace_output_void (); } @@ -2242,7 +2241,6 @@ OP_5F40 () trace_output_void (); } - /* sac */ void OP_5209 () { @@ -2275,7 +2273,6 @@ void OP_5209 () trace_output_40 (tmp); } - /* sachi */ void OP_4209 () @@ -2309,7 +2306,6 @@ OP_4209 () trace_output_16 (OP[0]); } - /* sadd */ void OP_1223 () @@ -2407,7 +2403,6 @@ OP_3220 () trace_output_40(tmp); } - /* sleep */ void OP_5FC0 () @@ -3428,4 +3423,3 @@ OP_5000000 () SET_GPR (OP[0], tmp); trace_output_16 (tmp); } - |