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author | Andrew Cagney <cagney@redhat.com> | 1998-02-16 00:35:57 +0000 |
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committer | Andrew Cagney <cagney@redhat.com> | 1998-02-16 00:35:57 +0000 |
commit | 729295b597c6afa78c1241e7ccbe2a15041d36be (patch) | |
tree | a99b069d25cb4b1e4dad242787bd81adb3688040 /sim/d10v | |
parent | b104806fd3d786560fcb451fb7c8a46a95f0fc79 (diff) | |
download | gdb-729295b597c6afa78c1241e7ccbe2a15041d36be.zip gdb-729295b597c6afa78c1241e7ccbe2a15041d36be.tar.gz gdb-729295b597c6afa78c1241e7ccbe2a15041d36be.tar.bz2 |
Implement "dbt" and "rtd" instructions.
Import fixes to dmap_addr() from mitsu branch.
Diffstat (limited to 'sim/d10v')
-rw-r--r-- | sim/d10v/ChangeLog | 15 | ||||
-rw-r--r-- | sim/d10v/interp.c | 40 |
2 files changed, 40 insertions, 15 deletions
diff --git a/sim/d10v/ChangeLog b/sim/d10v/ChangeLog index 7c884fb..ca21f30 100644 --- a/sim/d10v/ChangeLog +++ b/sim/d10v/ChangeLog @@ -1,3 +1,18 @@ +Mon Oct 27 14:43:33 1997 Fred Fish <fnf@cygnus.com> + + * (dmem_addr): If address is illegal or in I/O space, signal a bus + error. Allocate unified memory on demand. Fix DMEM address + calculations. + +Mon Feb 16 10:27:53 1998 Andrew Cagney <cagney@b1.cygnus.com> + + * simops.c (OP_5F20): Implement "dbt". + (OP_5F60): Implement "rtd". + + * d10v_sim.h (DPC_CR): Define enum. + (DBT_VECTOR_START): Define + (DPSW, DPC): Define. + Fri Feb 13 15:15:58 1998 Andrew Cagney <cagney@b1.cygnus.com> * simops.c (move_to_cr): Sync regs[SP_IDX] with State.sp according diff --git a/sim/d10v/interp.c b/sim/d10v/interp.c index 008894b..ad6e920 100644 --- a/sim/d10v/interp.c +++ b/sim/d10v/interp.c @@ -627,21 +627,31 @@ dmem_addr( addr ) if (DMAP & 0x1000) { /* instruction memory */ - return (DMAP & 0xf) * 0x4000 + State.imem; + return (DMAP & 0xf) * 0x4000 + State.imem + (addr - 0x8000); } - /* unified memory */ - /* this is ugly because we allocate unified memory in 128K segments and */ - /* dmap addresses 16k segments */ - seg = (DMAP & 0x3ff) >> 3; - if (State.umem[seg] == NULL) + else { - (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: unified memory region %d unmapped, pc = 0x%lx\n", - seg, (long)decode_pc ()); - State.exception = SIGBUS; + /* unified memory */ + /* this is ugly because we allocate unified memory in 128K segments and */ + /* dmap addresses 16k segments */ + seg = (DMAP & 0x3ff) >> 3; + if (State.umem[seg] == NULL) + { +#ifdef DEBUG + (*d10v_callback->printf_filtered) (d10v_callback,"Allocating %d bytes unified memory to region %d\n", 1<<UMEM_SIZE, seg); +#endif + State.umem[seg] = (uint8 *)calloc(1,1<<UMEM_SIZE); + if (!State.umem[seg]) + { + (*d10v_callback->printf_filtered) (d10v_callback, + "ERROR: alloc failed. unified memory region %d unmapped, pc = 0x%lx\n", + seg, (long)decode_pc ()); + State.exception = SIGBUS; + } + } + return State.umem[seg] + (DMAP & 7) * 0x4000 + (addr - 0x8000); } - return State.umem[seg] + (DMAP & 7) * 0x4000; } - return State.dmem + addr; } @@ -903,13 +913,13 @@ sim_create_inferior (sd, abfd, argv, env) { /* a hack to set r0/r1 with argc/argv */ /* some high memory that won't be overwritten by the stack soon */ - addr = State.regs[0] = 0x7C00; - p = 20; - i = 0; + bfd_vma addr = State.regs[0] = 0x7C00; + int p = 20; + int i = 0; while (argv[i]) { + int size = strlen (argv[i]) + 1; SW (addr + 2*i, addr + p); - size = strlen (argv[i]) + 1; sim_write (sd, addr + 0, argv[i], size); p += size; i++; |