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| author | Michael Meissner <gnu@the-meissners.org> | 1996-09-09 17:30:36 +0000 |
|---|---|---|
| committer | Michael Meissner <gnu@the-meissners.org> | 1996-09-09 17:30:36 +0000 |
| commit | 069398aaffc69e5930a29d6f55c6e9cac8f8fa37 (patch) | |
| tree | 8f0d4ee9ea3fe781018545d19057fd152254001d /sim/d10v | |
| parent | 517078c1b3b9e11fba127f6d9b5dd1ea08ca9d05 (diff) | |
| download | gdb-069398aaffc69e5930a29d6f55c6e9cac8f8fa37.zip gdb-069398aaffc69e5930a29d6f55c6e9cac8f8fa37.tar.gz gdb-069398aaffc69e5930a29d6f55c6e9cac8f8fa37.tar.bz2 | |
Fix accumulator shifts
Diffstat (limited to 'sim/d10v')
| -rw-r--r-- | sim/d10v/ChangeLog | 6 | ||||
| -rw-r--r-- | sim/d10v/simops.c | 30 |
2 files changed, 31 insertions, 5 deletions
diff --git a/sim/d10v/ChangeLog b/sim/d10v/ChangeLog index 57f9f1a..9703ca1 100644 --- a/sim/d10v/ChangeLog +++ b/sim/d10v/ChangeLog @@ -1,3 +1,9 @@ +Mon Sep 9 13:27:26 1996 Michael Meissner <meissner@tiktok.cygnus.com> + + * simops.c (trace_output): Properly align accumulator output. + (OP_3{0,2,4}00): Properly parenthesize test expression. Add error + if shift count is too high. + Fri Sep 6 17:56:17 1996 Martin M. Hunt <hunt@pizza.cygnus.com> * simops.c (OP_2600, OP_2601): Changed min and max comparisons diff --git a/sim/d10v/simops.c b/sim/d10v/simops.c index dc05f5e..6b8329b 100644 --- a/sim/d10v/simops.c +++ b/sim/d10v/simops.c @@ -325,14 +325,14 @@ trace_output (result) case OP_ACCUM: case OP_ACCUM_OUTPUT: - (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", + (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "", ((int)(State.a[OP[0]] >> 32) & 0xff), ((unsigned long)State.a[OP[0]]) & 0xffffffff, State.F0 != 0, State.F1 != 0, State.C != 0); break; case OP_ACCUM_REVERSE: - (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", + (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "", ((int)(State.a[OP[1]] >> 32) & 0xff), ((unsigned long)State.a[OP[1]]) & 0xffffffff, State.F0 != 0, State.F1 != 0, State.C != 0); @@ -1913,8 +1913,14 @@ OP_3200 () { int64 tmp; trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID); - if (State.regs[OP[1]] & 31 <= 16) + if ((State.regs[OP[1]] & 31) <= 16) tmp = SEXT40 (State.a[OP[0]]) << (State.regs[OP[1]] & 31); + else + { + (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31); + State.exception = SIGILL; + return; + } if (State.ST) { @@ -1990,8 +1996,15 @@ void OP_3400 () { trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID); - if (State.regs[OP[1]] & 31 <= 16) + if ((State.regs[OP[1]] & 31) <= 16) State.a[OP[0]] >>= (State.regs[OP[1]] & 31); + else + { + (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31); + State.exception = SIGILL; + return; + } + trace_output (OP_ACCUM); } @@ -2030,8 +2043,15 @@ void OP_3000 () { trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID); - if (State.regs[OP[1]] & 31 <= 16) + if ((State.regs[OP[1]] & 31) <= 16) State.a[OP[0]] >>= (State.regs[OP[1]] & 31); + else + { + (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31); + State.exception = SIGILL; + return; + } + trace_output (OP_ACCUM); } |