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authorMike Frysinger <vapier@gentoo.org>2015-11-15 02:57:42 -0800
committerMike Frysinger <vapier@gentoo.org>2015-11-15 20:47:03 -0500
commit679546067e1f3e1617bff22d03e483fb2beeed24 (patch)
tree1cf4ce63f612fb30be3ab13bdd657b44f2b46bed /sim/d10v
parenta572cc6fd43e90e28e828c6bdaa344c1ef6a75ab (diff)
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sim: d10v: push down sd/cpu vars
By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
Diffstat (limited to 'sim/d10v')
-rw-r--r--sim/d10v/ChangeLog25
-rw-r--r--sim/d10v/d10v_sim.h24
-rw-r--r--sim/d10v/endian.c2
-rw-r--r--sim/d10v/gencode.c8
-rw-r--r--sim/d10v/interp.c183
-rw-r--r--sim/d10v/simops.c801
6 files changed, 543 insertions, 500 deletions
diff --git a/sim/d10v/ChangeLog b/sim/d10v/ChangeLog
index 4f22db7..2db4312 100644
--- a/sim/d10v/ChangeLog
+++ b/sim/d10v/ChangeLog
@@ -1,3 +1,28 @@
+2015-11-15 Mike Frysinger <vapier@gentoo.org>
+
+ * d10v_sim.h (struct simops): Add SIM_DESC and SIM_CPU to func args.
+ (SET_CREG, SET_HW_CREG, SET_PSW_BIT): Pass sd and cpu to move_to_cr.
+ (dmem_addr, imem_addr, move_to_cr): Add SIM_DESC and SIM_CPU args.
+ (RB, SW, RW, SLW, RLW): Pass sd and cpu to dmem_addr.
+ * endian.c: Change d10v_sim.h include to sim-main.h.
+ * gencode.c: Likewise. Add SIM_DESC and SIM_CPU args to all OPs.
+ * interp.c (lookup_hash, do_long, do_2_short, do_parallel,
+ map_memory, set_dmap_register, dmap_register, set_imap_register,
+ imap_register, sim_d10v_translate_dmap_addr, xfer_mem,
+ sim_d10v_translate_imap_addr, sim_d10v_translate_addr): Add
+ SIM_DESC and SIM_CPU args and adjust all callers.
+ (trace_sd): Delete.
+ (sim_open): Do not assign trace_sd.
+ (sim_resume, sim_create_inferior, sim_fetch_register,
+ sim_store_register): Set up cpu from the first one in sd.
+ * simops.c (move_to_cr): Add SIM_DESC and SIM_CPU args.
+ (trace_input_func, trace_input, do_trace_output_finish,
+ do_trace_output_finish, trace_output_40, trace_output_32,
+ trace_output_16, trace_output_void, trace_output_flag): Add
+ SIM_DESC arg.
+ (trace_input_func): Likewise. Change trace_sd to sd.
+ (OP_*): Add SIM_DESC and SIM_CPU args to all OP funcs.
+
2015-11-14 Mike Frysinger <vapier@gentoo.org>
* interp.c (sim_close): Delete.
diff --git a/sim/d10v/d10v_sim.h b/sim/d10v/d10v_sim.h
index 87f7d5f..ed2bbbb 100644
--- a/sim/d10v/d10v_sim.h
+++ b/sim/d10v/d10v_sim.h
@@ -45,7 +45,7 @@ struct simops
int cycles;
int unit;
int exec_type;
- void (*func)();
+ void (*func)(SIM_DESC, SIM_CPU *);
int numops;
int operands[9];
};
@@ -241,8 +241,8 @@ struct _state
reg_t cregs[16]; /* control registers */
#define CREG(N) (State.cregs[(N)] + 0)
-#define SET_CREG(N,VAL) move_to_cr ((N), 0, (VAL), 0)
-#define SET_HW_CREG(N,VAL) move_to_cr ((N), 0, (VAL), 1)
+#define SET_CREG(N,VAL) move_to_cr (sd, cpu, (N), 0, (VAL), 0)
+#define SET_HW_CREG(N,VAL) move_to_cr (sd, cpu, (N), 0, (VAL), 1)
reg_t sp[2]; /* holding area for SPI(0)/SPU(1) */
#define HELD_SP(N) (State.sp[(N)] + 0)
@@ -314,7 +314,7 @@ enum
#define PSW CREG (PSW_CR)
#define SET_PSW(VAL) SET_CREG (PSW_CR, (VAL))
#define SET_HW_PSW(VAL) SET_HW_CREG (PSW_CR, (VAL))
-#define SET_PSW_BIT(MASK,VAL) move_to_cr (PSW_CR, ~((reg_t) MASK), (VAL) ? (MASK) : 0, 1)
+#define SET_PSW_BIT(MASK,VAL) move_to_cr (sd, cpu, PSW_CR, ~((reg_t) MASK), (VAL) ? (MASK) : 0, 1)
#define PSW_SM ((PSW & PSW_SM_BIT) != 0)
#define SET_PSW_SM(VAL) SET_PSW_BIT (PSW_SM_BIT, (VAL))
@@ -443,11 +443,11 @@ do \
} \
while (0)
-extern uint8 *dmem_addr (uint16 offset);
-extern uint8 *imem_addr (uint32);
+extern uint8 *dmem_addr (SIM_DESC, SIM_CPU *, uint16 offset);
+extern uint8 *imem_addr (SIM_DESC, SIM_CPU *, uint32);
extern bfd_vma decode_pc (void);
-#define RB(x) (*(dmem_addr(x)))
+#define RB(x) (*(dmem_addr (sd, cpu, x)))
#define SB(addr,data) ( RB(addr) = (data & 0xff))
#if defined(__GNUC__) && defined(__OPTIMIZE__) && !defined(NO_ENDIAN_INLINE)
@@ -464,10 +464,10 @@ extern void write_longword (uint8 *addr, uint32 data);
extern void write_longlong (uint8 *addr, int64 data);
#endif
-#define SW(addr,data) write_word(dmem_addr(addr),data)
-#define RW(x) get_word(dmem_addr(x))
-#define SLW(addr,data) write_longword(dmem_addr(addr),data)
-#define RLW(x) get_longword(dmem_addr(x))
+#define SW(addr,data) write_word (dmem_addr (sd, cpu, addr), data)
+#define RW(x) get_word (dmem_addr (sd, cpu, x))
+#define SLW(addr,data) write_longword (dmem_addr (sd, cpu, addr), data)
+#define RLW(x) get_longword (dmem_addr (sd, cpu, x))
#define READ_16(x) get_word(x)
#define WRITE_16(addr,data) write_word(addr,data)
#define READ_64(x) get_longlong(x)
@@ -486,4 +486,4 @@ extern void write_longlong (uint8 *addr, int64 data);
(VAL & ~MASK)). In addition, unless PSW_HW_P, a VAL intended for
PSW is masked for zero bits. */
-extern reg_t move_to_cr (int cr, reg_t mask, reg_t val, int psw_hw_p);
+extern reg_t move_to_cr (SIM_DESC, SIM_CPU *, int cr, reg_t mask, reg_t val, int psw_hw_p);
diff --git a/sim/d10v/endian.c b/sim/d10v/endian.c
index e9fce7d..8d85bcb 100644
--- a/sim/d10v/endian.c
+++ b/sim/d10v/endian.c
@@ -3,7 +3,7 @@
#ifndef ENDIAN_INLINE
#define NO_ENDIAN_INLINE
-#include "d10v_sim.h"
+#include "sim-main.h"
#define ENDIAN_INLINE
#endif
diff --git a/sim/d10v/gencode.c b/sim/d10v/gencode.c
index 1728d8c..9f8a41c 100644
--- a/sim/d10v/gencode.c
+++ b/sim/d10v/gencode.c
@@ -30,7 +30,7 @@ write_header (void)
for (opcode = (struct d10v_opcode *)d10v_opcodes; opcode->name; opcode++)
if (opcode->format != OPCODE_FAKE)
- printf("void OP_%lX (void);\t\t/* %s */\n", opcode->opcode, opcode->name);
+ printf ("void OP_%lX (SIM_DESC, SIM_CPU *);\t\t/* %s */\n", opcode->opcode, opcode->name);
}
@@ -43,7 +43,7 @@ write_template (void)
struct d10v_opcode *opcode;
int i,j;
- printf ("#include \"d10v_sim.h\"\n");
+ printf ("#include \"sim-main.h\"\n");
printf ("#include \"simops.h\"\n");
for (opcode = (struct d10v_opcode *)d10v_opcodes; opcode->name; opcode++)
@@ -103,7 +103,7 @@ write_opcodes (void)
int i, j;
/* write out opcode table */
- printf ("#include \"d10v_sim.h\"\n");
+ printf ("#include \"sim-main.h\"\n");
printf ("#include \"simops.h\"\n\n");
printf ("struct simops Simops[] = {\n");
@@ -150,5 +150,5 @@ write_opcodes (void)
printf ("},\n");
}
}
- printf ("{ 0,0,0,0,0,0,0,(void (*)(void))0,0,{0,0,0}},\n};\n");
+ printf ("{ 0,0,0,0,0,0,0,(void (*)())0,0,{0,0,0}},\n};\n");
}
diff --git a/sim/d10v/interp.c b/sim/d10v/interp.c
index 1cb1d7c..df8b929 100644
--- a/sim/d10v/interp.c
+++ b/sim/d10v/interp.c
@@ -37,13 +37,13 @@ unsigned long ins_type_counters[ (int)INS_MAX ];
uint16 OP[4];
static long hash (long insn, int format);
-static struct hash_entry *lookup_hash (uint32 ins, int size);
+static struct hash_entry *lookup_hash (SIM_DESC, SIM_CPU *, uint32 ins, int size);
static void get_operands (struct simops *s, uint32 ins);
-static void do_long (uint32 ins);
-static void do_2_short (uint16 ins1, uint16 ins2, enum _leftright leftright);
-static void do_parallel (uint16 ins1, uint16 ins2);
+static void do_long (SIM_DESC, SIM_CPU *, uint32 ins);
+static void do_2_short (SIM_DESC, SIM_CPU *, uint16 ins1, uint16 ins2, enum _leftright leftright);
+static void do_parallel (SIM_DESC, SIM_CPU *, uint16 ins1, uint16 ins2);
static char *add_commas (char *buf, int sizeof_buf, unsigned long value);
-static INLINE uint8 *map_memory (unsigned phys_addr);
+static INLINE uint8 *map_memory (SIM_DESC, SIM_CPU *, unsigned phys_addr);
#define MAX_HASH 63
struct hash_entry
@@ -67,7 +67,7 @@ hash (long insn, int format)
}
INLINE static struct hash_entry *
-lookup_hash (uint32 ins, int size)
+lookup_hash (SIM_DESC sd, SIM_CPU *cpu, uint32 ins, int size)
{
struct hash_entry *h;
@@ -108,24 +108,24 @@ get_operands (struct simops *s, uint32 ins)
}
static void
-do_long (uint32 ins)
+do_long (SIM_DESC sd, SIM_CPU *cpu, uint32 ins)
{
struct hash_entry *h;
#ifdef DEBUG
if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
(*d10v_callback->printf_filtered) (d10v_callback, "do_long 0x%x\n", ins);
#endif
- h = lookup_hash (ins, 1);
+ h = lookup_hash (sd, cpu, ins, 1);
if (h == NULL)
return;
get_operands (h->ops, ins);
State.ins_type = INS_LONG;
ins_type_counters[ (int)State.ins_type ]++;
- (h->ops->func)();
+ (h->ops->func) (sd, cpu);
}
static void
-do_2_short (uint16 ins1, uint16 ins2, enum _leftright leftright)
+do_2_short (SIM_DESC sd, SIM_CPU *cpu, uint16 ins1, uint16 ins2, enum _leftright leftright)
{
struct hash_entry *h;
enum _ins_type first, second;
@@ -150,34 +150,34 @@ do_2_short (uint16 ins1, uint16 ins2, enum _leftright leftright)
}
/* Issue the first instruction */
- h = lookup_hash (ins1, 0);
+ h = lookup_hash (sd, cpu, ins1, 0);
if (h == NULL)
return;
get_operands (h->ops, ins1);
State.ins_type = first;
ins_type_counters[ (int)State.ins_type ]++;
- (h->ops->func)();
+ (h->ops->func) (sd, cpu);
/* Issue the second instruction (if the PC hasn't changed) */
if (!State.pc_changed && !State.exception)
{
/* finish any existing instructions */
SLOT_FLUSH ();
- h = lookup_hash (ins2, 0);
+ h = lookup_hash (sd, cpu, ins2, 0);
if (h == NULL)
return;
get_operands (h->ops, ins2);
State.ins_type = second;
ins_type_counters[ (int)State.ins_type ]++;
ins_type_counters[ (int)INS_CYCLES ]++;
- (h->ops->func)();
+ (h->ops->func) (sd, cpu);
}
else if (!State.exception)
ins_type_counters[ (int)INS_COND_JUMP ]++;
}
static void
-do_parallel (uint16 ins1, uint16 ins2)
+do_parallel (SIM_DESC sd, SIM_CPU *cpu, uint16 ins1, uint16 ins2)
{
struct hash_entry *h1, *h2;
#ifdef DEBUG
@@ -185,10 +185,10 @@ do_parallel (uint16 ins1, uint16 ins2)
(*d10v_callback->printf_filtered) (d10v_callback, "do_parallel 0x%x || 0x%x\n", ins1, ins2);
#endif
ins_type_counters[ (int)INS_PARALLEL ]++;
- h1 = lookup_hash (ins1, 0);
+ h1 = lookup_hash (sd, cpu, ins1, 0);
if (h1 == NULL)
return;
- h2 = lookup_hash (ins2, 0);
+ h2 = lookup_hash (sd, cpu, ins2, 0);
if (h2 == NULL)
return;
@@ -197,14 +197,14 @@ do_parallel (uint16 ins1, uint16 ins2)
get_operands (h1->ops, ins1);
State.ins_type = INS_LEFT_COND_TEST;
ins_type_counters[ (int)State.ins_type ]++;
- (h1->ops->func)();
+ (h1->ops->func) (sd, cpu);
if (State.exe)
{
ins_type_counters[ (int)INS_COND_TRUE ]++;
get_operands (h2->ops, ins2);
State.ins_type = INS_RIGHT_COND_EXE;
ins_type_counters[ (int)State.ins_type ]++;
- (h2->ops->func)();
+ (h2->ops->func) (sd, cpu);
}
else
ins_type_counters[ (int)INS_COND_FALSE ]++;
@@ -214,14 +214,14 @@ do_parallel (uint16 ins1, uint16 ins2)
get_operands (h2->ops, ins2);
State.ins_type = INS_RIGHT_COND_TEST;
ins_type_counters[ (int)State.ins_type ]++;
- (h2->ops->func)();
+ (h2->ops->func) (sd, cpu);
if (State.exe)
{
ins_type_counters[ (int)INS_COND_TRUE ]++;
get_operands (h1->ops, ins1);
State.ins_type = INS_LEFT_COND_EXE;
ins_type_counters[ (int)State.ins_type ]++;
- (h1->ops->func)();
+ (h1->ops->func) (sd, cpu);
}
else
ins_type_counters[ (int)INS_COND_FALSE ]++;
@@ -231,13 +231,13 @@ do_parallel (uint16 ins1, uint16 ins2)
get_operands (h1->ops, ins1);
State.ins_type = INS_LEFT_PARALLEL;
ins_type_counters[ (int)State.ins_type ]++;
- (h1->ops->func)();
+ (h1->ops->func) (sd, cpu);
if (!State.exception)
{
get_operands (h2->ops, ins2);
State.ins_type = INS_RIGHT_PARALLEL;
ins_type_counters[ (int)State.ins_type ]++;
- (h2->ops->func)();
+ (h2->ops->func) (sd, cpu);
}
}
}
@@ -300,9 +300,9 @@ enum
};
static void
-set_dmap_register (int reg_nr, unsigned long value)
+set_dmap_register (SIM_DESC sd, int reg_nr, unsigned long value)
{
- uint8 *raw = map_memory (SIM_D10V_MEMORY_DATA
+ uint8 *raw = map_memory (sd, NULL, SIM_D10V_MEMORY_DATA
+ DMAP0_OFFSET + 2 * reg_nr);
WRITE_16 (raw, value);
#ifdef DEBUG
@@ -315,17 +315,17 @@ set_dmap_register (int reg_nr, unsigned long value)
}
static unsigned long
-dmap_register (void *regcache, int reg_nr)
+dmap_register (SIM_DESC sd, SIM_CPU *cpu, void *regcache, int reg_nr)
{
- uint8 *raw = map_memory (SIM_D10V_MEMORY_DATA
+ uint8 *raw = map_memory (sd, cpu, SIM_D10V_MEMORY_DATA
+ DMAP0_OFFSET + 2 * reg_nr);
return READ_16 (raw);
}
static void
-set_imap_register (int reg_nr, unsigned long value)
+set_imap_register (SIM_DESC sd, int reg_nr, unsigned long value)
{
- uint8 *raw = map_memory (SIM_D10V_MEMORY_DATA
+ uint8 *raw = map_memory (sd, NULL, SIM_D10V_MEMORY_DATA
+ IMAP0_OFFSET + 2 * reg_nr);
WRITE_16 (raw, value);
#ifdef DEBUG
@@ -338,9 +338,9 @@ set_imap_register (int reg_nr, unsigned long value)
}
static unsigned long
-imap_register (void *regcache, int reg_nr)
+imap_register (SIM_DESC sd, SIM_CPU *cpu, void *regcache, int reg_nr)
{
- uint8 *raw = map_memory (SIM_D10V_MEMORY_DATA
+ uint8 *raw = map_memory (sd, cpu, SIM_D10V_MEMORY_DATA
+ IMAP0_OFFSET + 2 * reg_nr);
return READ_16 (raw);
}
@@ -389,11 +389,15 @@ set_spu_register (unsigned long value)
into a physical address. */
static unsigned long
-sim_d10v_translate_dmap_addr (unsigned long offset,
+sim_d10v_translate_dmap_addr (SIM_DESC sd,
+ SIM_CPU *cpu,
+ unsigned long offset,
int nr_bytes,
unsigned long *phys,
void *regcache,
- unsigned long (*dmap_register) (void *regcache,
+ unsigned long (*dmap_register) (SIM_DESC,
+ SIM_CPU *,
+ void *regcache,
int reg_nr))
{
short map;
@@ -411,7 +415,7 @@ sim_d10v_translate_dmap_addr (unsigned long offset,
/* Don't cross a BLOCK boundary */
nr_bytes = DMAP_BLOCK_SIZE - (offset % DMAP_BLOCK_SIZE);
}
- map = dmap_register (regcache, regno);
+ map = dmap_register (sd, cpu, regcache, regno);
if (regno == 3)
{
/* Always maps to data memory */
@@ -449,11 +453,15 @@ sim_d10v_translate_dmap_addr (unsigned long offset,
into a physical address. */
static unsigned long
-sim_d10v_translate_imap_addr (unsigned long offset,
+sim_d10v_translate_imap_addr (SIM_DESC sd,
+ SIM_CPU *cpu,
+ unsigned long offset,
int nr_bytes,
unsigned long *phys,
void *regcache,
- unsigned long (*imap_register) (void *regcache,
+ unsigned long (*imap_register) (SIM_DESC,
+ SIM_CPU *,
+ void *regcache,
int reg_nr))
{
short map;
@@ -473,7 +481,7 @@ sim_d10v_translate_imap_addr (unsigned long offset,
/* Don't cross a BLOCK boundary */
nr_bytes = IMAP_BLOCK_SIZE - offset;
}
- map = imap_register (regcache, regno);
+ map = imap_register (sd, cpu, regcache, regno);
sp = (map & 0x3000) >> 12;
segno = (map & 0x007f);
switch (sp)
@@ -502,13 +510,19 @@ sim_d10v_translate_imap_addr (unsigned long offset,
}
static unsigned long
-sim_d10v_translate_addr (unsigned long memaddr,
+sim_d10v_translate_addr (SIM_DESC sd,
+ SIM_CPU *cpu,
+ unsigned long memaddr,
int nr_bytes,
unsigned long *targ_addr,
void *regcache,
- unsigned long (*dmap_register) (void *regcache,
+ unsigned long (*dmap_register) (SIM_DESC,
+ SIM_CPU *,
+ void *regcache,
int reg_nr),
- unsigned long (*imap_register) (void *regcache,
+ unsigned long (*imap_register) (SIM_DESC,
+ SIM_CPU *,
+ void *regcache,
int reg_nr))
{
unsigned long phys;
@@ -573,13 +587,13 @@ sim_d10v_translate_addr (unsigned long memaddr,
break;
case 0x10: /* in logical data address segment */
- nr_bytes = sim_d10v_translate_dmap_addr (off, nr_bytes, &phys, regcache,
- dmap_register);
+ nr_bytes = sim_d10v_translate_dmap_addr (sd, cpu, off, nr_bytes, &phys,
+ regcache, dmap_register);
break;
case 0x11: /* in logical instruction address segment */
- nr_bytes = sim_d10v_translate_imap_addr (off, nr_bytes, &phys, regcache,
- imap_register);
+ nr_bytes = sim_d10v_translate_imap_addr (sd, cpu, off, nr_bytes, &phys,
+ regcache, imap_register);
break;
default:
@@ -595,7 +609,7 @@ sim_d10v_translate_addr (unsigned long memaddr,
isn't going to cross a segment boundary. */
uint8 *
-map_memory (unsigned phys_addr)
+map_memory (SIM_DESC sd, SIM_CPU *cpu, unsigned phys_addr)
{
uint8 **memory;
uint8 *raw;
@@ -667,7 +681,8 @@ map_memory (unsigned phys_addr)
than aborting the entire run. */
static int
-xfer_mem (SIM_ADDR virt,
+xfer_mem (SIM_DESC sd,
+ SIM_ADDR virt,
unsigned char *buffer,
int size,
int write_p)
@@ -675,12 +690,12 @@ xfer_mem (SIM_ADDR virt,
uint8 *memory;
unsigned long phys;
int phys_size;
- phys_size = sim_d10v_translate_addr (virt, size, &phys, NULL,
+ phys_size = sim_d10v_translate_addr (sd, NULL, virt, size, &phys, NULL,
dmap_register, imap_register);
if (phys_size == 0)
return 0;
- memory = map_memory (phys);
+ memory = map_memory (sd, NULL, phys);
#ifdef DEBUG
if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
@@ -712,14 +727,14 @@ int
sim_write (SIM_DESC sd, SIM_ADDR addr, const unsigned char *buffer, int size)
{
/* FIXME: this should be performing a virtual transfer */
- return xfer_mem( addr, buffer, size, 1);
+ return xfer_mem (sd, addr, buffer, size, 1);
}
int
sim_read (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size)
{
/* FIXME: this should be performing a virtual transfer */
- return xfer_mem( addr, buffer, size, 0);
+ return xfer_mem (sd, addr, buffer, size, 0);
}
static sim_cia
@@ -731,6 +746,7 @@ d10v_pc_get (sim_cpu *cpu)
static void
d10v_pc_set (sim_cpu *cpu, sim_cia pc)
{
+ SIM_DESC sd = CPU_STATE (cpu);
SET_PC (pc);
}
@@ -743,8 +759,6 @@ free_state (SIM_DESC sd)
sim_state_free (sd);
}
-SIM_DESC trace_sd = NULL;
-
SIM_DESC
sim_open (SIM_OPEN_KIND kind, host_callback *cb, struct bfd *abfd, char **argv)
{
@@ -813,7 +827,6 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb, struct bfd *abfd, char **argv)
CPU_PC_STORE (cpu) = d10v_pc_set;
}
- trace_sd = sd;
d10v_callback = cb;
old_segment_mapping = 0;
@@ -867,7 +880,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb, struct bfd *abfd, char **argv)
}
uint8 *
-dmem_addr (uint16 offset)
+dmem_addr (SIM_DESC sd, SIM_CPU *cpu, uint16 offset)
{
unsigned long phys;
uint8 *mem;
@@ -877,14 +890,14 @@ dmem_addr (uint16 offset)
things like ``0xfffe + 0x0e60 == 0x10e5d''. Since offset's type
is uint16 this is modulo'ed onto 0x0e5d. */
- phys_size = sim_d10v_translate_dmap_addr (offset, 1, &phys, NULL,
+ phys_size = sim_d10v_translate_dmap_addr (sd, cpu, offset, 1, &phys, NULL,
dmap_register);
if (phys_size == 0)
{
mem = State.mem.fault;
}
else
- mem = map_memory (phys);
+ mem = map_memory (sd, cpu, phys);
#ifdef DEBUG
if ((d10v_debug & DEBUG_MEMORY))
{
@@ -900,17 +913,17 @@ dmem_addr (uint16 offset)
}
uint8 *
-imem_addr (uint32 offset)
+imem_addr (SIM_DESC sd, SIM_CPU *cpu, uint32 offset)
{
unsigned long phys;
uint8 *mem;
- int phys_size = sim_d10v_translate_imap_addr (offset, 1, &phys, NULL,
+ int phys_size = sim_d10v_translate_imap_addr (sd, cpu, offset, 1, &phys, NULL,
imap_register);
if (phys_size == 0)
{
return State.mem.fault;
}
- mem = map_memory (phys);
+ mem = map_memory (sd, cpu, phys);
#ifdef DEBUG
if ((d10v_debug & DEBUG_MEMORY))
{
@@ -939,6 +952,7 @@ sim_stop (SIM_DESC sd)
void
sim_resume (SIM_DESC sd, int step, int siggnal)
{
+ SIM_CPU *cpu = STATE_CPU (sd, 0);
uint32 inst;
uint8 *iaddr;
@@ -972,7 +986,7 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
do
{
- iaddr = imem_addr ((uint32)PC << 2);
+ iaddr = imem_addr (sd, cpu, (uint32)PC << 2);
if (iaddr == State.mem.fault)
{
State.exception = GDB_SIGNAL_BUS;
@@ -988,18 +1002,18 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
{
case 0xC0000000:
/* long instruction */
- do_long (inst & 0x3FFFFFFF);
+ do_long (sd, cpu, inst & 0x3FFFFFFF);
break;
case 0x80000000:
/* R -> L */
- do_2_short ( inst & 0x7FFF, (inst & 0x3FFF8000) >> 15, RIGHT_FIRST);
+ do_2_short (sd, cpu, inst & 0x7FFF, (inst & 0x3FFF8000) >> 15, RIGHT_FIRST);
break;
case 0x40000000:
/* L -> R */
- do_2_short ((inst & 0x3FFF8000) >> 15, inst & 0x7FFF, LEFT_FIRST);
+ do_2_short (sd, cpu, (inst & 0x3FFF8000) >> 15, inst & 0x7FFF, LEFT_FIRST);
break;
case 0:
- do_parallel ((inst & 0x3FFF8000) >> 15, inst & 0x7FFF);
+ do_parallel (sd, cpu, (inst & 0x3FFF8000) >> 15, inst & 0x7FFF);
break;
}
@@ -1178,7 +1192,10 @@ sim_create_inferior (SIM_DESC sd, struct bfd *abfd, char **argv, char **env)
if (d10v_debug)
(*d10v_callback->printf_filtered) (d10v_callback, "sim_create_inferior: PC=0x%lx\n", (long) start_address);
#endif
- SET_CREG (PC_CR, start_address >> 2);
+ {
+ SIM_CPU *cpu = STATE_CPU (sd, 0);
+ SET_CREG (PC_CR, start_address >> 2);
+ }
/* cpu resets imap0 to 0 and imap1 to 0x7f, but D10V-EVA board
initializes imap0 and imap1 to 0x1000 as part of its ROM
@@ -1186,23 +1203,23 @@ sim_create_inferior (SIM_DESC sd, struct bfd *abfd, char **argv, char **env)
if (old_segment_mapping)
{
/* External memory startup. This is the HARD reset state. */
- set_imap_register (0, 0x0000);
- set_imap_register (1, 0x007f);
- set_dmap_register (0, 0x2000);
- set_dmap_register (1, 0x2000);
- set_dmap_register (2, 0x0000); /* Old DMAP */
- set_dmap_register (3, 0x0000);
+ set_imap_register (sd, 0, 0x0000);
+ set_imap_register (sd, 1, 0x007f);
+ set_dmap_register (sd, 0, 0x2000);
+ set_dmap_register (sd, 1, 0x2000);
+ set_dmap_register (sd, 2, 0x0000); /* Old DMAP */
+ set_dmap_register (sd, 3, 0x0000);
}
else
{
/* Internal memory startup. This is the ROM intialized state. */
- set_imap_register (0, 0x1000);
- set_imap_register (1, 0x1000);
- set_dmap_register (0, 0x2000);
- set_dmap_register (1, 0x2000);
- set_dmap_register (2, 0x2000); /* DMAP2 initial internal value is
- 0x2000 on the new board. */
- set_dmap_register (3, 0x0000);
+ set_imap_register (sd, 0, 0x1000);
+ set_imap_register (sd, 1, 0x1000);
+ set_dmap_register (sd, 0, 0x2000);
+ set_dmap_register (sd, 1, 0x2000);
+ set_dmap_register (sd, 2, 0x2000); /* DMAP2 initial internal value is
+ 0x2000 on the new board. */
+ set_dmap_register (sd, 3, 0x0000);
}
SLOT_FLUSH ();
@@ -1246,6 +1263,7 @@ sim_stop_reason (SIM_DESC sd, enum sim_stop *reason, int *sigrc)
int
sim_fetch_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
{
+ SIM_CPU *cpu = STATE_CPU (sd, 0);
int size;
switch ((enum sim_d10v_regs) rn)
{
@@ -1306,14 +1324,14 @@ sim_fetch_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
break;
case SIM_D10V_IMAP0_REGNUM:
case SIM_D10V_IMAP1_REGNUM:
- WRITE_16 (memory, imap_register (NULL, rn - SIM_D10V_IMAP0_REGNUM));
+ WRITE_16 (memory, imap_register (sd, cpu, NULL, rn - SIM_D10V_IMAP0_REGNUM));
size = 2;
break;
case SIM_D10V_DMAP0_REGNUM:
case SIM_D10V_DMAP1_REGNUM:
case SIM_D10V_DMAP2_REGNUM:
case SIM_D10V_DMAP3_REGNUM:
- WRITE_16 (memory, dmap_register (NULL, rn - SIM_D10V_DMAP0_REGNUM));
+ WRITE_16 (memory, dmap_register (sd, cpu, NULL, rn - SIM_D10V_DMAP0_REGNUM));
size = 2;
break;
case SIM_D10V_TS2_DMAP_REGNUM:
@@ -1329,6 +1347,7 @@ sim_fetch_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
int
sim_store_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
{
+ SIM_CPU *cpu = STATE_CPU (sd, 0);
int size;
switch ((enum sim_d10v_regs) rn)
{
@@ -1387,14 +1406,14 @@ sim_store_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
break;
case SIM_D10V_IMAP0_REGNUM:
case SIM_D10V_IMAP1_REGNUM:
- set_imap_register (rn - SIM_D10V_IMAP0_REGNUM, READ_16(memory));
+ set_imap_register (sd, rn - SIM_D10V_IMAP0_REGNUM, READ_16(memory));
size = 2;
break;
case SIM_D10V_DMAP0_REGNUM:
case SIM_D10V_DMAP1_REGNUM:
case SIM_D10V_DMAP2_REGNUM:
case SIM_D10V_DMAP3_REGNUM:
- set_dmap_register (rn - SIM_D10V_DMAP0_REGNUM, READ_16(memory));
+ set_dmap_register (sd, rn - SIM_D10V_DMAP0_REGNUM, READ_16(memory));
size = 2;
break;
case SIM_D10V_TS2_DMAP_REGNUM:
diff --git a/sim/d10v/simops.c b/sim/d10v/simops.c
index 2c457bb..28044f6 100644
--- a/sim/d10v/simops.c
+++ b/sim/d10v/simops.c
@@ -63,7 +63,7 @@ enum {
};
reg_t
-move_to_cr (int cr, reg_t mask, reg_t val, int psw_hw_p)
+move_to_cr (SIM_DESC sd, SIM_CPU *cpu, int cr, reg_t mask, reg_t val, int psw_hw_p)
{
/* A MASK bit is set when the corresponding bit in the CR should
be left alone */
@@ -120,12 +120,13 @@ move_to_cr (int cr, reg_t mask, reg_t val, int psw_hw_p)
}
#ifdef DEBUG
-static void trace_input_func (const char *name,
+static void trace_input_func (SIM_DESC sd,
+ const char *name,
enum op_types in1,
enum op_types in2,
enum op_types in3);
-#define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
+#define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (sd, name, in1, in2, in3); } while (0)
#ifndef SIZE_INSTRUCTION
#define SIZE_INSTRUCTION 8
@@ -152,7 +153,7 @@ static void trace_input_func (const char *name,
#endif
static void
-trace_input_func (const char *name, enum op_types in1, enum op_types in2, enum op_types in3)
+trace_input_func (SIM_DESC sd, const char *name, enum op_types in1, enum op_types in2, enum op_types in3)
{
char *comma;
enum op_types in[3];
@@ -193,21 +194,19 @@ trace_input_func (const char *name, enum op_types in1, enum op_types in2, enum o
else
{
- extern SIM_DESC trace_sd;
-
buf[0] = '\0';
byte_pc = PC;
- if (STATE_TEXT_SECTION (trace_sd)
- && byte_pc >= STATE_TEXT_START (trace_sd)
- && byte_pc < STATE_TEXT_END (trace_sd))
+ if (STATE_TEXT_SECTION (sd)
+ && byte_pc >= STATE_TEXT_START (sd)
+ && byte_pc < STATE_TEXT_END (sd))
{
filename = (const char *)0;
functionname = (const char *)0;
linenumber = 0;
- if (bfd_find_nearest_line (STATE_PROG_BFD (trace_sd),
- STATE_TEXT_SECTION (trace_sd),
+ if (bfd_find_nearest_line (STATE_PROG_BFD (sd),
+ STATE_TEXT_SECTION (sd),
(struct bfd_symbol **)0,
- byte_pc - STATE_TEXT_START (trace_sd),
+ byte_pc - STATE_TEXT_START (sd),
&filename, &functionname, &linenumber))
{
p = buf;
@@ -490,13 +489,13 @@ trace_input_func (const char *name, enum op_types in1, enum op_types in2, enum o
}
static void
-do_trace_output_flush (void)
+do_trace_output_flush (SIM_DESC sd)
{
(*d10v_callback->flush_stdout) (d10v_callback);
}
static void
-do_trace_output_finish (void)
+do_trace_output_finish (SIM_DESC sd)
{
(*d10v_callback->printf_filtered) (d10v_callback,
" F0=%d F1=%d C=%d\n",
@@ -507,7 +506,7 @@ do_trace_output_finish (void)
}
static void
-trace_output_40 (uint64 val)
+trace_output_40 (SIM_DESC sd, uint64 val)
{
if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
{
@@ -517,12 +516,12 @@ trace_output_40 (uint64 val)
"",
((int)(val >> 32) & 0xff),
((unsigned long) val) & 0xffffffff);
- do_trace_output_finish ();
+ do_trace_output_finish (sd);
}
}
static void
-trace_output_32 (uint32 val)
+trace_output_32 (SIM_DESC sd, uint32 val)
{
if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
{
@@ -531,12 +530,12 @@ trace_output_32 (uint32 val)
SIZE_VALUES - 10,
"",
(int) val);
- do_trace_output_finish ();
+ do_trace_output_finish (sd);
}
}
static void
-trace_output_16 (uint16 val)
+trace_output_16 (SIM_DESC sd, uint16 val)
{
if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
{
@@ -545,22 +544,22 @@ trace_output_16 (uint16 val)
SIZE_VALUES - 6,
"",
(int) val);
- do_trace_output_finish ();
+ do_trace_output_finish (sd);
}
}
static void
-trace_output_void (void)
+trace_output_void (SIM_DESC sd)
{
if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
{
(*d10v_callback->printf_filtered) (d10v_callback, "\n");
- do_trace_output_flush ();
+ do_trace_output_flush (sd);
}
}
static void
-trace_output_flag (void)
+trace_output_flag (SIM_DESC sd)
{
if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
{
@@ -568,7 +567,7 @@ trace_output_flag (void)
" :: %*s",
SIZE_VALUES,
"");
- do_trace_output_finish ();
+ do_trace_output_finish (sd);
}
}
@@ -582,7 +581,7 @@ trace_output_flag (void)
/* abs */
void
-OP_4607 (void)
+OP_4607 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
@@ -596,12 +595,12 @@ OP_4607 (void)
else
SET_PSW_F0 (0);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* abs */
void
-OP_5607 (void)
+OP_5607 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
@@ -630,12 +629,12 @@ OP_5607 (void)
SET_PSW_F0 (0);
}
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* add */
void
-OP_200 (void)
+OP_200 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = GPR (OP[0]);
uint16 b = GPR (OP[1]);
@@ -643,12 +642,12 @@ OP_200 (void)
trace_input ("add", OP_REG, OP_REG, OP_VOID);
SET_PSW_C (a > tmp);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* add */
void
-OP_1201 (void)
+OP_1201 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
tmp = SEXT40(ACC (OP[0])) + (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
@@ -666,12 +665,12 @@ OP_1201 (void)
else
tmp = (tmp & MASK40);
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* add */
void
-OP_1203 (void)
+OP_1203 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
tmp = SEXT40(ACC (OP[0])) + SEXT40(ACC (OP[1]));
@@ -689,12 +688,12 @@ OP_1203 (void)
else
tmp = (tmp & MASK40);
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* add2w */
void
-OP_1200 (void)
+OP_1200 (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 tmp;
uint32 a = (GPR (OP[0])) << 16 | GPR (OP[0] + 1);
@@ -704,12 +703,12 @@ OP_1200 (void)
SET_PSW_C (tmp < a);
SET_GPR (OP[0] + 0, (tmp >> 16));
SET_GPR (OP[0] + 1, (tmp & 0xFFFF));
- trace_output_32 (tmp);
+ trace_output_32 (sd, tmp);
}
/* add3 */
void
-OP_1000000 (void)
+OP_1000000 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = GPR (OP[1]);
uint16 b = OP[2];
@@ -717,12 +716,12 @@ OP_1000000 (void)
trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
SET_PSW_C (tmp < a);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* addac3 */
void
-OP_17000200 (void)
+OP_17000200 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
tmp = SEXT40(ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
@@ -730,12 +729,12 @@ OP_17000200 (void)
trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
SET_GPR (OP[0] + 0, ((tmp >> 16) & 0xffff));
SET_GPR (OP[0] + 1, (tmp & 0xffff));
- trace_output_32 (tmp);
+ trace_output_32 (sd, tmp);
}
/* addac3 */
void
-OP_17000202 (void)
+OP_17000202 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
@@ -743,12 +742,12 @@ OP_17000202 (void)
trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
SET_GPR (OP[0] + 1, tmp & 0xffff);
- trace_output_32 (tmp);
+ trace_output_32 (sd, tmp);
}
/* addac3s */
void
-OP_17001200 (void)
+OP_17001200 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
SET_PSW_F1 (PSW_F0);
@@ -771,12 +770,12 @@ OP_17001200 (void)
}
SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
SET_GPR (OP[0] + 1, (tmp & 0xffff));
- trace_output_32 (tmp);
+ trace_output_32 (sd, tmp);
}
/* addac3s */
void
-OP_17001202 (void)
+OP_17001202 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
SET_PSW_F1 (PSW_F0);
@@ -799,12 +798,12 @@ OP_17001202 (void)
}
SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
SET_GPR (OP[0] + 1, (tmp & 0xffff));
- trace_output_32 (tmp);
+ trace_output_32 (sd, tmp);
}
/* addi */
void
-OP_201 (void)
+OP_201 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = GPR (OP[0]);
uint16 b;
@@ -816,262 +815,262 @@ OP_201 (void)
trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
SET_PSW_C (tmp < a);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* and */
void
-OP_C00 (void)
+OP_C00 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 tmp = GPR (OP[0]) & GPR (OP[1]);
trace_input ("and", OP_REG, OP_REG, OP_VOID);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* and3 */
void
-OP_6000000 (void)
+OP_6000000 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 tmp = GPR (OP[1]) & OP[2];
trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* bclri */
void
-OP_C01 (void)
+OP_C01 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
tmp = (GPR (OP[0]) &~(0x8000 >> OP[1]));
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* bl.s */
void
-OP_4900 (void)
+OP_4900 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("bl.s", OP_CONSTANT8, OP_R0, OP_R1);
SET_GPR (13, PC + 1);
JMP( PC + SEXT8 (OP[0]));
- trace_output_void ();
+ trace_output_void (sd);
}
/* bl.l */
void
-OP_24800000 (void)
+OP_24800000 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("bl.l", OP_CONSTANT16, OP_R0, OP_R1);
SET_GPR (13, (PC + 1));
JMP (PC + OP[0]);
- trace_output_void ();
+ trace_output_void (sd);
}
/* bnoti */
void
-OP_A01 (void)
+OP_A01 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
tmp = (GPR (OP[0]) ^ (0x8000 >> OP[1]));
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* bra.s */
void
-OP_4800 (void)
+OP_4800 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID);
JMP (PC + SEXT8 (OP[0]));
- trace_output_void ();
+ trace_output_void (sd);
}
/* bra.l */
void
-OP_24000000 (void)
+OP_24000000 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
JMP (PC + OP[0]);
- trace_output_void ();
+ trace_output_void (sd);
}
/* brf0f.s */
void
-OP_4A00 (void)
+OP_4A00 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID);
if (!PSW_F0)
JMP (PC + SEXT8 (OP[0]));
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* brf0f.l */
void
-OP_25000000 (void)
+OP_25000000 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
if (!PSW_F0)
JMP (PC + OP[0]);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* brf0t.s */
void
-OP_4B00 (void)
+OP_4B00 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID);
if (PSW_F0)
JMP (PC + SEXT8 (OP[0]));
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* brf0t.l */
void
-OP_25800000 (void)
+OP_25800000 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
if (PSW_F0)
JMP (PC + OP[0]);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* bseti */
void
-OP_801 (void)
+OP_801 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
tmp = (GPR (OP[0]) | (0x8000 >> OP[1]));
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* btsti */
void
-OP_E01 (void)
+OP_E01 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
SET_PSW_F1 (PSW_F0);
SET_PSW_F0 ((GPR (OP[0]) & (0x8000 >> OP[1])) ? 1 : 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* clrac */
void
-OP_5601 (void)
+OP_5601 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
SET_ACC (OP[0], 0);
- trace_output_40 (0);
+ trace_output_40 (sd, 0);
}
/* cmp */
void
-OP_600 (void)
+OP_600 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
SET_PSW_F1 (PSW_F0);
SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(GPR (OP[1]))) ? 1 : 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* cmp */
void
-OP_1603 (void)
+OP_1603 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
SET_PSW_F1 (PSW_F0);
SET_PSW_F0 ((SEXT40(ACC (OP[0])) < SEXT40(ACC (OP[1]))) ? 1 : 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* cmpeq */
void
-OP_400 (void)
+OP_400 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
SET_PSW_F1 (PSW_F0);
SET_PSW_F0 ((GPR (OP[0]) == GPR (OP[1])) ? 1 : 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* cmpeq */
void
-OP_1403 (void)
+OP_1403 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
SET_PSW_F1 (PSW_F0);
SET_PSW_F0 (((ACC (OP[0]) & MASK40) == (ACC (OP[1]) & MASK40)) ? 1 : 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* cmpeqi.s */
void
-OP_401 (void)
+OP_401 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID);
SET_PSW_F1 (PSW_F0);
SET_PSW_F0 ((GPR (OP[0]) == (reg_t) SEXT4 (OP[1])) ? 1 : 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* cmpeqi.l */
void
-OP_2000000 (void)
+OP_2000000 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
SET_PSW_F1 (PSW_F0);
SET_PSW_F0 ((GPR (OP[0]) == (reg_t)OP[1]) ? 1 : 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* cmpi.s */
void
-OP_601 (void)
+OP_601 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
SET_PSW_F1 (PSW_F0);
SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)SEXT4(OP[1])) ? 1 : 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* cmpi.l */
void
-OP_3000000 (void)
+OP_3000000 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
SET_PSW_F1 (PSW_F0);
SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(OP[1])) ? 1 : 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* cmpu */
void
-OP_4600 (void)
+OP_4600 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
SET_PSW_F1 (PSW_F0);
SET_PSW_F0 ((GPR (OP[0]) < GPR (OP[1])) ? 1 : 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* cmpui */
void
-OP_23000000 (void)
+OP_23000000 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
SET_PSW_F1 (PSW_F0);
SET_PSW_F0 ((GPR (OP[0]) < (reg_t)OP[1]) ? 1 : 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* cpfg */
void
-OP_4E09 (void)
+OP_4E09 (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 val;
@@ -1088,12 +1087,12 @@ OP_4E09 (void)
else
SET_PSW_F1 (val);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* cpfg */
void
-OP_4E0F (void)
+OP_4E0F (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 val;
@@ -1110,12 +1109,12 @@ OP_4E0F (void)
else
SET_PSW_F1 (val);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* dbt */
void
-OP_5F20 (void)
+OP_5F20 (SIM_DESC sd, SIM_CPU *cpu)
{
/* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
@@ -1136,7 +1135,7 @@ OP_5F20 (void)
SET_DPSW (PSW);
SET_HW_PSW (PSW_DM_BIT | (PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT)));
JMP (DBT_VECTOR_START);
- trace_output_void ();
+ trace_output_void (sd);
}
else
{
@@ -1146,7 +1145,7 @@ OP_5F20 (void)
/* divs */
void
-OP_14002800 (void)
+OP_14002800 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 foo, tmp, tmpf;
uint16 hi;
@@ -1160,84 +1159,84 @@ OP_14002800 (void)
lo = ((GPR (OP[0] + 1) << 1) | tmpf);
SET_GPR (OP[0] + 0, hi);
SET_GPR (OP[0] + 1, lo);
- trace_output_32 (((uint32) hi << 16) | lo);
+ trace_output_32 (sd, ((uint32) hi << 16) | lo);
}
/* exef0f */
void
-OP_4E04 (void)
+OP_4E04 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
State.exe = (PSW_F0 == 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* exef0t */
void
-OP_4E24 (void)
+OP_4E24 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
State.exe = (PSW_F0 != 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* exef1f */
void
-OP_4E40 (void)
+OP_4E40 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
State.exe = (PSW_F1 == 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* exef1t */
void
-OP_4E42 (void)
+OP_4E42 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
State.exe = (PSW_F1 != 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* exefaf */
void
-OP_4E00 (void)
+OP_4E00 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
State.exe = (PSW_F0 == 0) & (PSW_F1 == 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* exefat */
void
-OP_4E02 (void)
+OP_4E02 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
State.exe = (PSW_F0 == 0) & (PSW_F1 != 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* exetaf */
void
-OP_4E20 (void)
+OP_4E20 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
State.exe = (PSW_F0 != 0) & (PSW_F1 == 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* exetat */
void
-OP_4E22 (void)
+OP_4E22 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
State.exe = (PSW_F0 != 0) & (PSW_F1 != 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* exp */
void
-OP_15002A00 (void)
+OP_15002A00 (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 tmp, foo;
int i;
@@ -1254,18 +1253,18 @@ OP_15002A00 (void)
if (tmp & foo)
{
SET_GPR (OP[0], (i - 1));
- trace_output_16 (i - 1);
+ trace_output_16 (sd, i - 1);
return;
}
foo >>= 1;
}
SET_GPR (OP[0], 16);
- trace_output_16 (16);
+ trace_output_16 (sd, 16);
}
/* exp */
void
-OP_15002A02 (void)
+OP_15002A02 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp, foo;
int i;
@@ -1281,40 +1280,40 @@ OP_15002A02 (void)
if (tmp & foo)
{
SET_GPR (OP[0], i - 9);
- trace_output_16 (i - 9);
+ trace_output_16 (sd, i - 9);
return;
}
foo >>= 1;
}
SET_GPR (OP[0], 16);
- trace_output_16 (16);
+ trace_output_16 (sd, 16);
}
/* jl */
void
-OP_4D00 (void)
+OP_4D00 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("jl", OP_REG, OP_R0, OP_R1);
SET_GPR (13, PC + 1);
JMP (GPR (OP[0]));
- trace_output_void ();
+ trace_output_void (sd);
}
/* jmp */
void
-OP_4C00 (void)
+OP_4C00 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("jmp", OP_REG,
(OP[0] == 13) ? OP_R0 : OP_VOID,
(OP[0] == 13) ? OP_R1 : OP_VOID);
JMP (GPR (OP[0]));
- trace_output_void ();
+ trace_output_void (sd);
}
/* ld */
void
-OP_30000000 (void)
+OP_30000000 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 tmp;
uint16 addr = OP[1] + GPR (OP[2]);
@@ -1323,17 +1322,17 @@ OP_30000000 (void)
{
State.exception = SIG_D10V_BUS;
State.pc_changed = 1; /* Don't increment the PC. */
- trace_output_void ();
+ trace_output_void (sd);
return;
}
tmp = RW (addr);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* ld */
void
-OP_6401 (void)
+OP_6401 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 tmp;
uint16 addr = GPR (OP[1]);
@@ -1342,19 +1341,19 @@ OP_6401 (void)
{
State.exception = SIG_D10V_BUS;
State.pc_changed = 1; /* Don't increment the PC. */
- trace_output_void ();
+ trace_output_void (sd);
return;
}
tmp = RW (addr);
SET_GPR (OP[0], tmp);
if (OP[0] != OP[1])
INC_ADDR (OP[1], -2);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* ld */
void
-OP_6001 (void)
+OP_6001 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 tmp;
uint16 addr = GPR (OP[1]);
@@ -1363,19 +1362,19 @@ OP_6001 (void)
{
State.exception = SIG_D10V_BUS;
State.pc_changed = 1; /* Don't increment the PC. */
- trace_output_void ();
+ trace_output_void (sd);
return;
}
tmp = RW (addr);
SET_GPR (OP[0], tmp);
if (OP[0] != OP[1])
INC_ADDR (OP[1], 2);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* ld */
void
-OP_6000 (void)
+OP_6000 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 tmp;
uint16 addr = GPR (OP[1]);
@@ -1384,17 +1383,17 @@ OP_6000 (void)
{
State.exception = SIG_D10V_BUS;
State.pc_changed = 1; /* Don't increment the PC. */
- trace_output_void ();
+ trace_output_void (sd);
return;
}
tmp = RW (addr);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* ld */
void
-OP_32010000 (void)
+OP_32010000 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 tmp;
uint16 addr = OP[1];
@@ -1403,17 +1402,17 @@ OP_32010000 (void)
{
State.exception = SIG_D10V_BUS;
State.pc_changed = 1; /* Don't increment the PC. */
- trace_output_void ();
+ trace_output_void (sd);
return;
}
tmp = RW (addr);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* ld2w */
void
-OP_31000000 (void)
+OP_31000000 (SIM_DESC sd, SIM_CPU *cpu)
{
int32 tmp;
uint16 addr = OP[1] + GPR (OP[2]);
@@ -1422,17 +1421,17 @@ OP_31000000 (void)
{
State.exception = SIG_D10V_BUS;
State.pc_changed = 1; /* Don't increment the PC. */
- trace_output_void ();
+ trace_output_void (sd);
return;
}
tmp = RLW (addr);
SET_GPR32 (OP[0], tmp);
- trace_output_32 (tmp);
+ trace_output_32 (sd, tmp);
}
/* ld2w */
void
-OP_6601 (void)
+OP_6601 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 addr = GPR (OP[1]);
int32 tmp;
@@ -1441,19 +1440,19 @@ OP_6601 (void)
{
State.exception = SIG_D10V_BUS;
State.pc_changed = 1; /* Don't increment the PC. */
- trace_output_void ();
+ trace_output_void (sd);
return;
}
tmp = RLW (addr);
SET_GPR32 (OP[0], tmp);
if (OP[0] != OP[1] && ((OP[0] + 1) != OP[1]))
INC_ADDR (OP[1], -4);
- trace_output_32 (tmp);
+ trace_output_32 (sd, tmp);
}
/* ld2w */
void
-OP_6201 (void)
+OP_6201 (SIM_DESC sd, SIM_CPU *cpu)
{
int32 tmp;
uint16 addr = GPR (OP[1]);
@@ -1462,19 +1461,19 @@ OP_6201 (void)
{
State.exception = SIG_D10V_BUS;
State.pc_changed = 1; /* Don't increment the PC. */
- trace_output_void ();
+ trace_output_void (sd);
return;
}
tmp = RLW (addr);
SET_GPR32 (OP[0], tmp);
if (OP[0] != OP[1] && ((OP[0] + 1) != OP[1]))
INC_ADDR (OP[1], 4);
- trace_output_32 (tmp);
+ trace_output_32 (sd, tmp);
}
/* ld2w */
void
-OP_6200 (void)
+OP_6200 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 addr = GPR (OP[1]);
int32 tmp;
@@ -1483,17 +1482,17 @@ OP_6200 (void)
{
State.exception = SIG_D10V_BUS;
State.pc_changed = 1; /* Don't increment the PC. */
- trace_output_void ();
+ trace_output_void (sd);
return;
}
tmp = RLW (addr);
SET_GPR32 (OP[0], tmp);
- trace_output_32 (tmp);
+ trace_output_32 (sd, tmp);
}
/* ld2w */
void
-OP_33010000 (void)
+OP_33010000 (SIM_DESC sd, SIM_CPU *cpu)
{
int32 tmp;
uint16 addr = OP[1];
@@ -1502,83 +1501,83 @@ OP_33010000 (void)
{
State.exception = SIG_D10V_BUS;
State.pc_changed = 1; /* Don't increment the PC. */
- trace_output_void ();
+ trace_output_void (sd);
return;
}
tmp = RLW (addr);
SET_GPR32 (OP[0], tmp);
- trace_output_32 (tmp);
+ trace_output_32 (sd, tmp);
}
/* ldb */
void
-OP_38000000 (void)
+OP_38000000 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
tmp = SEXT8 (RB (OP[1] + GPR (OP[2])));
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* ldb */
void
-OP_7000 (void)
+OP_7000 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
tmp = SEXT8 (RB (GPR (OP[1])));
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* ldi.s */
void
-OP_4001 (void)
+OP_4001 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
tmp = SEXT4 (OP[1]);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* ldi.l */
void
-OP_20000000 (void)
+OP_20000000 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("ldi.l", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
tmp = OP[1];
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* ldub */
void
-OP_39000000 (void)
+OP_39000000 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
tmp = RB (OP[1] + GPR (OP[2]));
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* ldub */
void
-OP_7200 (void)
+OP_7200 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
tmp = RB (GPR (OP[1]));
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* mac */
void
-OP_2A00 (void)
+OP_2A00 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
@@ -1604,12 +1603,12 @@ OP_2A00 (void)
else
tmp = (tmp & MASK40);
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* macsu */
void
-OP_1A00 (void)
+OP_1A00 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
@@ -1619,12 +1618,12 @@ OP_1A00 (void)
tmp = SEXT40 ((tmp << 1) & MASK40);
tmp = ((SEXT40 (ACC (OP[0])) + tmp) & MASK40);
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* macu */
void
-OP_3A00 (void)
+OP_3A00 (SIM_DESC sd, SIM_CPU *cpu)
{
uint64 tmp;
uint32 src1;
@@ -1638,12 +1637,12 @@ OP_3A00 (void)
tmp = (tmp << 1);
tmp = ((ACC (OP[0]) + tmp) & MASK40);
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* max */
void
-OP_2600 (void)
+OP_2600 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("max", OP_REG, OP_REG, OP_VOID);
@@ -1659,12 +1658,12 @@ OP_2600 (void)
SET_PSW_F0 (0);
}
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* max */
void
-OP_3600 (void)
+OP_3600 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
@@ -1682,12 +1681,12 @@ OP_3600 (void)
SET_PSW_F0 (0);
}
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* max */
void
-OP_3602 (void)
+OP_3602 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
@@ -1703,13 +1702,13 @@ OP_3602 (void)
SET_PSW_F0 (0);
}
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* min */
void
-OP_2601 (void)
+OP_2601 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("min", OP_REG, OP_REG, OP_VOID);
@@ -1725,12 +1724,12 @@ OP_2601 (void)
SET_PSW_F0 (0);
}
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* min */
void
-OP_3601 (void)
+OP_3601 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
@@ -1748,12 +1747,12 @@ OP_3601 (void)
SET_PSW_F0 (0);
}
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* min */
void
-OP_3603 (void)
+OP_3603 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
@@ -1769,12 +1768,12 @@ OP_3603 (void)
SET_PSW_F0 (0);
}
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* msb */
void
-OP_2800 (void)
+OP_2800 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
@@ -1802,12 +1801,12 @@ OP_2800 (void)
tmp = (tmp & MASK40);
}
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* msbsu */
void
-OP_1800 (void)
+OP_1800 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
@@ -1817,12 +1816,12 @@ OP_1800 (void)
tmp = SEXT40( (tmp << 1) & MASK40);
tmp = ((SEXT40 (ACC (OP[0])) - tmp) & MASK40);
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* msbu */
void
-OP_3800 (void)
+OP_3800 (SIM_DESC sd, SIM_CPU *cpu)
{
uint64 tmp;
uint32 src1;
@@ -1836,23 +1835,23 @@ OP_3800 (void)
tmp = (tmp << 1);
tmp = ((ACC (OP[0]) - tmp) & MASK40);
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* mul */
void
-OP_2E00 (void)
+OP_2E00 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("mul", OP_REG, OP_REG, OP_VOID);
tmp = GPR (OP[0]) * GPR (OP[1]);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* mulx */
void
-OP_2C00 (void)
+OP_2C00 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
@@ -1867,12 +1866,12 @@ OP_2C00 (void)
else
tmp = (tmp & MASK40);
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* mulxsu */
void
-OP_1C00 (void)
+OP_1C00 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
@@ -1883,12 +1882,12 @@ OP_1C00 (void)
tmp <<= 1;
tmp = (tmp & MASK40);
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* mulxu */
void
-OP_3C00 (void)
+OP_3C00 (SIM_DESC sd, SIM_CPU *cpu)
{
uint64 tmp;
uint32 src1;
@@ -1902,78 +1901,78 @@ OP_3C00 (void)
tmp <<= 1;
tmp = (tmp & MASK40);
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* mv */
void
-OP_4000 (void)
+OP_4000 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
tmp = GPR (OP[1]);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* mv2w */
void
-OP_5000 (void)
+OP_5000 (SIM_DESC sd, SIM_CPU *cpu)
{
int32 tmp;
trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
tmp = GPR32 (OP[1]);
SET_GPR32 (OP[0], tmp);
- trace_output_32 (tmp);
+ trace_output_32 (sd, tmp);
}
/* mv2wfac */
void
-OP_3E00 (void)
+OP_3E00 (SIM_DESC sd, SIM_CPU *cpu)
{
int32 tmp;
trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
tmp = ACC (OP[1]);
SET_GPR32 (OP[0], tmp);
- trace_output_32 (tmp);
+ trace_output_32 (sd, tmp);
}
/* mv2wtac */
void
-OP_3E01 (void)
+OP_3E01 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
trace_input ("mv2wtac", OP_DREG, OP_ACCUM_OUTPUT, OP_VOID);
tmp = ((SEXT16 (GPR (OP[0])) << 16 | GPR (OP[0] + 1)) & MASK40);
SET_ACC (OP[1], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* mvac */
void
-OP_3E03 (void)
+OP_3E03 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
tmp = ACC (OP[1]);
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* mvb */
void
-OP_5400 (void)
+OP_5400 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
tmp = SEXT8 (GPR (OP[1]) & 0xff);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* mvf0f */
void
-OP_4400 (void)
+OP_4400 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("mvf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
@@ -1984,12 +1983,12 @@ OP_4400 (void)
}
else
tmp = GPR (OP[0]);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* mvf0t */
void
-OP_4401 (void)
+OP_4401 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("mvf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
@@ -2000,124 +1999,124 @@ OP_4401 (void)
}
else
tmp = GPR (OP[0]);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* mvfacg */
void
-OP_1E04 (void)
+OP_1E04 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
tmp = ((ACC (OP[1]) >> 32) & 0xff);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* mvfachi */
void
-OP_1E00 (void)
+OP_1E00 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
tmp = (ACC (OP[1]) >> 16);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* mvfaclo */
void
-OP_1E02 (void)
+OP_1E02 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
tmp = ACC (OP[1]);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* mvfc */
void
-OP_5200 (void)
+OP_5200 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
tmp = CREG (OP[1]);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* mvtacg */
void
-OP_1E41 (void)
+OP_1E41 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
tmp = ((ACC (OP[1]) & MASK32)
| ((int64)(GPR (OP[0]) & 0xff) << 32));
SET_ACC (OP[1], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* mvtachi */
void
-OP_1E01 (void)
+OP_1E01 (SIM_DESC sd, SIM_CPU *cpu)
{
uint64 tmp;
trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
tmp = ACC (OP[1]) & 0xffff;
tmp = ((SEXT16 (GPR (OP[0])) << 16 | tmp) & MASK40);
SET_ACC (OP[1], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* mvtaclo */
void
-OP_1E21 (void)
+OP_1E21 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
tmp = ((SEXT16 (GPR (OP[0]))) & MASK40);
SET_ACC (OP[1], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* mvtc */
void
-OP_5600 (void)
+OP_5600 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
tmp = GPR (OP[0]);
tmp = SET_CREG (OP[1], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* mvub */
void
-OP_5401 (void)
+OP_5401 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
tmp = (GPR (OP[1]) & 0xff);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* neg */
void
-OP_4605 (void)
+OP_4605 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
tmp = - GPR (OP[0]);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* neg */
void
-OP_5605 (void)
+OP_5605 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
@@ -2135,13 +2134,13 @@ OP_5605 (void)
else
tmp = (tmp & MASK40);
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* nop */
void
-OP_5E00 (void)
+OP_5E00 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
@@ -2177,45 +2176,45 @@ OP_5E00 (void)
break;
}
- trace_output_void ();
+ trace_output_void (sd);
}
/* not */
void
-OP_4603 (void)
+OP_4603 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("not", OP_REG, OP_VOID, OP_VOID);
tmp = ~GPR (OP[0]);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* or */
void
-OP_800 (void)
+OP_800 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("or", OP_REG, OP_REG, OP_VOID);
tmp = (GPR (OP[0]) | GPR (OP[1]));
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* or3 */
void
-OP_4000000 (void)
+OP_4000000 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
tmp = (GPR (OP[1]) | OP[2]);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* rac */
void
-OP_5201 (void)
+OP_5201 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
int shift = SEXT3 (OP[2]);
@@ -2252,12 +2251,12 @@ OP_5201 (void)
SET_PSW_F0 (0);
}
SET_GPR32 (OP[0], tmp);
- trace_output_32 (tmp);
+ trace_output_32 (sd, tmp);
}
/* rachi */
void
-OP_4201 (void)
+OP_4201 (SIM_DESC sd, SIM_CPU *cpu)
{
signed64 tmp;
int shift = SEXT3 (OP[2]);
@@ -2286,12 +2285,12 @@ OP_4201 (void)
SET_PSW_F0 (0);
}
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* rep */
void
-OP_27000000 (void)
+OP_27000000 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
SET_RPT_S (PC + 1);
@@ -2308,12 +2307,12 @@ OP_27000000 (void)
(*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
State.exception = SIGILL;
}
- trace_output_void ();
+ trace_output_void (sd);
}
/* repi */
void
-OP_2F000000 (void)
+OP_2F000000 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
SET_RPT_S (PC + 1);
@@ -2330,31 +2329,31 @@ OP_2F000000 (void)
(*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
State.exception = SIGILL;
}
- trace_output_void ();
+ trace_output_void (sd);
}
/* rtd */
void
-OP_5F60 (void)
+OP_5F60 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("rtd", OP_VOID, OP_VOID, OP_VOID);
SET_CREG (PSW_CR, DPSW);
JMP(DPC);
- trace_output_void ();
+ trace_output_void (sd);
}
/* rte */
void
-OP_5F40 (void)
+OP_5F40 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
SET_CREG (PSW_CR, BPSW);
JMP(BPC);
- trace_output_void ();
+ trace_output_void (sd);
}
/* sac */
-void OP_5209 (void)
+void OP_5209 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
@@ -2382,12 +2381,12 @@ void OP_5209 (void)
SET_GPR32 (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* sachi */
void
-OP_4209 (void)
+OP_4209 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
@@ -2415,12 +2414,12 @@ OP_4209 (void)
SET_GPR (OP[0], tmp);
- trace_output_16 (OP[0]);
+ trace_output_16 (sd, OP[0]);
}
/* sadd */
void
-OP_1223 (void)
+OP_1223 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
@@ -2438,34 +2437,34 @@ OP_1223 (void)
else
tmp = (tmp & MASK40);
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* setf0f */
void
-OP_4611 (void)
+OP_4611 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
tmp = ((PSW_F0 == 0) ? 1 : 0);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* setf0t */
void
-OP_4613 (void)
+OP_4613 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
tmp = ((PSW_F0 == 1) ? 1 : 0);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* slae */
void
-OP_3220 (void)
+OP_3220 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
int16 reg;
@@ -2512,32 +2511,32 @@ OP_3220 (void)
SET_ACC(OP[0], tmp);
- trace_output_40(tmp);
+ trace_output_40 (sd, tmp);
}
/* sleep */
void
-OP_5FC0 (void)
+OP_5FC0 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
SET_PSW_IE (1);
- trace_output_void ();
+ trace_output_void (sd);
}
/* sll */
void
-OP_2200 (void)
+OP_2200 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("sll", OP_REG, OP_REG, OP_VOID);
tmp = (GPR (OP[0]) << (GPR (OP[1]) & 0xf));
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* sll */
void
-OP_3200 (void)
+OP_3200 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
@@ -2562,23 +2561,23 @@ OP_3200 (void)
else
tmp = (tmp & MASK40);
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* slli */
void
-OP_2201 (void)
+OP_2201 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
tmp = (GPR (OP[0]) << OP[1]);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* slli */
void
-OP_3201 (void)
+OP_3201 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
@@ -2600,41 +2599,41 @@ OP_3201 (void)
else
tmp = (tmp & MASK40);
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* slx */
void
-OP_460B (void)
+OP_460B (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("slx", OP_REG, OP_VOID, OP_VOID);
tmp = ((GPR (OP[0]) << 1) | PSW_F0);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* sra */
void
-OP_2400 (void)
+OP_2400 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("sra", OP_REG, OP_REG, OP_VOID);
tmp = (((int16)(GPR (OP[0]))) >> (GPR (OP[1]) & 0xf));
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* sra */
void
-OP_3400 (void)
+OP_3400 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
if ((GPR (OP[1]) & 31) <= 16)
{
int64 tmp = ((SEXT40(ACC (OP[0])) >> (GPR (OP[1]) & 31)) & MASK40);
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
else
{
@@ -2646,18 +2645,18 @@ OP_3400 (void)
/* srai */
void
-OP_2401 (void)
+OP_2401 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
tmp = (((int16)(GPR (OP[0]))) >> OP[1]);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* srai */
void
-OP_3401 (void)
+OP_3401 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
if (OP[1] == 0)
@@ -2666,30 +2665,30 @@ OP_3401 (void)
trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
tmp = ((SEXT40(ACC (OP[0])) >> OP[1]) & MASK40);
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* srl */
void
-OP_2000 (void)
+OP_2000 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("srl", OP_REG, OP_REG, OP_VOID);
tmp = (GPR (OP[0]) >> (GPR (OP[1]) & 0xf));
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* srl */
void
-OP_3000 (void)
+OP_3000 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
if ((GPR (OP[1]) & 31) <= 16)
{
int64 tmp = ((uint64)((ACC (OP[0]) & MASK40) >> (GPR (OP[1]) & 31)));
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
else
{
@@ -2702,18 +2701,18 @@ OP_3000 (void)
/* srli */
void
-OP_2001 (void)
+OP_2001 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
tmp = (GPR (OP[0]) >> OP[1]);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* srli */
void
-OP_3001 (void)
+OP_3001 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
if (OP[1] == 0)
@@ -2722,24 +2721,24 @@ OP_3001 (void)
trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
tmp = ((uint64)(ACC (OP[0]) & MASK40) >> OP[1]);
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* srx */
void
-OP_4609 (void)
+OP_4609 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 tmp;
trace_input ("srx", OP_REG, OP_VOID, OP_VOID);
tmp = PSW_F0 << 15;
tmp = ((GPR (OP[0]) >> 1) | tmp);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* st */
void
-OP_34000000 (void)
+OP_34000000 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 addr = OP[1] + GPR (OP[2]);
trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
@@ -2747,16 +2746,16 @@ OP_34000000 (void)
{
State.exception = SIG_D10V_BUS;
State.pc_changed = 1; /* Don't increment the PC. */
- trace_output_void ();
+ trace_output_void (sd);
return;
}
SW (addr, GPR (OP[0]));
- trace_output_void ();
+ trace_output_void (sd);
}
/* st */
void
-OP_6800 (void)
+OP_6800 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 addr = GPR (OP[1]);
trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
@@ -2764,17 +2763,17 @@ OP_6800 (void)
{
State.exception = SIG_D10V_BUS;
State.pc_changed = 1; /* Don't increment the PC. */
- trace_output_void ();
+ trace_output_void (sd);
return;
}
SW (addr, GPR (OP[0]));
- trace_output_void ();
+ trace_output_void (sd);
}
/* st */
/* st Rsrc1,@-SP */
void
-OP_6C1F (void)
+OP_6C1F (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 addr = GPR (OP[1]) - 2;
trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
@@ -2788,17 +2787,17 @@ OP_6C1F (void)
{
State.exception = SIG_D10V_BUS;
State.pc_changed = 1; /* Don't increment the PC. */
- trace_output_void ();
+ trace_output_void (sd);
return;
}
SW (addr, GPR (OP[0]));
SET_GPR (OP[1], addr);
- trace_output_void ();
+ trace_output_void (sd);
}
/* st */
void
-OP_6801 (void)
+OP_6801 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 addr = GPR (OP[1]);
trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
@@ -2806,17 +2805,17 @@ OP_6801 (void)
{
State.exception = SIG_D10V_BUS;
State.pc_changed = 1; /* Don't increment the PC. */
- trace_output_void ();
+ trace_output_void (sd);
return;
}
SW (addr, GPR (OP[0]));
INC_ADDR (OP[1], 2);
- trace_output_void ();
+ trace_output_void (sd);
}
/* st */
void
-OP_6C01 (void)
+OP_6C01 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 addr = GPR (OP[1]);
trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
@@ -2830,17 +2829,17 @@ OP_6C01 (void)
{
State.exception = SIG_D10V_BUS;
State.pc_changed = 1; /* Don't increment the PC. */
- trace_output_void ();
+ trace_output_void (sd);
return;
}
SW (addr, GPR (OP[0]));
INC_ADDR (OP[1], -2);
- trace_output_void ();
+ trace_output_void (sd);
}
/* st */
void
-OP_36010000 (void)
+OP_36010000 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 addr = OP[1];
trace_input ("st", OP_REG, OP_MEMREF3, OP_VOID);
@@ -2848,16 +2847,16 @@ OP_36010000 (void)
{
State.exception = SIG_D10V_BUS;
State.pc_changed = 1; /* Don't increment the PC. */
- trace_output_void ();
+ trace_output_void (sd);
return;
}
SW (addr, GPR (OP[0]));
- trace_output_void ();
+ trace_output_void (sd);
}
/* st2w */
void
-OP_35000000 (void)
+OP_35000000 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 addr = GPR (OP[2])+ OP[1];
trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
@@ -2865,17 +2864,17 @@ OP_35000000 (void)
{
State.exception = SIG_D10V_BUS;
State.pc_changed = 1; /* Don't increment the PC. */
- trace_output_void ();
+ trace_output_void (sd);
return;
}
SW (addr + 0, GPR (OP[0] + 0));
SW (addr + 2, GPR (OP[0] + 1));
- trace_output_void ();
+ trace_output_void (sd);
}
/* st2w */
void
-OP_6A00 (void)
+OP_6A00 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 addr = GPR (OP[1]);
trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID);
@@ -2883,17 +2882,17 @@ OP_6A00 (void)
{
State.exception = SIG_D10V_BUS;
State.pc_changed = 1; /* Don't increment the PC. */
- trace_output_void ();
+ trace_output_void (sd);
return;
}
SW (addr + 0, GPR (OP[0] + 0));
SW (addr + 2, GPR (OP[0] + 1));
- trace_output_void ();
+ trace_output_void (sd);
}
/* st2w */
void
-OP_6E1F (void)
+OP_6E1F (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 addr = GPR (OP[1]) - 4;
trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID);
@@ -2907,18 +2906,18 @@ OP_6E1F (void)
{
State.exception = SIG_D10V_BUS;
State.pc_changed = 1; /* Don't increment the PC. */
- trace_output_void ();
+ trace_output_void (sd);
return;
}
SW (addr + 0, GPR (OP[0] + 0));
SW (addr + 2, GPR (OP[0] + 1));
SET_GPR (OP[1], addr);
- trace_output_void ();
+ trace_output_void (sd);
}
/* st2w */
void
-OP_6A01 (void)
+OP_6A01 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 addr = GPR (OP[1]);
trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
@@ -2926,18 +2925,18 @@ OP_6A01 (void)
{
State.exception = SIG_D10V_BUS;
State.pc_changed = 1; /* Don't increment the PC. */
- trace_output_void ();
+ trace_output_void (sd);
return;
}
SW (addr + 0, GPR (OP[0] + 0));
SW (addr + 2, GPR (OP[0] + 1));
INC_ADDR (OP[1], 4);
- trace_output_void ();
+ trace_output_void (sd);
}
/* st2w */
void
-OP_6E01 (void)
+OP_6E01 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 addr = GPR (OP[1]);
trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
@@ -2951,18 +2950,18 @@ OP_6E01 (void)
{
State.exception = SIG_D10V_BUS;
State.pc_changed = 1; /* Don't increment the PC. */
- trace_output_void ();
+ trace_output_void (sd);
return;
}
SW (addr + 0, GPR (OP[0] + 0));
SW (addr + 2, GPR (OP[0] + 1));
INC_ADDR (OP[1], -4);
- trace_output_void ();
+ trace_output_void (sd);
}
/* st2w */
void
-OP_37010000 (void)
+OP_37010000 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 addr = OP[1];
trace_input ("st2w", OP_DREG, OP_MEMREF3, OP_VOID);
@@ -2970,44 +2969,44 @@ OP_37010000 (void)
{
State.exception = SIG_D10V_BUS;
State.pc_changed = 1; /* Don't increment the PC. */
- trace_output_void ();
+ trace_output_void (sd);
return;
}
SW (addr + 0, GPR (OP[0] + 0));
SW (addr + 2, GPR (OP[0] + 1));
- trace_output_void ();
+ trace_output_void (sd);
}
/* stb */
void
-OP_3C000000 (void)
+OP_3C000000 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
SB (GPR (OP[2]) + OP[1], GPR (OP[0]));
- trace_output_void ();
+ trace_output_void (sd);
}
/* stb */
void
-OP_7800 (void)
+OP_7800 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
SB (GPR (OP[1]), GPR (OP[0]));
- trace_output_void ();
+ trace_output_void (sd);
}
/* stop */
void
-OP_5FE0 (void)
+OP_5FE0 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
State.exception = SIG_D10V_STOP;
- trace_output_void ();
+ trace_output_void (sd);
}
/* sub */
void
-OP_0 (void)
+OP_0 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = GPR (OP[0]);
uint16 b = GPR (OP[1]);
@@ -3017,12 +3016,12 @@ OP_0 (void)
compute the carry/overflow bits. */
SET_PSW_C (a >= b);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* sub */
void
-OP_1001 (void)
+OP_1001 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
@@ -3041,13 +3040,13 @@ OP_1001 (void)
tmp = (tmp & MASK40);
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* sub */
void
-OP_1003 (void)
+OP_1003 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
@@ -3066,12 +3065,12 @@ OP_1003 (void)
tmp = (tmp & MASK40);
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* sub2w */
void
-OP_1000 (void)
+OP_1000 (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 tmp, a, b;
@@ -3083,36 +3082,36 @@ OP_1000 (void)
tmp = a - b;
SET_PSW_C (a >= b);
SET_GPR32 (OP[0], tmp);
- trace_output_32 (tmp);
+ trace_output_32 (sd, tmp);
}
/* subac3 */
void
-OP_17000000 (void)
+OP_17000000 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40 (ACC (OP[2]));
SET_GPR32 (OP[0], tmp);
- trace_output_32 (tmp);
+ trace_output_32 (sd, tmp);
}
/* subac3 */
void
-OP_17000002 (void)
+OP_17000002 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
tmp = SEXT40 (ACC (OP[1])) - SEXT40(ACC (OP[2]));
SET_GPR32 (OP[0], tmp);
- trace_output_32 (tmp);
+ trace_output_32 (sd, tmp);
}
/* subac3s */
void
-OP_17001000 (void)
+OP_17001000 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
@@ -3134,12 +3133,12 @@ OP_17001000 (void)
SET_PSW_F0 (0);
}
SET_GPR32 (OP[0], tmp);
- trace_output_32 (tmp);
+ trace_output_32 (sd, tmp);
}
/* subac3s */
void
-OP_17001002 (void)
+OP_17001002 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
@@ -3161,12 +3160,12 @@ OP_17001002 (void)
SET_PSW_F0 (0);
}
SET_GPR32 (OP[0], tmp);
- trace_output_32 (tmp);
+ trace_output_32 (sd, tmp);
}
/* subi */
void
-OP_1 (void)
+OP_1 (SIM_DESC sd, SIM_CPU *cpu)
{
unsigned tmp;
if (OP[1] == 0)
@@ -3180,15 +3179,15 @@ OP_1 (void)
+ (unsigned)(unsigned16) ( - OP[1]));
SET_PSW_C (tmp >= (1 << 16));
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* trap */
void
-OP_5F00 (void)
+OP_5F00 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
- trace_output_void ();
+ trace_output_void (sd);
switch (OP[0])
{
@@ -3254,7 +3253,7 @@ OP_5F00 (void)
/* Turn a pointer in a register into a pointer into real memory. */
-#define MEMPTR(x) ((char *)(dmem_addr(x)))
+#define MEMPTR(x) ((char *)(dmem_addr (sd, cpu, x)))
switch (FUNC)
{
@@ -3262,21 +3261,21 @@ OP_5F00 (void)
case TARGET_SYS_fork:
trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
RETVAL (fork ());
- trace_output_16 (result);
+ trace_output_16 (sd, result);
break;
#define getpid() 47
case TARGET_SYS_getpid:
trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
RETVAL (getpid ());
- trace_output_16 (result);
+ trace_output_16 (sd, result);
break;
case TARGET_SYS_kill:
trace_input ("<kill>", OP_R0, OP_R1, OP_VOID);
if (PARM1 == getpid ())
{
- trace_output_void ();
+ trace_output_void (sd);
State.exception = PARM2;
}
else
@@ -3387,7 +3386,7 @@ OP_5F00 (void)
if (os_sig == -1)
{
- trace_output_void ();
+ trace_output_void (sd);
(*d10v_callback->printf_filtered) (d10v_callback, "Unknown signal %d\n", PARM2);
(*d10v_callback->flush_stdout) (d10v_callback);
State.exception = SIGILL;
@@ -3395,7 +3394,7 @@ OP_5F00 (void)
else
{
RETVAL (kill (PARM1, PARM2));
- trace_output_16 (result);
+ trace_output_16 (sd, result);
}
}
break;
@@ -3404,14 +3403,14 @@ OP_5F00 (void)
trace_input ("<execve>", OP_R0, OP_R1, OP_R2);
RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
(char **)MEMPTR (PARM3)));
- trace_output_16 (result);
+ trace_output_16 (sd, result);
break;
#ifdef TARGET_SYS_execv
case TARGET_SYS_execv:
trace_input ("<execv>", OP_R0, OP_R1, OP_VOID);
RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL));
- trace_output_16 (result);
+ trace_output_16 (sd, result);
break;
#endif
@@ -3426,7 +3425,7 @@ OP_5F00 (void)
SW (buf, host_fd[0]);
buf += sizeof(uint16);
SW (buf, host_fd[1]);
- trace_output_16 (result);
+ trace_output_16 (sd, result);
}
break;
@@ -3439,7 +3438,7 @@ OP_5F00 (void)
RETVAL (wait (&status));
if (PARM1)
SW (PARM1, status);
- trace_output_16 (result);
+ trace_output_16 (sd, result);
}
break;
#endif
@@ -3448,12 +3447,12 @@ OP_5F00 (void)
case TARGET_SYS_getpid:
trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
RETVAL (1);
- trace_output_16 (result);
+ trace_output_16 (sd, result);
break;
case TARGET_SYS_kill:
trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
- trace_output_void ();
+ trace_output_void (sd);
State.exception = PARM2;
break;
#endif
@@ -3462,7 +3461,7 @@ OP_5F00 (void)
trace_input ("<read>", OP_R0, OP_R1, OP_R2);
RETVAL (d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
PARM3));
- trace_output_16 (result);
+ trace_output_16 (sd, result);
break;
case TARGET_SYS_write:
@@ -3473,7 +3472,7 @@ OP_5F00 (void)
else
RETVAL ((int)d10v_callback->write (d10v_callback, PARM1,
MEMPTR (PARM2), PARM3));
- trace_output_16 (result);
+ trace_output_16 (sd, result);
break;
case TARGET_SYS_lseek:
@@ -3482,25 +3481,25 @@ OP_5F00 (void)
((((unsigned long) PARM2) << 16)
|| (unsigned long) PARM3),
PARM4));
- trace_output_32 (result);
+ trace_output_32 (sd, result);
break;
case TARGET_SYS_close:
trace_input ("<close>", OP_R0, OP_VOID, OP_VOID);
RETVAL (d10v_callback->close (d10v_callback, PARM1));
- trace_output_16 (result);
+ trace_output_16 (sd, result);
break;
case TARGET_SYS_open:
trace_input ("<open>", OP_R0, OP_R1, OP_R2);
RETVAL (d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2));
- trace_output_16 (result);
+ trace_output_16 (sd, result);
break;
case TARGET_SYS_exit:
trace_input ("<exit>", OP_R0, OP_VOID, OP_VOID);
State.exception = SIG_D10V_EXIT;
- trace_output_void ();
+ trace_output_void (sd);
break;
#ifdef TARGET_SYS_stat
@@ -3530,20 +3529,20 @@ OP_5F00 (void)
SLW (buf+28, host_stat.st_mtime);
SLW (buf+36, host_stat.st_ctime);
}
- trace_output_16 (result);
+ trace_output_16 (sd, result);
break;
#endif
case TARGET_SYS_chown:
trace_input ("<chown>", OP_R0, OP_R1, OP_R2);
RETVAL (chown (MEMPTR (PARM1), PARM2, PARM3));
- trace_output_16 (result);
+ trace_output_16 (sd, result);
break;
case TARGET_SYS_chmod:
trace_input ("<chmod>", OP_R0, OP_R1, OP_R2);
RETVAL (chmod (MEMPTR (PARM1), PARM2));
- trace_output_16 (result);
+ trace_output_16 (sd, result);
break;
#if 0
@@ -3553,7 +3552,7 @@ OP_5F00 (void)
/* Cast the second argument to void *, to avoid type mismatch
if a prototype is present. */
RETVAL (utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2)));
- trace_output_16 (result);
+ trace_output_16 (sd, result);
break;
#endif
#endif
@@ -3563,7 +3562,7 @@ OP_5F00 (void)
case TARGET_SYS_time:
trace_input ("<time>", OP_R0, OP_R1, OP_R2);
RETVAL32 (time (PARM1 ? MEMPTR (PARM1) : NULL));
- trace_output_32 (result);
+ trace_output_32 (sd, result);
break;
#endif
#endif
@@ -3582,51 +3581,51 @@ OP_5F00 (void)
/* tst0i */
void
-OP_7000000 (void)
+OP_7000000 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
SET_PSW_F1 (PSW_F0);;
SET_PSW_F0 ((GPR (OP[0]) & OP[1]) ? 1 : 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* tst1i */
void
-OP_F000000 (void)
+OP_F000000 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
SET_PSW_F1 (PSW_F0);
SET_PSW_F0 ((~(GPR (OP[0])) & OP[1]) ? 1 : 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* wait */
void
-OP_5F80 (void)
+OP_5F80 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
SET_PSW_IE (1);
- trace_output_void ();
+ trace_output_void (sd);
}
/* xor */
void
-OP_A00 (void)
+OP_A00 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("xor", OP_REG, OP_REG, OP_VOID);
tmp = (GPR (OP[0]) ^ GPR (OP[1]));
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* xor3 */
void
-OP_5000000 (void)
+OP_5000000 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
tmp = (GPR (OP[1]) ^ OP[2]);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
generated by cgit v1.1 at 2024-11-22 18:20:19 +0000