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| author | Michael Meissner <gnu@the-meissners.org> | 1996-09-19 17:23:21 +0000 |
|---|---|---|
| committer | Michael Meissner <gnu@the-meissners.org> | 1996-09-19 17:23:21 +0000 |
| commit | addb61a5b2faa558625249bc18c05dde51ec1809 (patch) | |
| tree | 383cf8c64138cfbc9efb3ab26ecc1f55dc597fb3 /sim/d10v/simops.c | |
| parent | 72f70020f351f17c7e57dd5fcadfc7eb150cb63a (diff) | |
| download | gdb-addb61a5b2faa558625249bc18c05dde51ec1809.zip gdb-addb61a5b2faa558625249bc18c05dde51ec1809.tar.gz gdb-addb61a5b2faa558625249bc18c05dde51ec1809.tar.bz2 | |
Fix tracing info
Diffstat (limited to 'sim/d10v/simops.c')
| -rw-r--r-- | sim/d10v/simops.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/sim/d10v/simops.c b/sim/d10v/simops.c index da60b2c..a1af4f9 100644 --- a/sim/d10v/simops.c +++ b/sim/d10v/simops.c @@ -1197,7 +1197,7 @@ OP_6201 () void OP_6200 () { - trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID); + trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID); State.regs[OP[0]] = RW (State.regs[OP[1]]); State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2); trace_output (OP_REG); |