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| author | Andrew Cagney <cagney@redhat.com> | 1997-12-02 00:27:27 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 1997-12-02 00:27:27 +0000 |
| commit | 51b057f27b7da5dcbb57b118e24ed03f0f8f5034 (patch) | |
| tree | c14ee726e62cdf190624719d04770c0618fe43ef /sim/d10v/simops.c | |
| parent | 3c6d5393c4705b748e27aef0e358164da1f8f252 (diff) | |
| download | gdb-51b057f27b7da5dcbb57b118e24ed03f0f8f5034.zip gdb-51b057f27b7da5dcbb57b118e24ed03f0f8f5034.tar.gz gdb-51b057f27b7da5dcbb57b118e24ed03f0f8f5034.tar.bz2 | |
For sub2w, compute carry according to negated addition rules.
Test.
Diffstat (limited to 'sim/d10v/simops.c')
| -rw-r--r-- | sim/d10v/simops.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/sim/d10v/simops.c b/sim/d10v/simops.c index 222d2d4..d617cb4 100644 --- a/sim/d10v/simops.c +++ b/sim/d10v/simops.c @@ -2483,7 +2483,7 @@ OP_1000 () /* see ../common/sim-alu.h for a more extensive discussion on how to compute the carry/overflow bits */ tmp = a - b; - State.C = (a < b); + State.C = (a >= b); State.regs[OP[0]] = (tmp >> 16) & 0xffff; State.regs[OP[0]+1] = tmp & 0xffff; trace_output (OP_DREG); @@ -2585,7 +2585,8 @@ OP_1 () trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID); /* see ../common/sim-alu.h for a more extensive discussion on how to - compute the carry/overflow bits */ + compute the carry/overflow bits. */ + /* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */ tmp = ((unsigned)(unsigned16) State.regs[OP[0]] + (unsigned)(unsigned16) ( - OP[1])); State.C = (tmp >= (1 << 16)); |