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| author | Michael Meissner <gnu@the-meissners.org> | 1996-09-09 20:45:33 +0000 |
|---|---|---|
| committer | Michael Meissner <gnu@the-meissners.org> | 1996-09-09 20:45:33 +0000 |
| commit | 308f64d3ac2fe556f4f2aee0fbc4e3c8af24f9f3 (patch) | |
| tree | ac8534d04e8ff9870a536eb1597421e49d1751cd /sim/d10v/simops.c | |
| parent | 60fc5b72702bbae4431f6f7b245e586f5fc542be (diff) | |
| download | gdb-308f64d3ac2fe556f4f2aee0fbc4e3c8af24f9f3.zip gdb-308f64d3ac2fe556f4f2aee0fbc4e3c8af24f9f3.tar.gz gdb-308f64d3ac2fe556f4f2aee0fbc4e3c8af24f9f3.tar.bz2 | |
Fix ld2w tracing
Diffstat (limited to 'sim/d10v/simops.c')
| -rw-r--r-- | sim/d10v/simops.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/sim/d10v/simops.c b/sim/d10v/simops.c index 8618b4f..1af4e09 100644 --- a/sim/d10v/simops.c +++ b/sim/d10v/simops.c @@ -1068,7 +1068,7 @@ OP_6000 () void OP_31000000 () { - trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID); + trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID); State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]); State.regs[OP[0]+1] = RW (OP[1] + State.regs[OP[2]] + 2); trace_output (OP_DREG); |