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| author | Andrew Cagney <cagney@redhat.com> | 1997-12-02 05:18:27 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 1997-12-02 05:18:27 +0000 |
| commit | ae55807561cc4c213d1ff8439b831a4bec28b2e2 (patch) | |
| tree | 2f458b450903e087e04e1a2d2948814f16ccb9f4 /sim/d10v/simops.c | |
| parent | 8b9c29f5cbe612e040212ddb899abf7a673ade35 (diff) | |
| download | gdb-ae55807561cc4c213d1ff8439b831a4bec28b2e2.zip gdb-ae55807561cc4c213d1ff8439b831a4bec28b2e2.tar.gz gdb-ae55807561cc4c213d1ff8439b831a4bec28b2e2.tar.bz2 | |
For MACU add unsigned multiply to accumulator.
Test.
Diffstat (limited to 'sim/d10v/simops.c')
| -rw-r--r-- | sim/d10v/simops.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/sim/d10v/simops.c b/sim/d10v/simops.c index d617cb4..6f12e5a 100644 --- a/sim/d10v/simops.c +++ b/sim/d10v/simops.c @@ -1352,13 +1352,17 @@ OP_1A00 () void OP_3A00 () { - int64 tmp; + uint64 tmp; + uint32 src1; + uint32 src2; trace_input ("macu", OP_ACCUM, OP_REG, OP_REG); - tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]); + src1 = (uint16) State.regs[OP[1]]; + src2 = (uint16) State.regs[OP[2]]; + tmp = src1 * src2; if (State.FX) - tmp = SEXT40( (tmp << 1) & MASK40); - State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40; + tmp = (tmp << 1); + State.a[OP[0]] = (State.a[OP[0]] + tmp) & MASK40; trace_output (OP_ACCUM); } |